1b8021494Sopenharmony_ci// Copyright 2016, VIXL authors 2b8021494Sopenharmony_ci// All rights reserved. 3b8021494Sopenharmony_ci// 4b8021494Sopenharmony_ci// Redistribution and use in source and binary forms, with or without 5b8021494Sopenharmony_ci// modification, are permitted provided that the following conditions are met: 6b8021494Sopenharmony_ci// 7b8021494Sopenharmony_ci// * Redistributions of source code must retain the above copyright notice, 8b8021494Sopenharmony_ci// this list of conditions and the following disclaimer. 9b8021494Sopenharmony_ci// * Redistributions in binary form must reproduce the above copyright notice, 10b8021494Sopenharmony_ci// this list of conditions and the following disclaimer in the documentation 11b8021494Sopenharmony_ci// and/or other materials provided with the distribution. 12b8021494Sopenharmony_ci// * Neither the name of ARM Limited nor the names of its contributors may be 13b8021494Sopenharmony_ci// used to endorse or promote products derived from this software without 14b8021494Sopenharmony_ci// specific prior written permission. 15b8021494Sopenharmony_ci// 16b8021494Sopenharmony_ci// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17b8021494Sopenharmony_ci// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18b8021494Sopenharmony_ci// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19b8021494Sopenharmony_ci// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20b8021494Sopenharmony_ci// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21b8021494Sopenharmony_ci// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22b8021494Sopenharmony_ci// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23b8021494Sopenharmony_ci// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24b8021494Sopenharmony_ci// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25b8021494Sopenharmony_ci// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26b8021494Sopenharmony_ci 27b8021494Sopenharmony_ci// Test description for instructions of the following forms: 28b8021494Sopenharmony_ci// MNEMONIC{<c>}.N <Rd>, <Rn>, #0 29b8021494Sopenharmony_ci// MNEMONIC{<c>}.N <Rd>, <Rn>, #<imm3> 30b8021494Sopenharmony_ci// MNEMONIC{<c>}.N <Rdn>, <Rdn>, #<imm8> 31b8021494Sopenharmony_ci 32b8021494Sopenharmony_ci{ 33b8021494Sopenharmony_ci "mnemonics" : [ 34b8021494Sopenharmony_ci "Add", // ADD<c>{<q>} <Rd>, <Rn>, #<imm3> ; T1 35b8021494Sopenharmony_ci // ADD<c>{<q>} <Rdn>, #<imm8> ; T2 36b8021494Sopenharmony_ci // ADD<c>{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2 37b8021494Sopenharmony_ci "Adds", // ADDS{<q>} <Rd>, <Rn>, #<imm3> ; T1 38b8021494Sopenharmony_ci // ADDS{<q>} <Rdn>, #<imm8> ; T2 39b8021494Sopenharmony_ci // ADDS{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2 40b8021494Sopenharmony_ci "Rsb", // RSB<c>{<q>} {<Rd>}, <Rn>, #0 ; T1 41b8021494Sopenharmony_ci "Rsbs", // RSBS{<q>} {<Rd>}, <Rn>, #0 ; T1 42b8021494Sopenharmony_ci "Sub", // SUB<c>{<q>} <Rd>, <Rn>, #<imm3> ; T1 43b8021494Sopenharmony_ci // SUB<c>{<q>} <Rdn>, #<imm8> ; T2 44b8021494Sopenharmony_ci // SUB<c>{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2 45b8021494Sopenharmony_ci "Subs" // SUBS{<q>} <Rd>, <Rn>, #<imm3> ; T1 46b8021494Sopenharmony_ci // SUBS{<q>} <Rdn>, #<imm8> ; T2 47b8021494Sopenharmony_ci // SUBS{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2 48b8021494Sopenharmony_ci ], 49b8021494Sopenharmony_ci "description" : { 50b8021494Sopenharmony_ci "operands": [ 51b8021494Sopenharmony_ci { 52b8021494Sopenharmony_ci "name": "cond", 53b8021494Sopenharmony_ci "type": "Condition" 54b8021494Sopenharmony_ci }, 55b8021494Sopenharmony_ci { 56b8021494Sopenharmony_ci "name": "rd", 57b8021494Sopenharmony_ci "type": "LowRegisters" 58b8021494Sopenharmony_ci }, 59b8021494Sopenharmony_ci { 60b8021494Sopenharmony_ci "name": "rn", 61b8021494Sopenharmony_ci "type": "LowRegisters" 62b8021494Sopenharmony_ci }, 63b8021494Sopenharmony_ci { 64b8021494Sopenharmony_ci "name": "op", 65b8021494Sopenharmony_ci "wrapper": "Operand", 66b8021494Sopenharmony_ci "operands": [ 67b8021494Sopenharmony_ci { 68b8021494Sopenharmony_ci "name": "immediate", 69b8021494Sopenharmony_ci "type": "OffsetLowerThan256" 70b8021494Sopenharmony_ci } 71b8021494Sopenharmony_ci ] 72b8021494Sopenharmony_ci } 73b8021494Sopenharmony_ci ], 74b8021494Sopenharmony_ci "inputs": [ 75b8021494Sopenharmony_ci { 76b8021494Sopenharmony_ci "name": "apsr", 77b8021494Sopenharmony_ci "type": "NZCV" 78b8021494Sopenharmony_ci }, 79b8021494Sopenharmony_ci { 80b8021494Sopenharmony_ci "name": "rd", 81b8021494Sopenharmony_ci "type": "Register" 82b8021494Sopenharmony_ci }, 83b8021494Sopenharmony_ci { 84b8021494Sopenharmony_ci "name": "rn", 85b8021494Sopenharmony_ci "type": "Register" 86b8021494Sopenharmony_ci } 87b8021494Sopenharmony_ci ] 88b8021494Sopenharmony_ci }, 89b8021494Sopenharmony_ci "test-files": [ 90b8021494Sopenharmony_ci { 91b8021494Sopenharmony_ci "type": "simulator", 92b8021494Sopenharmony_ci "test-cases": [ 93b8021494Sopenharmony_ci { 94b8021494Sopenharmony_ci "name": "RdIsRn", 95b8021494Sopenharmony_ci "operands": [ 96b8021494Sopenharmony_ci "cond", "rd", "rn", "immediate" 97b8021494Sopenharmony_ci ], 98b8021494Sopenharmony_ci "inputs": [ 99b8021494Sopenharmony_ci "apsr", "rd", "rn" 100b8021494Sopenharmony_ci ], 101b8021494Sopenharmony_ci "operand-filter": "rd == rn", 102b8021494Sopenharmony_ci "operand-limit": 20, 103b8021494Sopenharmony_ci "input-filter": "rd == rn", 104b8021494Sopenharmony_ci "input-limit": 300 105b8021494Sopenharmony_ci }, 106b8021494Sopenharmony_ci { 107b8021494Sopenharmony_ci "name": "RdIsNotRn", 108b8021494Sopenharmony_ci "operands": [ 109b8021494Sopenharmony_ci "cond", "rd", "rn", "immediate" 110b8021494Sopenharmony_ci ], 111b8021494Sopenharmony_ci "inputs": [ 112b8021494Sopenharmony_ci "apsr", "rd", "rn" 113b8021494Sopenharmony_ci ], 114b8021494Sopenharmony_ci "operand-filter": "rd != rn", 115b8021494Sopenharmony_ci "operand-limit": 20, 116b8021494Sopenharmony_ci "input-limit": 300 117b8021494Sopenharmony_ci }, 118b8021494Sopenharmony_ci { 119b8021494Sopenharmony_ci "name": "Immediate", 120b8021494Sopenharmony_ci "operands": [ 121b8021494Sopenharmony_ci "cond", "immediate" 122b8021494Sopenharmony_ci ], 123b8021494Sopenharmony_ci "inputs": [ 124b8021494Sopenharmony_ci "apsr", "rn" 125b8021494Sopenharmony_ci ], 126b8021494Sopenharmony_ci "operand-limit": 20, 127b8021494Sopenharmony_ci "input-limit": 300 128b8021494Sopenharmony_ci } 129b8021494Sopenharmony_ci ] 130b8021494Sopenharmony_ci }, 131b8021494Sopenharmony_ci // Test encodings with an 8 bit immediate and identical rn and rd. 132b8021494Sopenharmony_ci { 133b8021494Sopenharmony_ci "name": "imm8", 134b8021494Sopenharmony_ci "type": "assembler", 135b8021494Sopenharmony_ci "mnemonics" : [ 136b8021494Sopenharmony_ci "Adds", // ADDS{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2 137b8021494Sopenharmony_ci "Subs" // SUBS{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2 138b8021494Sopenharmony_ci ], 139b8021494Sopenharmony_ci "test-cases": [ 140b8021494Sopenharmony_ci { 141b8021494Sopenharmony_ci "name": "OutItBlock", 142b8021494Sopenharmony_ci "operands": [ 143b8021494Sopenharmony_ci "cond", "rd", "rn", "immediate" 144b8021494Sopenharmony_ci ], 145b8021494Sopenharmony_ci "operand-filter": "cond == 'al' and rd == rn" 146b8021494Sopenharmony_ci } 147b8021494Sopenharmony_ci ] 148b8021494Sopenharmony_ci }, 149b8021494Sopenharmony_ci { 150b8021494Sopenharmony_ci "name": "imm8-in-it-block", 151b8021494Sopenharmony_ci "type": "assembler", 152b8021494Sopenharmony_ci "mnemonics" : [ 153b8021494Sopenharmony_ci "Add", // ADD<c>{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2 154b8021494Sopenharmony_ci "Sub" // SUB<c>{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2 155b8021494Sopenharmony_ci ], 156b8021494Sopenharmony_ci "test-cases": [ 157b8021494Sopenharmony_ci { 158b8021494Sopenharmony_ci "name": "InITBlock", 159b8021494Sopenharmony_ci "operands": [ 160b8021494Sopenharmony_ci "cond", "rd", "rn", "immediate" 161b8021494Sopenharmony_ci ], 162b8021494Sopenharmony_ci // Generate an extra IT instruction. 163b8021494Sopenharmony_ci "in-it-block": "{cond}", 164b8021494Sopenharmony_ci "operand-filter": "cond != 'al' and rd == rn", 165b8021494Sopenharmony_ci "operand-limit": 1000 166b8021494Sopenharmony_ci } 167b8021494Sopenharmony_ci ] 168b8021494Sopenharmony_ci }, 169b8021494Sopenharmony_ci // Test encodings with a 3 bit immediate and different rn and rd. 170b8021494Sopenharmony_ci { 171b8021494Sopenharmony_ci "name": "imm3", 172b8021494Sopenharmony_ci "type": "assembler", 173b8021494Sopenharmony_ci "mnemonics" : [ 174b8021494Sopenharmony_ci "Adds", // ADDS{<q>} <Rd>, <Rn>, #<imm3> ; T1 175b8021494Sopenharmony_ci "Subs" // SUBS{<q>} <Rd>, <Rn>, #<imm3> ; T1 176b8021494Sopenharmony_ci ], 177b8021494Sopenharmony_ci "test-cases": [ 178b8021494Sopenharmony_ci { 179b8021494Sopenharmony_ci "name": "OutITBlock", 180b8021494Sopenharmony_ci "operands": [ 181b8021494Sopenharmony_ci "cond", "rd", "rn", "immediate" 182b8021494Sopenharmony_ci ], 183b8021494Sopenharmony_ci "operand-filter": "cond == 'al' and int(immediate) <= 7" 184b8021494Sopenharmony_ci } 185b8021494Sopenharmony_ci ] 186b8021494Sopenharmony_ci }, 187b8021494Sopenharmony_ci { 188b8021494Sopenharmony_ci "name": "imm3-in-it-block", 189b8021494Sopenharmony_ci "type": "assembler", 190b8021494Sopenharmony_ci "mnemonics" : [ 191b8021494Sopenharmony_ci "Add", // ADD<c>{<q>} <Rd>, <Rn>, #<imm3> ; T1 192b8021494Sopenharmony_ci "Sub" // SUB<c>{<q>} <Rd>, <Rn>, #<imm3> ; T1 193b8021494Sopenharmony_ci ], 194b8021494Sopenharmony_ci "test-cases": [ 195b8021494Sopenharmony_ci { 196b8021494Sopenharmony_ci "name": "InITBlock", 197b8021494Sopenharmony_ci "operands": [ 198b8021494Sopenharmony_ci "cond", "rd", "rn", "immediate" 199b8021494Sopenharmony_ci ], 200b8021494Sopenharmony_ci // Generate an extra IT instruction. 201b8021494Sopenharmony_ci "in-it-block": "{cond}", 202b8021494Sopenharmony_ci "operand-filter": "cond != 'al' and int(immediate) <= 7", 203b8021494Sopenharmony_ci "operand-limit": 1000 204b8021494Sopenharmony_ci } 205b8021494Sopenharmony_ci ] 206b8021494Sopenharmony_ci }, 207b8021494Sopenharmony_ci // Test special cases for Rsb and Rsbs where there is a special 208b8021494Sopenharmony_ci // encoding when the immediate is zero. 209b8021494Sopenharmony_ci { 210b8021494Sopenharmony_ci "name": "zero", 211b8021494Sopenharmony_ci "type": "assembler", 212b8021494Sopenharmony_ci "mnemonics" : [ 213b8021494Sopenharmony_ci "Rsbs" // RSBS{<q>} {<Rd>}, <Rn>, #0 ; T1 214b8021494Sopenharmony_ci ], 215b8021494Sopenharmony_ci "test-cases": [ 216b8021494Sopenharmony_ci { 217b8021494Sopenharmony_ci "name": "OutITBlock", 218b8021494Sopenharmony_ci "operands": [ 219b8021494Sopenharmony_ci "cond", "rd", "rn", "immediate" 220b8021494Sopenharmony_ci ], 221b8021494Sopenharmony_ci "operand-filter": "cond == 'al' and int(immediate) == 0" 222b8021494Sopenharmony_ci } 223b8021494Sopenharmony_ci ] 224b8021494Sopenharmony_ci }, 225b8021494Sopenharmony_ci { 226b8021494Sopenharmony_ci "name": "zero-in-it-block", 227b8021494Sopenharmony_ci "type": "assembler", 228b8021494Sopenharmony_ci "mnemonics" : [ 229b8021494Sopenharmony_ci "Rsb" // RSB<c>{<q>} {<Rd>}, <Rn>, #0 ; T1 230b8021494Sopenharmony_ci ], 231b8021494Sopenharmony_ci "test-cases": [ 232b8021494Sopenharmony_ci { 233b8021494Sopenharmony_ci "name": "InITBlock", 234b8021494Sopenharmony_ci "operands": [ 235b8021494Sopenharmony_ci "cond", "rd", "rn", "immediate" 236b8021494Sopenharmony_ci ], 237b8021494Sopenharmony_ci // Generate an extra IT instruction. 238b8021494Sopenharmony_ci "in-it-block": "{cond}", 239b8021494Sopenharmony_ci "operand-filter": "cond != 'al' and int(immediate) == 0" 240b8021494Sopenharmony_ci } 241b8021494Sopenharmony_ci ] 242b8021494Sopenharmony_ci } 243b8021494Sopenharmony_ci ] 244b8021494Sopenharmony_ci} 245