1b8021494Sopenharmony_ci// Copyright 2016, VIXL authors 2b8021494Sopenharmony_ci// All rights reserved. 3b8021494Sopenharmony_ci// 4b8021494Sopenharmony_ci// Redistribution and use in source and binary forms, with or without 5b8021494Sopenharmony_ci// modification, are permitted provided that the following conditions are met: 6b8021494Sopenharmony_ci// 7b8021494Sopenharmony_ci// * Redistributions of source code must retain the above copyright notice, 8b8021494Sopenharmony_ci// this list of conditions and the following disclaimer. 9b8021494Sopenharmony_ci// * Redistributions in binary form must reproduce the above copyright notice, 10b8021494Sopenharmony_ci// this list of conditions and the following disclaimer in the documentation 11b8021494Sopenharmony_ci// and/or other materials provided with the distribution. 12b8021494Sopenharmony_ci// * Neither the name of ARM Limited nor the names of its contributors may be 13b8021494Sopenharmony_ci// used to endorse or promote products derived from this software without 14b8021494Sopenharmony_ci// specific prior written permission. 15b8021494Sopenharmony_ci// 16b8021494Sopenharmony_ci// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17b8021494Sopenharmony_ci// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18b8021494Sopenharmony_ci// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19b8021494Sopenharmony_ci// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20b8021494Sopenharmony_ci// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21b8021494Sopenharmony_ci// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22b8021494Sopenharmony_ci// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23b8021494Sopenharmony_ci// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24b8021494Sopenharmony_ci// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25b8021494Sopenharmony_ci// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26b8021494Sopenharmony_ci 27b8021494Sopenharmony_ci// Test description for instructions of the following form: 28b8021494Sopenharmony_ci// MNEMONIC{<c>}.N <Rdn>, #<imm8> 29b8021494Sopenharmony_ci 30b8021494Sopenharmony_ci{ 31b8021494Sopenharmony_ci "mnemonics" : [ 32b8021494Sopenharmony_ci "Cmp", // CMP{<c>}{<q>} <Rn>, #<imm8> ; T1 33b8021494Sopenharmony_ci "Mov", // MOV<c>{<q>} <Rd>, #<imm8> ; T1 34b8021494Sopenharmony_ci "Movs" // MOVS{<q>} <Rd>, #<imm8> ; T1 35b8021494Sopenharmony_ci ], 36b8021494Sopenharmony_ci "description" : { 37b8021494Sopenharmony_ci "operands": [ 38b8021494Sopenharmony_ci { 39b8021494Sopenharmony_ci "name": "cond", 40b8021494Sopenharmony_ci "type": "Condition" 41b8021494Sopenharmony_ci }, 42b8021494Sopenharmony_ci { 43b8021494Sopenharmony_ci "name": "rd", 44b8021494Sopenharmony_ci "type": "LowRegisters" 45b8021494Sopenharmony_ci }, 46b8021494Sopenharmony_ci { 47b8021494Sopenharmony_ci "name": "op", 48b8021494Sopenharmony_ci "wrapper": "Operand", 49b8021494Sopenharmony_ci "operands": [ 50b8021494Sopenharmony_ci { 51b8021494Sopenharmony_ci "name": "immediate", 52b8021494Sopenharmony_ci "type": "OffsetLowerThan256" 53b8021494Sopenharmony_ci } 54b8021494Sopenharmony_ci ] 55b8021494Sopenharmony_ci } 56b8021494Sopenharmony_ci ], 57b8021494Sopenharmony_ci "inputs": [ 58b8021494Sopenharmony_ci { 59b8021494Sopenharmony_ci "name": "apsr", 60b8021494Sopenharmony_ci "type": "NZCV" 61b8021494Sopenharmony_ci }, 62b8021494Sopenharmony_ci { 63b8021494Sopenharmony_ci "name": "rd", 64b8021494Sopenharmony_ci "type": "Register" 65b8021494Sopenharmony_ci } 66b8021494Sopenharmony_ci ] 67b8021494Sopenharmony_ci }, 68b8021494Sopenharmony_ci "test-files": [ 69b8021494Sopenharmony_ci { 70b8021494Sopenharmony_ci "type": "assembler", 71b8021494Sopenharmony_ci "test-cases": [ 72b8021494Sopenharmony_ci { 73b8021494Sopenharmony_ci "name": "Unconditional", 74b8021494Sopenharmony_ci "operands": [ 75b8021494Sopenharmony_ci "cond", "rd", "immediate" 76b8021494Sopenharmony_ci ], 77b8021494Sopenharmony_ci "operand-filter": "cond == 'al'" 78b8021494Sopenharmony_ci } 79b8021494Sopenharmony_ci ] 80b8021494Sopenharmony_ci }, 81b8021494Sopenharmony_ci { 82b8021494Sopenharmony_ci "name": "in-it-block", 83b8021494Sopenharmony_ci "type": "assembler", 84b8021494Sopenharmony_ci "mnemonics" : [ 85b8021494Sopenharmony_ci "Cmp", // CMP{<c>}{<q>} <Rn>, #<imm8> ; T1 86b8021494Sopenharmony_ci "Mov" // MOV<c>{<q>} <Rd>, #<imm8> ; T1 87b8021494Sopenharmony_ci ], 88b8021494Sopenharmony_ci "test-cases": [ 89b8021494Sopenharmony_ci { 90b8021494Sopenharmony_ci "name": "InITBlock", 91b8021494Sopenharmony_ci "operands": [ 92b8021494Sopenharmony_ci "cond", "rd", "immediate" 93b8021494Sopenharmony_ci ], 94b8021494Sopenharmony_ci // Generate an extra IT instruction. 95b8021494Sopenharmony_ci "in-it-block": "{cond}", 96b8021494Sopenharmony_ci "operand-filter": "cond != 'al'", 97b8021494Sopenharmony_ci "operand-limit": 1000 98b8021494Sopenharmony_ci } 99b8021494Sopenharmony_ci ] 100b8021494Sopenharmony_ci }, 101b8021494Sopenharmony_ci { 102b8021494Sopenharmony_ci "type": "simulator", 103b8021494Sopenharmony_ci "test-cases": [ 104b8021494Sopenharmony_ci { 105b8021494Sopenharmony_ci "name": "Condition", 106b8021494Sopenharmony_ci "operands": [ 107b8021494Sopenharmony_ci "cond" 108b8021494Sopenharmony_ci ], 109b8021494Sopenharmony_ci "inputs": [ 110b8021494Sopenharmony_ci "apsr" 111b8021494Sopenharmony_ci ] 112b8021494Sopenharmony_ci }, 113b8021494Sopenharmony_ci { 114b8021494Sopenharmony_ci "name": "ModifiedImmediate", 115b8021494Sopenharmony_ci "operands": [ 116b8021494Sopenharmony_ci "immediate" 117b8021494Sopenharmony_ci ], 118b8021494Sopenharmony_ci "inputs": [ 119b8021494Sopenharmony_ci "rd" 120b8021494Sopenharmony_ci ] 121b8021494Sopenharmony_ci } 122b8021494Sopenharmony_ci ] 123b8021494Sopenharmony_ci } 124b8021494Sopenharmony_ci ] 125b8021494Sopenharmony_ci} 126