1b8021494Sopenharmony_ci// Copyright 2016, VIXL authors 2b8021494Sopenharmony_ci// All rights reserved. 3b8021494Sopenharmony_ci// 4b8021494Sopenharmony_ci// Redistribution and use in source and binary forms, with or without 5b8021494Sopenharmony_ci// modification, are permitted provided that the following conditions are met: 6b8021494Sopenharmony_ci// 7b8021494Sopenharmony_ci// * Redistributions of source code must retain the above copyright notice, 8b8021494Sopenharmony_ci// this list of conditions and the following disclaimer. 9b8021494Sopenharmony_ci// * Redistributions in binary form must reproduce the above copyright notice, 10b8021494Sopenharmony_ci// this list of conditions and the following disclaimer in the documentation 11b8021494Sopenharmony_ci// and/or other materials provided with the distribution. 12b8021494Sopenharmony_ci// * Neither the name of ARM Limited nor the names of its contributors may be 13b8021494Sopenharmony_ci// used to endorse or promote products derived from this software without 14b8021494Sopenharmony_ci// specific prior written permission. 15b8021494Sopenharmony_ci// 16b8021494Sopenharmony_ci// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17b8021494Sopenharmony_ci// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18b8021494Sopenharmony_ci// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19b8021494Sopenharmony_ci// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20b8021494Sopenharmony_ci// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21b8021494Sopenharmony_ci// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22b8021494Sopenharmony_ci// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23b8021494Sopenharmony_ci// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24b8021494Sopenharmony_ci// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25b8021494Sopenharmony_ci// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26b8021494Sopenharmony_ci 27b8021494Sopenharmony_ci// Test description for instructions of the following form: 28b8021494Sopenharmony_ci// MNEMONIC{<c>}.N <Rd>, <Rm> 29b8021494Sopenharmony_ci// MNEMONIC{<c>}.W <Rd>, <Rm> 30b8021494Sopenharmony_ci 31b8021494Sopenharmony_ci{ 32b8021494Sopenharmony_ci "mnemonics" : [ 33b8021494Sopenharmony_ci "Clz", // CLZ{<c>}{<q>} <Rd>, <Rm> ; T1 34b8021494Sopenharmony_ci "Rbit", // RBIT{<c>}{<q>} <Rd>, <Rm> ; T1 35b8021494Sopenharmony_ci "Rev", // REV{<c>}{<q>} <Rd>, <Rm> ; T1 36b8021494Sopenharmony_ci // REV{<c>}{<q>} <Rd>, <Rm> ; T2 37b8021494Sopenharmony_ci "Rev16", // REV16{<c>}{<q>} <Rd>, <Rm> ; T1 38b8021494Sopenharmony_ci // REV16{<c>}{<q>} <Rd>, <Rm> ; T2 39b8021494Sopenharmony_ci "Revsh", // REVSH{<c>}{<q>} <Rd>, <Rm> ; T1 40b8021494Sopenharmony_ci // REVSH{<c>}{<q>} <Rd>, <Rm> ; T2 41b8021494Sopenharmony_ci "Rrx", // RRX{<c>}{<q>} {<Rd>}, <Rm> ; T3 42b8021494Sopenharmony_ci "Rrxs" // RRXS{<c>}{<q>} {<Rd>}, <Rm> ; T3 43b8021494Sopenharmony_ci ], 44b8021494Sopenharmony_ci "description" : { 45b8021494Sopenharmony_ci "operands": [ 46b8021494Sopenharmony_ci { 47b8021494Sopenharmony_ci "name": "cond", 48b8021494Sopenharmony_ci "type": "Condition" 49b8021494Sopenharmony_ci }, 50b8021494Sopenharmony_ci { 51b8021494Sopenharmony_ci "name": "rd", 52b8021494Sopenharmony_ci "type": "AllRegistersButPC" 53b8021494Sopenharmony_ci }, 54b8021494Sopenharmony_ci { 55b8021494Sopenharmony_ci "name": "rn", 56b8021494Sopenharmony_ci "type": "AllRegistersButPC" 57b8021494Sopenharmony_ci } 58b8021494Sopenharmony_ci ], 59b8021494Sopenharmony_ci "inputs": [ 60b8021494Sopenharmony_ci { 61b8021494Sopenharmony_ci "name": "apsr", 62b8021494Sopenharmony_ci "type": "NZCV" 63b8021494Sopenharmony_ci }, 64b8021494Sopenharmony_ci { 65b8021494Sopenharmony_ci "name": "rd", 66b8021494Sopenharmony_ci "type": "Register" 67b8021494Sopenharmony_ci }, 68b8021494Sopenharmony_ci { 69b8021494Sopenharmony_ci "name": "rn", 70b8021494Sopenharmony_ci "type": "Register" 71b8021494Sopenharmony_ci } 72b8021494Sopenharmony_ci ] 73b8021494Sopenharmony_ci }, 74b8021494Sopenharmony_ci "test-files": [ 75b8021494Sopenharmony_ci { 76b8021494Sopenharmony_ci "type": "assembler", 77b8021494Sopenharmony_ci "test-cases": [ 78b8021494Sopenharmony_ci { 79b8021494Sopenharmony_ci "name": "Unconditional", 80b8021494Sopenharmony_ci "operands": [ 81b8021494Sopenharmony_ci "cond", "rd", "rn" 82b8021494Sopenharmony_ci ], 83b8021494Sopenharmony_ci "operand-filter": "cond == 'al'" 84b8021494Sopenharmony_ci } 85b8021494Sopenharmony_ci ] 86b8021494Sopenharmony_ci }, 87b8021494Sopenharmony_ci { 88b8021494Sopenharmony_ci "type": "macro-assembler", 89b8021494Sopenharmony_ci "test-cases": [ 90b8021494Sopenharmony_ci { 91b8021494Sopenharmony_ci "name": "Operands", 92b8021494Sopenharmony_ci "operands": [ 93b8021494Sopenharmony_ci "cond", "rd", "rn" 94b8021494Sopenharmony_ci ], 95b8021494Sopenharmony_ci "operand-limit": 500 96b8021494Sopenharmony_ci } 97b8021494Sopenharmony_ci ] 98b8021494Sopenharmony_ci }, 99b8021494Sopenharmony_ci { 100b8021494Sopenharmony_ci "type": "simulator", 101b8021494Sopenharmony_ci "test-cases": [ 102b8021494Sopenharmony_ci { 103b8021494Sopenharmony_ci "name": "Condition", 104b8021494Sopenharmony_ci "operands": [ 105b8021494Sopenharmony_ci "cond" 106b8021494Sopenharmony_ci ], 107b8021494Sopenharmony_ci "inputs": [ 108b8021494Sopenharmony_ci "apsr" 109b8021494Sopenharmony_ci ] 110b8021494Sopenharmony_ci }, 111b8021494Sopenharmony_ci // Test combinations of registers values with rd == rn. 112b8021494Sopenharmony_ci { 113b8021494Sopenharmony_ci "name": "RdIsRn", 114b8021494Sopenharmony_ci "operands": [ 115b8021494Sopenharmony_ci "rd", "rn" 116b8021494Sopenharmony_ci ], 117b8021494Sopenharmony_ci "inputs": [ 118b8021494Sopenharmony_ci "rd", "rn" 119b8021494Sopenharmony_ci ], 120b8021494Sopenharmony_ci "operand-filter": "rd == rn", 121b8021494Sopenharmony_ci "input-filter": "rd == rn" 122b8021494Sopenharmony_ci }, 123b8021494Sopenharmony_ci // Test combinations of registers values with rd != rn. 124b8021494Sopenharmony_ci { 125b8021494Sopenharmony_ci "name": "RdIsNotRn", 126b8021494Sopenharmony_ci "operands": [ 127b8021494Sopenharmony_ci "rd", "rn" 128b8021494Sopenharmony_ci ], 129b8021494Sopenharmony_ci "inputs": [ 130b8021494Sopenharmony_ci "rd", "rn" 131b8021494Sopenharmony_ci ], 132b8021494Sopenharmony_ci "operand-filter": "rd != rn", 133b8021494Sopenharmony_ci "operand-limit": 10, 134b8021494Sopenharmony_ci "input-filter": "rd != rn" 135b8021494Sopenharmony_ci } 136b8021494Sopenharmony_ci ] 137b8021494Sopenharmony_ci } 138b8021494Sopenharmony_ci ] 139b8021494Sopenharmony_ci} 140