1b8021494Sopenharmony_ci// Copyright 2016, VIXL authors
2b8021494Sopenharmony_ci// All rights reserved.
3b8021494Sopenharmony_ci//
4b8021494Sopenharmony_ci// Redistribution and use in source and binary forms, with or without
5b8021494Sopenharmony_ci// modification, are permitted provided that the following conditions are met:
6b8021494Sopenharmony_ci//
7b8021494Sopenharmony_ci//   * Redistributions of source code must retain the above copyright notice,
8b8021494Sopenharmony_ci//     this list of conditions and the following disclaimer.
9b8021494Sopenharmony_ci//   * Redistributions in binary form must reproduce the above copyright notice,
10b8021494Sopenharmony_ci//     this list of conditions and the following disclaimer in the documentation
11b8021494Sopenharmony_ci//     and/or other materials provided with the distribution.
12b8021494Sopenharmony_ci//   * Neither the name of ARM Limited nor the names of its contributors may be
13b8021494Sopenharmony_ci//     used to endorse or promote products derived from this software without
14b8021494Sopenharmony_ci//     specific prior written permission.
15b8021494Sopenharmony_ci//
16b8021494Sopenharmony_ci// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
17b8021494Sopenharmony_ci// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18b8021494Sopenharmony_ci// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19b8021494Sopenharmony_ci// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
20b8021494Sopenharmony_ci// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21b8021494Sopenharmony_ci// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22b8021494Sopenharmony_ci// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
23b8021494Sopenharmony_ci// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24b8021494Sopenharmony_ci// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25b8021494Sopenharmony_ci// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26b8021494Sopenharmony_ci
27b8021494Sopenharmony_ci// Test description for instructions of the following forms:
28b8021494Sopenharmony_ci//   MNEMONIC{<c>}.W <Rd>, <Rn>, <Rm>
29b8021494Sopenharmony_ci//   MNEMONIC{<c>}.W <Rd>, SP, <Rm>
30b8021494Sopenharmony_ci//   MNEMONIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> }
31b8021494Sopenharmony_ci//   MNEMONIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> }
32b8021494Sopenharmony_ci//
33b8021494Sopenharmony_ci//   MNEMONIC{<c>}.N <Rdm>, SP, <Rdm>
34b8021494Sopenharmony_ci//   MNEMONIC{<c>}.N SP, SP, <Rm>
35b8021494Sopenharmony_ci//   MNEMONIC{<c>}.N <Rd>, <Rn>, <Rm>
36b8021494Sopenharmony_ci//   MNEMONIC{<c>}.N <Rdn>, <Rdn>, <Rm> ; rm is not SP
37b8021494Sopenharmony_ci//   MNEMONIC{<c>}.N <Rdn>, <Rdn>, <Rm> ; low registers
38b8021494Sopenharmony_ci//
39b8021494Sopenharmony_ci// Note that this test only covers the cases where the optional shift
40b8021494Sopenharmony_ci// operand is not provided. The shift operands are tested in
41b8021494Sopenharmony_ci// "cond-rd-rn-operand-rm-shift-amount-*-t32.json".
42b8021494Sopenharmony_ci
43b8021494Sopenharmony_ci{
44b8021494Sopenharmony_ci  "mnemonics": [
45b8021494Sopenharmony_ci    "Adc",  // ADC<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
46b8021494Sopenharmony_ci            // ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
47b8021494Sopenharmony_ci
48b8021494Sopenharmony_ci    "Adcs", // ADCS{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
49b8021494Sopenharmony_ci            // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
50b8021494Sopenharmony_ci
51b8021494Sopenharmony_ci    "Add",  // ADD<c>{<q>} <Rd>, <Rn>, <Rm> ; T1
52b8021494Sopenharmony_ci            // ADD<c>{<q>} <Rdn>, <Rm> ; T2
53b8021494Sopenharmony_ci            // ADD{<c>}{<q>} {<Rdn>}, <Rdn>, <Rm> ; T2
54b8021494Sopenharmony_ci            // ADD{<c>}{<q>} {<Rdm>}, SP, <Rdm> ; T1
55b8021494Sopenharmony_ci            // ADD{<c>}{<q>} {SP}, SP, <Rm> ; T2
56b8021494Sopenharmony_ci            // ADD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T3
57b8021494Sopenharmony_ci            // ADD{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T3
58b8021494Sopenharmony_ci
59b8021494Sopenharmony_ci    "Adds", // ADDS{<q>} {<Rd>}, <Rn>, <Rm> ; T1
60b8021494Sopenharmony_ci            // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T3
61b8021494Sopenharmony_ci            // ADDS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T3
62b8021494Sopenharmony_ci
63b8021494Sopenharmony_ci    "And",  // AND<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
64b8021494Sopenharmony_ci            // AND{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
65b8021494Sopenharmony_ci
66b8021494Sopenharmony_ci    "Ands", // ANDS{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
67b8021494Sopenharmony_ci            // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
68b8021494Sopenharmony_ci
69b8021494Sopenharmony_ci    "Bic",  // BIC<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
70b8021494Sopenharmony_ci            // BIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
71b8021494Sopenharmony_ci
72b8021494Sopenharmony_ci    "Bics", // BICS{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
73b8021494Sopenharmony_ci            // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
74b8021494Sopenharmony_ci
75b8021494Sopenharmony_ci    "Eor",  // EOR<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
76b8021494Sopenharmony_ci            // EOR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
77b8021494Sopenharmony_ci
78b8021494Sopenharmony_ci    "Eors", // EORS{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
79b8021494Sopenharmony_ci            // EORS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
80b8021494Sopenharmony_ci
81b8021494Sopenharmony_ci    "Orn",  // ORN{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T1
82b8021494Sopenharmony_ci
83b8021494Sopenharmony_ci    "Orns", // ORNS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T1
84b8021494Sopenharmony_ci
85b8021494Sopenharmony_ci    "Orr",  // ORR<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
86b8021494Sopenharmony_ci            // ORR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
87b8021494Sopenharmony_ci
88b8021494Sopenharmony_ci    "Orrs", // ORRS{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
89b8021494Sopenharmony_ci            // ORRS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
90b8021494Sopenharmony_ci
91b8021494Sopenharmony_ci    "Rsb",  // RSB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T1
92b8021494Sopenharmony_ci
93b8021494Sopenharmony_ci    "Rsbs", // RSBS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T1
94b8021494Sopenharmony_ci
95b8021494Sopenharmony_ci    "Sbc",  // SBC<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
96b8021494Sopenharmony_ci            // SBC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
97b8021494Sopenharmony_ci
98b8021494Sopenharmony_ci    "Sbcs", // SBCS{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
99b8021494Sopenharmony_ci            // SBCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
100b8021494Sopenharmony_ci
101b8021494Sopenharmony_ci    "Sub",  // SUB<c>{<q>} <Rd>, <Rn>, <Rm> ; T1
102b8021494Sopenharmony_ci            // SUB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
103b8021494Sopenharmony_ci            // SUB{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T1
104b8021494Sopenharmony_ci            // SUB{<c>} {<Rd>}, SP, <Rm> ; T1
105b8021494Sopenharmony_ci
106b8021494Sopenharmony_ci    "Subs", // SUBS{<q>} {<Rd>}, <Rn>, <Rm> ; T1
107b8021494Sopenharmony_ci            // SUBS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
108b8021494Sopenharmony_ci            // SUBS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T1
109b8021494Sopenharmony_ci
110b8021494Sopenharmony_ci    "Sxtab",   // SXTAB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1
111b8021494Sopenharmony_ci    "Sxtab16", // SXTAB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1
112b8021494Sopenharmony_ci    "Sxtah",   // SXTAH{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1
113b8021494Sopenharmony_ci    "Uxtab",   // UXTAB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1
114b8021494Sopenharmony_ci    "Uxtab16", // UXTAB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1
115b8021494Sopenharmony_ci    "Uxtah",   // UXTAH{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1
116b8021494Sopenharmony_ci
117b8021494Sopenharmony_ci    // Shift instructions that alias to MOV.
118b8021494Sopenharmony_ci    // Note that we are not giving them a different input for their
119b8021494Sopenharmony_ci    // last operand since they are already tested in
120b8021494Sopenharmony_ci    // "cond-rd-operand-rn-shift-rs-t32.json".
121b8021494Sopenharmony_ci    // TODO: Add tests for MOV <Rd>, <Rn>, <shift>, <Rs>.
122b8021494Sopenharmony_ci    "Asr",  // ASR<c>{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
123b8021494Sopenharmony_ci            // ASR{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2
124b8021494Sopenharmony_ci
125b8021494Sopenharmony_ci    "Asrs", // ASRS{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
126b8021494Sopenharmony_ci            // ASRS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2
127b8021494Sopenharmony_ci
128b8021494Sopenharmony_ci    "Lsl",  // LSL<c>{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
129b8021494Sopenharmony_ci            // LSL{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2
130b8021494Sopenharmony_ci
131b8021494Sopenharmony_ci    "Lsls", // LSLS{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
132b8021494Sopenharmony_ci            // LSLS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2
133b8021494Sopenharmony_ci
134b8021494Sopenharmony_ci    "Lsr",  // LSR<c>{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
135b8021494Sopenharmony_ci            // LSR{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2
136b8021494Sopenharmony_ci
137b8021494Sopenharmony_ci    "Lsrs", // LSRS{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
138b8021494Sopenharmony_ci            // LSRS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2
139b8021494Sopenharmony_ci
140b8021494Sopenharmony_ci    "Ror",  // ROR<c>{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
141b8021494Sopenharmony_ci            // ROR{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2
142b8021494Sopenharmony_ci
143b8021494Sopenharmony_ci    "Rors"  // RORS{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
144b8021494Sopenharmony_ci            // RORS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2
145b8021494Sopenharmony_ci  ],
146b8021494Sopenharmony_ci  "description": {
147b8021494Sopenharmony_ci    "operands": [
148b8021494Sopenharmony_ci      {
149b8021494Sopenharmony_ci        "name": "cond",
150b8021494Sopenharmony_ci        "type": "Condition"
151b8021494Sopenharmony_ci      },
152b8021494Sopenharmony_ci      {
153b8021494Sopenharmony_ci        "name": "rd",
154b8021494Sopenharmony_ci        "type": "AllRegistersButPC"
155b8021494Sopenharmony_ci      },
156b8021494Sopenharmony_ci      {
157b8021494Sopenharmony_ci        "name": "rn",
158b8021494Sopenharmony_ci        "type": "AllRegistersButPC"
159b8021494Sopenharmony_ci      },
160b8021494Sopenharmony_ci      {
161b8021494Sopenharmony_ci        "name": "op",
162b8021494Sopenharmony_ci        "wrapper": "Operand",
163b8021494Sopenharmony_ci        "operands": [
164b8021494Sopenharmony_ci          {
165b8021494Sopenharmony_ci            "name": "rm",
166b8021494Sopenharmony_ci            "type": "AllRegistersButPC"
167b8021494Sopenharmony_ci          }
168b8021494Sopenharmony_ci        ]
169b8021494Sopenharmony_ci      }
170b8021494Sopenharmony_ci    ],
171b8021494Sopenharmony_ci    "inputs": [
172b8021494Sopenharmony_ci      {
173b8021494Sopenharmony_ci        "name": "apsr",
174b8021494Sopenharmony_ci        "type": "NZCV"
175b8021494Sopenharmony_ci      },
176b8021494Sopenharmony_ci      {
177b8021494Sopenharmony_ci        "name": "rd",
178b8021494Sopenharmony_ci        "type": "Register"
179b8021494Sopenharmony_ci      },
180b8021494Sopenharmony_ci      {
181b8021494Sopenharmony_ci        "name": "rn",
182b8021494Sopenharmony_ci        "type": "Register"
183b8021494Sopenharmony_ci      },
184b8021494Sopenharmony_ci      {
185b8021494Sopenharmony_ci        "name": "rm",
186b8021494Sopenharmony_ci        "type": "Register"
187b8021494Sopenharmony_ci      }
188b8021494Sopenharmony_ci    ]
189b8021494Sopenharmony_ci  },
190b8021494Sopenharmony_ci  "test-files": [
191b8021494Sopenharmony_ci    {
192b8021494Sopenharmony_ci      "type": "assembler",
193b8021494Sopenharmony_ci      "test-cases": [
194b8021494Sopenharmony_ci        {
195b8021494Sopenharmony_ci          "name": "Unconditional",
196b8021494Sopenharmony_ci          "operands": [
197b8021494Sopenharmony_ci            "cond", "rd", "rn", "rm"
198b8021494Sopenharmony_ci          ],
199b8021494Sopenharmony_ci          "operand-filter": "cond == 'al'",
200b8021494Sopenharmony_ci          "operand-limit": 500
201b8021494Sopenharmony_ci        }
202b8021494Sopenharmony_ci      ]
203b8021494Sopenharmony_ci    },
204b8021494Sopenharmony_ci    // Test cases where an IT instruction is allowed.
205b8021494Sopenharmony_ci    {
206b8021494Sopenharmony_ci      "name": "all-low-in-it-block",
207b8021494Sopenharmony_ci      "type": "assembler",
208b8021494Sopenharmony_ci      "mnemonics": [
209b8021494Sopenharmony_ci        "Add", // ADD<c>{<q>} <Rd>, <Rn>, <Rm> ; T1
210b8021494Sopenharmony_ci        "Sub"  // SUB<c>{<q>} <Rd>, <Rn>, <Rm> ; T1
211b8021494Sopenharmony_ci      ],
212b8021494Sopenharmony_ci      "test-cases": [
213b8021494Sopenharmony_ci        {
214b8021494Sopenharmony_ci          "name": "InITBlock",
215b8021494Sopenharmony_ci          "operands": [
216b8021494Sopenharmony_ci            "cond", "rd", "rn", "rm"
217b8021494Sopenharmony_ci          ],
218b8021494Sopenharmony_ci          // Generate an extra IT instruction.
219b8021494Sopenharmony_ci          "in-it-block": "{cond}",
220b8021494Sopenharmony_ci          "operand-filter": "cond != 'al' and register_is_low(rd) and register_is_low(rn) and register_is_low(rm)",
221b8021494Sopenharmony_ci          "operand-limit": 500
222b8021494Sopenharmony_ci        }
223b8021494Sopenharmony_ci      ]
224b8021494Sopenharmony_ci    },
225b8021494Sopenharmony_ci    {
226b8021494Sopenharmony_ci      "name": "all-low-rd-is-rn-in-it-block",
227b8021494Sopenharmony_ci      "type": "assembler",
228b8021494Sopenharmony_ci      "mnemonics": [
229b8021494Sopenharmony_ci        "Adc", // ADC<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
230b8021494Sopenharmony_ci        "And", // AND<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
231b8021494Sopenharmony_ci        "Asr", // ASR<c>{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
232b8021494Sopenharmony_ci        "Bic", // BIC<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
233b8021494Sopenharmony_ci        "Eor", // EOR<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
234b8021494Sopenharmony_ci        "Lsl", // LSL<c>{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
235b8021494Sopenharmony_ci        "Lsr", // LSR<c>{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
236b8021494Sopenharmony_ci        "Orr", // ORR<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
237b8021494Sopenharmony_ci        "Ror", // ROR<c>{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
238b8021494Sopenharmony_ci        "Sbc"  // SBC<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
239b8021494Sopenharmony_ci      ],
240b8021494Sopenharmony_ci      "test-cases": [
241b8021494Sopenharmony_ci        {
242b8021494Sopenharmony_ci          "name": "InITBlock",
243b8021494Sopenharmony_ci          "operands": [
244b8021494Sopenharmony_ci            "cond", "rd", "rn", "rm"
245b8021494Sopenharmony_ci          ],
246b8021494Sopenharmony_ci          // Generate an extra IT instruction.
247b8021494Sopenharmony_ci          "in-it-block": "{cond}",
248b8021494Sopenharmony_ci          "operand-filter": "cond != 'al' and rd == rn and register_is_low(rn) and register_is_low(rm)",
249b8021494Sopenharmony_ci          "operand-limit": 500
250b8021494Sopenharmony_ci        }
251b8021494Sopenharmony_ci      ]
252b8021494Sopenharmony_ci    },
253b8021494Sopenharmony_ci    {
254b8021494Sopenharmony_ci      "name": "rd-is-rn-in-it-block",
255b8021494Sopenharmony_ci      "type": "assembler",
256b8021494Sopenharmony_ci      "mnemonics": [
257b8021494Sopenharmony_ci        "Add" // ADD{<c>}{<q>} {<Rdn>}, <Rdn>, <Rm> ; T2
258b8021494Sopenharmony_ci      ],
259b8021494Sopenharmony_ci      "test-cases": [
260b8021494Sopenharmony_ci        {
261b8021494Sopenharmony_ci          "name": "InITBlock",
262b8021494Sopenharmony_ci          "operands": [
263b8021494Sopenharmony_ci            "cond", "rd", "rn", "rm"
264b8021494Sopenharmony_ci          ],
265b8021494Sopenharmony_ci          // Generate an extra IT instruction.
266b8021494Sopenharmony_ci          "in-it-block": "{cond}",
267b8021494Sopenharmony_ci          "operand-filter": "cond != 'al' and rd == rn and rm != 'r13'",
268b8021494Sopenharmony_ci          "operand-limit": 500
269b8021494Sopenharmony_ci        }
270b8021494Sopenharmony_ci      ]
271b8021494Sopenharmony_ci    },
272b8021494Sopenharmony_ci    // Special case for a conditional ADD instruction with rn as SP.
273b8021494Sopenharmony_ci    {
274b8021494Sopenharmony_ci      "name": "rn-is-sp-in-it-block",
275b8021494Sopenharmony_ci      "type": "assembler",
276b8021494Sopenharmony_ci      "mnemonics": [
277b8021494Sopenharmony_ci        "Add" // ADD{<c>}{<q>} {<Rdm>}, SP, <Rdm> ; T1
278b8021494Sopenharmony_ci      ],
279b8021494Sopenharmony_ci      "test-cases": [
280b8021494Sopenharmony_ci        {
281b8021494Sopenharmony_ci          "name": "InITBlock",
282b8021494Sopenharmony_ci          "operands": [
283b8021494Sopenharmony_ci            "cond", "rd", "rn", "rm"
284b8021494Sopenharmony_ci          ],
285b8021494Sopenharmony_ci          // Generate an extra IT instruction.
286b8021494Sopenharmony_ci          "in-it-block": "{cond}",
287b8021494Sopenharmony_ci          "operand-filter": "cond != 'al' and rd == rm and register_is_low(rm) and rn == 'r13'"
288b8021494Sopenharmony_ci        }
289b8021494Sopenharmony_ci      ]
290b8021494Sopenharmony_ci    },
291b8021494Sopenharmony_ci    // Special case for a conditional ADD instruction with rd and rn as SP.
292b8021494Sopenharmony_ci    {
293b8021494Sopenharmony_ci      "name": "rd-is-rn-is-sp-in-it-block",
294b8021494Sopenharmony_ci      "type": "assembler",
295b8021494Sopenharmony_ci      "mnemonics": [
296b8021494Sopenharmony_ci        "Add" // ADD{<c>}{<q>} {SP}, SP, <Rm> ; T2
297b8021494Sopenharmony_ci      ],
298b8021494Sopenharmony_ci      "test-cases": [
299b8021494Sopenharmony_ci        {
300b8021494Sopenharmony_ci          "name": "InITBlock",
301b8021494Sopenharmony_ci          "operands": [
302b8021494Sopenharmony_ci            "cond", "rd", "rn", "rm"
303b8021494Sopenharmony_ci          ],
304b8021494Sopenharmony_ci          // Generate an extra IT instruction.
305b8021494Sopenharmony_ci          "in-it-block": "{cond}",
306b8021494Sopenharmony_ci          "operand-filter": "cond != 'al' and rd == 'r13' and rn == 'r13'"
307b8021494Sopenharmony_ci        }
308b8021494Sopenharmony_ci      ]
309b8021494Sopenharmony_ci    },
310b8021494Sopenharmony_ci    {
311b8021494Sopenharmony_ci      "type": "simulator",
312b8021494Sopenharmony_ci      "test-cases": [
313b8021494Sopenharmony_ci        {
314b8021494Sopenharmony_ci          "name": "Condition",
315b8021494Sopenharmony_ci          "operands": [
316b8021494Sopenharmony_ci            "cond"
317b8021494Sopenharmony_ci          ],
318b8021494Sopenharmony_ci          "inputs": [
319b8021494Sopenharmony_ci            "apsr"
320b8021494Sopenharmony_ci          ]
321b8021494Sopenharmony_ci        },
322b8021494Sopenharmony_ci        // Test combinations of registers values with rd == rn.
323b8021494Sopenharmony_ci        {
324b8021494Sopenharmony_ci          "name": "RdIsRn",
325b8021494Sopenharmony_ci          "operands": [
326b8021494Sopenharmony_ci            "cond", "rd", "rn", "rm"
327b8021494Sopenharmony_ci          ],
328b8021494Sopenharmony_ci          "inputs": [
329b8021494Sopenharmony_ci            "apsr", "rd", "rn", "rm"
330b8021494Sopenharmony_ci          ],
331b8021494Sopenharmony_ci          "operand-filter": "rd == rn and rn != rm",
332b8021494Sopenharmony_ci          "operand-limit": 10,
333b8021494Sopenharmony_ci          "input-filter": "rd == rn",
334b8021494Sopenharmony_ci          "input-limit": 200
335b8021494Sopenharmony_ci        },
336b8021494Sopenharmony_ci        // Test combinations of registers values with rd == rm.
337b8021494Sopenharmony_ci        {
338b8021494Sopenharmony_ci          "name": "RdIsRm",
339b8021494Sopenharmony_ci          "operands": [
340b8021494Sopenharmony_ci            "cond", "rd", "rn", "rm"
341b8021494Sopenharmony_ci          ],
342b8021494Sopenharmony_ci          "inputs": [
343b8021494Sopenharmony_ci            "apsr", "rd", "rn", "rm"
344b8021494Sopenharmony_ci          ],
345b8021494Sopenharmony_ci          "operand-filter": "rd == rm and rn != rm",
346b8021494Sopenharmony_ci          "operand-limit": 10,
347b8021494Sopenharmony_ci          "input-filter": "rd == rm",
348b8021494Sopenharmony_ci          "input-limit": 200
349b8021494Sopenharmony_ci        },
350b8021494Sopenharmony_ci        // Test combinations of registers values.
351b8021494Sopenharmony_ci        {
352b8021494Sopenharmony_ci          "name": "RdIsNotRnIsNotRm",
353b8021494Sopenharmony_ci          "operands": [
354b8021494Sopenharmony_ci            "cond", "rd", "rn", "rm"
355b8021494Sopenharmony_ci          ],
356b8021494Sopenharmony_ci          "inputs": [
357b8021494Sopenharmony_ci            "apsr", "rd", "rn", "rm"
358b8021494Sopenharmony_ci          ],
359b8021494Sopenharmony_ci          "operand-filter": "rd != rn != rm",
360b8021494Sopenharmony_ci          "operand-limit": 10,
361b8021494Sopenharmony_ci          "input-limit": 200
362b8021494Sopenharmony_ci        }
363b8021494Sopenharmony_ci      ]
364b8021494Sopenharmony_ci    }
365b8021494Sopenharmony_ci  ]
366b8021494Sopenharmony_ci}
367