1b8021494Sopenharmony_ci// Copyright 2016, VIXL authors 2b8021494Sopenharmony_ci// All rights reserved. 3b8021494Sopenharmony_ci// 4b8021494Sopenharmony_ci// Redistribution and use in source and binary forms, with or without 5b8021494Sopenharmony_ci// modification, are permitted provided that the following conditions are met: 6b8021494Sopenharmony_ci// 7b8021494Sopenharmony_ci// * Redistributions of source code must retain the above copyright notice, 8b8021494Sopenharmony_ci// this list of conditions and the following disclaimer. 9b8021494Sopenharmony_ci// * Redistributions in binary form must reproduce the above copyright notice, 10b8021494Sopenharmony_ci// this list of conditions and the following disclaimer in the documentation 11b8021494Sopenharmony_ci// and/or other materials provided with the distribution. 12b8021494Sopenharmony_ci// * Neither the name of ARM Limited nor the names of its contributors may be 13b8021494Sopenharmony_ci// used to endorse or promote products derived from this software without 14b8021494Sopenharmony_ci// specific prior written permission. 15b8021494Sopenharmony_ci// 16b8021494Sopenharmony_ci// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17b8021494Sopenharmony_ci// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18b8021494Sopenharmony_ci// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19b8021494Sopenharmony_ci// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20b8021494Sopenharmony_ci// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21b8021494Sopenharmony_ci// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22b8021494Sopenharmony_ci// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23b8021494Sopenharmony_ci// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24b8021494Sopenharmony_ci// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25b8021494Sopenharmony_ci// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26b8021494Sopenharmony_ci 27b8021494Sopenharmony_ci// Test description for instructions of the following form: 28b8021494Sopenharmony_ci// MNEMONIC{<c>}.W <Rd>, <Rn>, <Rm>, LSL|ROR #<amount> 29b8021494Sopenharmony_ci// MNEMONIC{<c>}.W <Rd>, SP, <Rm>, LSL|ROR #<amount> 30b8021494Sopenharmony_ci 31b8021494Sopenharmony_ci{ 32b8021494Sopenharmony_ci "mnemonics": [ 33b8021494Sopenharmony_ci "Adc", // ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2 34b8021494Sopenharmony_ci "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2 35b8021494Sopenharmony_ci "Add", // ADD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T3 36b8021494Sopenharmony_ci // ADD{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T3 37b8021494Sopenharmony_ci "Adds", // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T3 38b8021494Sopenharmony_ci // ADDS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T3 39b8021494Sopenharmony_ci "And", // AND{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2 40b8021494Sopenharmony_ci "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2 41b8021494Sopenharmony_ci "Bic", // BIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2 42b8021494Sopenharmony_ci "Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2 43b8021494Sopenharmony_ci "Eor", // EOR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2 44b8021494Sopenharmony_ci "Eors", // EORS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2 45b8021494Sopenharmony_ci "Orn", // ORN{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T1 46b8021494Sopenharmony_ci "Orns", // ORNS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T1 47b8021494Sopenharmony_ci "Orr", // ORR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2 48b8021494Sopenharmony_ci "Orrs", // ORRS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2 49b8021494Sopenharmony_ci "Rsb", // RSB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T1 50b8021494Sopenharmony_ci "Rsbs", // RSBS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T1 51b8021494Sopenharmony_ci "Sbc", // SBC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2 52b8021494Sopenharmony_ci "Sbcs", // SBCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2 53b8021494Sopenharmony_ci "Sub", // SUB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2 54b8021494Sopenharmony_ci // SUB{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T1 55b8021494Sopenharmony_ci "Subs" // SUBS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2 56b8021494Sopenharmony_ci // SUBS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T1 57b8021494Sopenharmony_ci ], 58b8021494Sopenharmony_ci "description": { 59b8021494Sopenharmony_ci "operands": [ 60b8021494Sopenharmony_ci { 61b8021494Sopenharmony_ci "name": "cond", 62b8021494Sopenharmony_ci "type": "Condition" 63b8021494Sopenharmony_ci }, 64b8021494Sopenharmony_ci { 65b8021494Sopenharmony_ci "name": "rd", 66b8021494Sopenharmony_ci "type": "AllRegistersButPC" 67b8021494Sopenharmony_ci }, 68b8021494Sopenharmony_ci { 69b8021494Sopenharmony_ci "name": "rn", 70b8021494Sopenharmony_ci "type": "AllRegistersButPC" 71b8021494Sopenharmony_ci }, 72b8021494Sopenharmony_ci { 73b8021494Sopenharmony_ci "name": "op", 74b8021494Sopenharmony_ci "wrapper": "Operand", 75b8021494Sopenharmony_ci "operands": [ 76b8021494Sopenharmony_ci { 77b8021494Sopenharmony_ci "name": "rm", 78b8021494Sopenharmony_ci "type": "AllRegistersButPC" 79b8021494Sopenharmony_ci }, 80b8021494Sopenharmony_ci { 81b8021494Sopenharmony_ci "name": "shift", 82b8021494Sopenharmony_ci "type": "Shift1To31" 83b8021494Sopenharmony_ci }, 84b8021494Sopenharmony_ci { 85b8021494Sopenharmony_ci "name": "amount", 86b8021494Sopenharmony_ci "type": "ShiftAmount1To31" 87b8021494Sopenharmony_ci } 88b8021494Sopenharmony_ci ] 89b8021494Sopenharmony_ci } 90b8021494Sopenharmony_ci ], 91b8021494Sopenharmony_ci "inputs": [ 92b8021494Sopenharmony_ci { 93b8021494Sopenharmony_ci "name": "apsr", 94b8021494Sopenharmony_ci "type": "NZCV" 95b8021494Sopenharmony_ci }, 96b8021494Sopenharmony_ci { 97b8021494Sopenharmony_ci "name": "rd", 98b8021494Sopenharmony_ci "type": "Register" 99b8021494Sopenharmony_ci }, 100b8021494Sopenharmony_ci { 101b8021494Sopenharmony_ci "name": "rn", 102b8021494Sopenharmony_ci "type": "Register" 103b8021494Sopenharmony_ci }, 104b8021494Sopenharmony_ci { 105b8021494Sopenharmony_ci "name": "rm", 106b8021494Sopenharmony_ci "type": "Register" 107b8021494Sopenharmony_ci } 108b8021494Sopenharmony_ci ] 109b8021494Sopenharmony_ci }, 110b8021494Sopenharmony_ci "test-files": [ 111b8021494Sopenharmony_ci { 112b8021494Sopenharmony_ci "type": "assembler", 113b8021494Sopenharmony_ci "test-cases": [ 114b8021494Sopenharmony_ci { 115b8021494Sopenharmony_ci "name": "Operands", 116b8021494Sopenharmony_ci "operands": [ 117b8021494Sopenharmony_ci "cond", "rd", "rn", "rm", "shift", "amount" 118b8021494Sopenharmony_ci ], 119b8021494Sopenharmony_ci "operand-filter": "cond == 'al'", 120b8021494Sopenharmony_ci "operand-limit": 500 121b8021494Sopenharmony_ci } 122b8021494Sopenharmony_ci ] 123b8021494Sopenharmony_ci }, 124b8021494Sopenharmony_ci { 125b8021494Sopenharmony_ci "type": "simulator", 126b8021494Sopenharmony_ci "test-cases": [ 127b8021494Sopenharmony_ci { 128b8021494Sopenharmony_ci "name": "Condition", 129b8021494Sopenharmony_ci "operands": [ 130b8021494Sopenharmony_ci "cond" 131b8021494Sopenharmony_ci ], 132b8021494Sopenharmony_ci "inputs": [ 133b8021494Sopenharmony_ci "apsr" 134b8021494Sopenharmony_ci ] 135b8021494Sopenharmony_ci }, 136b8021494Sopenharmony_ci // Test combinations of registers values with rd == rn. 137b8021494Sopenharmony_ci { 138b8021494Sopenharmony_ci "name": "RdIsRn", 139b8021494Sopenharmony_ci "operands": [ 140b8021494Sopenharmony_ci "rd", "rn", "rm" 141b8021494Sopenharmony_ci ], 142b8021494Sopenharmony_ci "inputs": [ 143b8021494Sopenharmony_ci "rd", "rn", "rm" 144b8021494Sopenharmony_ci ], 145b8021494Sopenharmony_ci "operand-filter": "rd == rn and rn != rm", 146b8021494Sopenharmony_ci "operand-limit": 10, 147b8021494Sopenharmony_ci "input-filter": "rd == rn", 148b8021494Sopenharmony_ci "input-limit": 200 149b8021494Sopenharmony_ci }, 150b8021494Sopenharmony_ci // Test combinations of registers values with rd == rm. 151b8021494Sopenharmony_ci { 152b8021494Sopenharmony_ci "name": "RdIsRm", 153b8021494Sopenharmony_ci "operands": [ 154b8021494Sopenharmony_ci "rd", "rn", "rm" 155b8021494Sopenharmony_ci ], 156b8021494Sopenharmony_ci "inputs": [ 157b8021494Sopenharmony_ci "rd", "rn", "rm" 158b8021494Sopenharmony_ci ], 159b8021494Sopenharmony_ci "operand-filter": "rd == rm and rn != rm", 160b8021494Sopenharmony_ci "operand-limit": 10, 161b8021494Sopenharmony_ci "input-filter": "rd == rm", 162b8021494Sopenharmony_ci "input-limit": 200 163b8021494Sopenharmony_ci }, 164b8021494Sopenharmony_ci // Test combinations of registers values. 165b8021494Sopenharmony_ci { 166b8021494Sopenharmony_ci "name": "RdIsNotRnIsNotRm", 167b8021494Sopenharmony_ci "operands": [ 168b8021494Sopenharmony_ci "rd", "rn", "rm" 169b8021494Sopenharmony_ci ], 170b8021494Sopenharmony_ci "inputs": [ 171b8021494Sopenharmony_ci "rd", "rn", "rm" 172b8021494Sopenharmony_ci ], 173b8021494Sopenharmony_ci "operand-filter": "rd != rn != rm", 174b8021494Sopenharmony_ci "operand-limit": 10, 175b8021494Sopenharmony_ci "input-limit": 200 176b8021494Sopenharmony_ci }, 177b8021494Sopenharmony_ci // Test combinations of shift types and shift amounts. 178b8021494Sopenharmony_ci { 179b8021494Sopenharmony_ci "name": "ShiftTypes", 180b8021494Sopenharmony_ci "operands": [ 181b8021494Sopenharmony_ci "rd", "rn", "rm", "shift", "amount" 182b8021494Sopenharmony_ci ], 183b8021494Sopenharmony_ci "inputs": [ 184b8021494Sopenharmony_ci "rm" 185b8021494Sopenharmony_ci ], 186b8021494Sopenharmony_ci // Specify exactly what registers to use in this test to make sure 187b8021494Sopenharmony_ci // that they are different. It makes the execution trace more 188b8021494Sopenharmony_ci // understandable. 189b8021494Sopenharmony_ci "operand-filter": "rd == 'r0' and rn == 'r1' and rm == 'r2'" 190b8021494Sopenharmony_ci } 191b8021494Sopenharmony_ci ] 192b8021494Sopenharmony_ci } 193b8021494Sopenharmony_ci ] 194b8021494Sopenharmony_ci} 195