1b8021494Sopenharmony_ci// Copyright 2016, VIXL authors
2b8021494Sopenharmony_ci// All rights reserved.
3b8021494Sopenharmony_ci//
4b8021494Sopenharmony_ci// Redistribution and use in source and binary forms, with or without
5b8021494Sopenharmony_ci// modification, are permitted provided that the following conditions are met:
6b8021494Sopenharmony_ci//
7b8021494Sopenharmony_ci//   * Redistributions of source code must retain the above copyright notice,
8b8021494Sopenharmony_ci//     this list of conditions and the following disclaimer.
9b8021494Sopenharmony_ci//   * Redistributions in binary form must reproduce the above copyright notice,
10b8021494Sopenharmony_ci//     this list of conditions and the following disclaimer in the documentation
11b8021494Sopenharmony_ci//     and/or other materials provided with the distribution.
12b8021494Sopenharmony_ci//   * Neither the name of ARM Limited nor the names of its contributors may be
13b8021494Sopenharmony_ci//     used to endorse or promote products derived from this software without
14b8021494Sopenharmony_ci//     specific prior written permission.
15b8021494Sopenharmony_ci//
16b8021494Sopenharmony_ci// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
17b8021494Sopenharmony_ci// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18b8021494Sopenharmony_ci// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19b8021494Sopenharmony_ci// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
20b8021494Sopenharmony_ci// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21b8021494Sopenharmony_ci// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22b8021494Sopenharmony_ci// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
23b8021494Sopenharmony_ci// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24b8021494Sopenharmony_ci// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25b8021494Sopenharmony_ci// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26b8021494Sopenharmony_ci
27b8021494Sopenharmony_ci{
28b8021494Sopenharmony_ci  "mnemonics": [
29b8021494Sopenharmony_ci    "Adc",  // ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
30b8021494Sopenharmony_ci    "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
31b8021494Sopenharmony_ci    "Add",  // ADD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
32b8021494Sopenharmony_ci            // ADD{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1
33b8021494Sopenharmony_ci    "Adds", // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
34b8021494Sopenharmony_ci            // ADDS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1
35b8021494Sopenharmony_ci    "And",  // AND{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
36b8021494Sopenharmony_ci    "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
37b8021494Sopenharmony_ci    "Bic",  // BIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
38b8021494Sopenharmony_ci    "Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
39b8021494Sopenharmony_ci    "Eor",  // EOR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
40b8021494Sopenharmony_ci    "Eors", // EORS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
41b8021494Sopenharmony_ci    "Orr",  // ORR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
42b8021494Sopenharmony_ci    "Orrs", // ORRS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
43b8021494Sopenharmony_ci    "Rsb",  // RSB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
44b8021494Sopenharmony_ci    "Rsbs", // RSBS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
45b8021494Sopenharmony_ci    "Rsc",  // RSC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
46b8021494Sopenharmony_ci    "Rscs", // RSCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
47b8021494Sopenharmony_ci    "Sbc",  // SBC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
48b8021494Sopenharmony_ci    "Sbcs", // SBCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
49b8021494Sopenharmony_ci    "Sub",  // SUB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
50b8021494Sopenharmony_ci            // SUB{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1
51b8021494Sopenharmony_ci    "Subs"  // SUBS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
52b8021494Sopenharmony_ci            // SUBS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1
53b8021494Sopenharmony_ci  ],
54b8021494Sopenharmony_ci  "description": {
55b8021494Sopenharmony_ci    "operands": [
56b8021494Sopenharmony_ci      {
57b8021494Sopenharmony_ci        "name": "cond",
58b8021494Sopenharmony_ci        "type": "Condition"
59b8021494Sopenharmony_ci      },
60b8021494Sopenharmony_ci      {
61b8021494Sopenharmony_ci        "name": "rd",
62b8021494Sopenharmony_ci        "type": "AllRegistersButPC"
63b8021494Sopenharmony_ci      },
64b8021494Sopenharmony_ci      {
65b8021494Sopenharmony_ci        "name": "rn",
66b8021494Sopenharmony_ci        "type": "AllRegistersButPC"
67b8021494Sopenharmony_ci      },
68b8021494Sopenharmony_ci      {
69b8021494Sopenharmony_ci        "name": "op",
70b8021494Sopenharmony_ci        "wrapper": "Operand",
71b8021494Sopenharmony_ci        "operands": [
72b8021494Sopenharmony_ci          {
73b8021494Sopenharmony_ci            "name": "rm",
74b8021494Sopenharmony_ci            "type": "AllRegistersButPC"
75b8021494Sopenharmony_ci          },
76b8021494Sopenharmony_ci          {
77b8021494Sopenharmony_ci            "name": "shift",
78b8021494Sopenharmony_ci            "type": "Shift1To31"
79b8021494Sopenharmony_ci          },
80b8021494Sopenharmony_ci          {
81b8021494Sopenharmony_ci            "name": "amount",
82b8021494Sopenharmony_ci            "type": "ShiftAmount1To31"
83b8021494Sopenharmony_ci          }
84b8021494Sopenharmony_ci        ]
85b8021494Sopenharmony_ci      }
86b8021494Sopenharmony_ci    ],
87b8021494Sopenharmony_ci    "inputs": [
88b8021494Sopenharmony_ci      {
89b8021494Sopenharmony_ci        "name": "apsr",
90b8021494Sopenharmony_ci        "type": "NZCV"
91b8021494Sopenharmony_ci      },
92b8021494Sopenharmony_ci      {
93b8021494Sopenharmony_ci        "name": "rd",
94b8021494Sopenharmony_ci        "type": "Register"
95b8021494Sopenharmony_ci      },
96b8021494Sopenharmony_ci      {
97b8021494Sopenharmony_ci        "name": "rn",
98b8021494Sopenharmony_ci        "type": "Register"
99b8021494Sopenharmony_ci      },
100b8021494Sopenharmony_ci      {
101b8021494Sopenharmony_ci        "name": "rm",
102b8021494Sopenharmony_ci        "type": "Register"
103b8021494Sopenharmony_ci      }
104b8021494Sopenharmony_ci    ]
105b8021494Sopenharmony_ci  },
106b8021494Sopenharmony_ci  "test-files": [
107b8021494Sopenharmony_ci    {
108b8021494Sopenharmony_ci      "type": "assembler",
109b8021494Sopenharmony_ci      "test-cases": [
110b8021494Sopenharmony_ci        {
111b8021494Sopenharmony_ci          "name": "Operands",
112b8021494Sopenharmony_ci          "operands": [
113b8021494Sopenharmony_ci            "cond", "rd", "rn", "rm", "shift", "amount"
114b8021494Sopenharmony_ci          ],
115b8021494Sopenharmony_ci          "operand-limit": 500
116b8021494Sopenharmony_ci        }
117b8021494Sopenharmony_ci      ]
118b8021494Sopenharmony_ci    },
119b8021494Sopenharmony_ci    {
120b8021494Sopenharmony_ci      "type": "simulator",
121b8021494Sopenharmony_ci      "test-cases": [
122b8021494Sopenharmony_ci        {
123b8021494Sopenharmony_ci          "name": "Condition",
124b8021494Sopenharmony_ci          "operands": [
125b8021494Sopenharmony_ci            "cond"
126b8021494Sopenharmony_ci          ],
127b8021494Sopenharmony_ci          "inputs": [
128b8021494Sopenharmony_ci            "apsr"
129b8021494Sopenharmony_ci          ]
130b8021494Sopenharmony_ci        },
131b8021494Sopenharmony_ci        // Test combinations of registers values with rd == rn.
132b8021494Sopenharmony_ci        {
133b8021494Sopenharmony_ci          "name": "RdIsRn",
134b8021494Sopenharmony_ci          "operands": [
135b8021494Sopenharmony_ci            "rd", "rn", "rm"
136b8021494Sopenharmony_ci          ],
137b8021494Sopenharmony_ci          "inputs": [
138b8021494Sopenharmony_ci            "rd", "rn", "rm"
139b8021494Sopenharmony_ci          ],
140b8021494Sopenharmony_ci          "operand-filter": "rd == rn and rn != rm",
141b8021494Sopenharmony_ci          "operand-limit": 10,
142b8021494Sopenharmony_ci          "input-filter": "rd == rn",
143b8021494Sopenharmony_ci          "input-limit": 200
144b8021494Sopenharmony_ci        },
145b8021494Sopenharmony_ci        // Test combinations of registers values with rd == rm.
146b8021494Sopenharmony_ci        {
147b8021494Sopenharmony_ci          "name": "RdIsRm",
148b8021494Sopenharmony_ci          "operands": [
149b8021494Sopenharmony_ci            "rd", "rn", "rm"
150b8021494Sopenharmony_ci          ],
151b8021494Sopenharmony_ci          "inputs": [
152b8021494Sopenharmony_ci            "rd", "rn", "rm"
153b8021494Sopenharmony_ci          ],
154b8021494Sopenharmony_ci          "operand-filter": "rd == rm and rn != rm",
155b8021494Sopenharmony_ci          "operand-limit": 10,
156b8021494Sopenharmony_ci          "input-filter": "rd == rm",
157b8021494Sopenharmony_ci          "input-limit": 200
158b8021494Sopenharmony_ci        },
159b8021494Sopenharmony_ci        // Test combinations of registers values.
160b8021494Sopenharmony_ci        {
161b8021494Sopenharmony_ci          "name": "RdIsNotRnIsNotRm",
162b8021494Sopenharmony_ci          "operands": [
163b8021494Sopenharmony_ci            "rd", "rn", "rm"
164b8021494Sopenharmony_ci          ],
165b8021494Sopenharmony_ci          "inputs": [
166b8021494Sopenharmony_ci            "rd", "rn", "rm"
167b8021494Sopenharmony_ci          ],
168b8021494Sopenharmony_ci          "operand-filter": "rd != rn != rm",
169b8021494Sopenharmony_ci          "operand-limit": 10,
170b8021494Sopenharmony_ci          "input-limit": 200
171b8021494Sopenharmony_ci        },
172b8021494Sopenharmony_ci        // Test combinations of shift types and shift amounts.
173b8021494Sopenharmony_ci        {
174b8021494Sopenharmony_ci          "name": "ShiftTypes",
175b8021494Sopenharmony_ci          "operands": [
176b8021494Sopenharmony_ci            "rm", "shift", "amount"
177b8021494Sopenharmony_ci          ],
178b8021494Sopenharmony_ci          "inputs": [
179b8021494Sopenharmony_ci            "rm"
180b8021494Sopenharmony_ci          ],
181b8021494Sopenharmony_ci          "operand-filter": "rm == 'r1'"
182b8021494Sopenharmony_ci        }
183b8021494Sopenharmony_ci      ]
184b8021494Sopenharmony_ci    }
185b8021494Sopenharmony_ci  ]
186b8021494Sopenharmony_ci}
187