1b8021494Sopenharmony_ci// Copyright 2016, VIXL authors
2b8021494Sopenharmony_ci// All rights reserved.
3b8021494Sopenharmony_ci//
4b8021494Sopenharmony_ci// Redistribution and use in source and binary forms, with or without
5b8021494Sopenharmony_ci// modification, are permitted provided that the following conditions are met:
6b8021494Sopenharmony_ci//
7b8021494Sopenharmony_ci//   * Redistributions of source code must retain the above copyright notice,
8b8021494Sopenharmony_ci//     this list of conditions and the following disclaimer.
9b8021494Sopenharmony_ci//   * Redistributions in binary form must reproduce the above copyright notice,
10b8021494Sopenharmony_ci//     this list of conditions and the following disclaimer in the documentation
11b8021494Sopenharmony_ci//     and/or other materials provided with the distribution.
12b8021494Sopenharmony_ci//   * Neither the name of ARM Limited nor the names of its contributors may be
13b8021494Sopenharmony_ci//     used to endorse or promote products derived from this software without
14b8021494Sopenharmony_ci//     specific prior written permission.
15b8021494Sopenharmony_ci//
16b8021494Sopenharmony_ci// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
17b8021494Sopenharmony_ci// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18b8021494Sopenharmony_ci// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19b8021494Sopenharmony_ci// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
20b8021494Sopenharmony_ci// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21b8021494Sopenharmony_ci// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22b8021494Sopenharmony_ci// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
23b8021494Sopenharmony_ci// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24b8021494Sopenharmony_ci// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25b8021494Sopenharmony_ci// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26b8021494Sopenharmony_ci
27b8021494Sopenharmony_ci// Test description for instructions of the following form:
28b8021494Sopenharmony_ci//   MNEMONIC{<c>}.W <Rd>, <Rn>, <Rm>, ROR #<amount>
29b8021494Sopenharmony_ci
30b8021494Sopenharmony_ci{
31b8021494Sopenharmony_ci  "mnemonics": [
32b8021494Sopenharmony_ci    "Sxtab",   // SXTAB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1
33b8021494Sopenharmony_ci    "Sxtab16", // SXTAB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1
34b8021494Sopenharmony_ci    "Sxtah",   // SXTAH{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1
35b8021494Sopenharmony_ci    "Uxtab",   // UXTAB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1
36b8021494Sopenharmony_ci    "Uxtab16", // UXTAB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1
37b8021494Sopenharmony_ci    "Uxtah"    // UXTAH{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1
38b8021494Sopenharmony_ci  ],
39b8021494Sopenharmony_ci  "description": {
40b8021494Sopenharmony_ci    "operands": [
41b8021494Sopenharmony_ci      {
42b8021494Sopenharmony_ci        "name": "cond",
43b8021494Sopenharmony_ci        "type": "Condition"
44b8021494Sopenharmony_ci      },
45b8021494Sopenharmony_ci      {
46b8021494Sopenharmony_ci        "name": "rd",
47b8021494Sopenharmony_ci        "type": "AllRegistersButPC"
48b8021494Sopenharmony_ci      },
49b8021494Sopenharmony_ci      {
50b8021494Sopenharmony_ci        "name": "rn",
51b8021494Sopenharmony_ci        "type": "AllRegistersButPC"
52b8021494Sopenharmony_ci      },
53b8021494Sopenharmony_ci      {
54b8021494Sopenharmony_ci        "name": "op",
55b8021494Sopenharmony_ci        "wrapper": "Operand",
56b8021494Sopenharmony_ci        "operands": [
57b8021494Sopenharmony_ci          {
58b8021494Sopenharmony_ci            "name": "rm",
59b8021494Sopenharmony_ci            "type": "AllRegistersButPC"
60b8021494Sopenharmony_ci          },
61b8021494Sopenharmony_ci          {
62b8021494Sopenharmony_ci            "name": "ror",
63b8021494Sopenharmony_ci            "type": "ShiftROR"
64b8021494Sopenharmony_ci          },
65b8021494Sopenharmony_ci          {
66b8021494Sopenharmony_ci            "name": "amount",
67b8021494Sopenharmony_ci            "type": "ShiftRotationAmountX8"
68b8021494Sopenharmony_ci          }
69b8021494Sopenharmony_ci        ]
70b8021494Sopenharmony_ci      }
71b8021494Sopenharmony_ci    ],
72b8021494Sopenharmony_ci    "inputs": [
73b8021494Sopenharmony_ci      {
74b8021494Sopenharmony_ci        "name": "apsr",
75b8021494Sopenharmony_ci        "type": "NZCV"
76b8021494Sopenharmony_ci      },
77b8021494Sopenharmony_ci      {
78b8021494Sopenharmony_ci        "name": "rd",
79b8021494Sopenharmony_ci        "type": "Register"
80b8021494Sopenharmony_ci      },
81b8021494Sopenharmony_ci      {
82b8021494Sopenharmony_ci        "name": "rn",
83b8021494Sopenharmony_ci        "type": "Register"
84b8021494Sopenharmony_ci      },
85b8021494Sopenharmony_ci      {
86b8021494Sopenharmony_ci        "name": "rm",
87b8021494Sopenharmony_ci        "type": "Register"
88b8021494Sopenharmony_ci      }
89b8021494Sopenharmony_ci    ]
90b8021494Sopenharmony_ci  },
91b8021494Sopenharmony_ci  "test-files": [
92b8021494Sopenharmony_ci    {
93b8021494Sopenharmony_ci      "type": "assembler",
94b8021494Sopenharmony_ci      "test-cases": [
95b8021494Sopenharmony_ci        {
96b8021494Sopenharmony_ci          "name": "Operands",
97b8021494Sopenharmony_ci          "operands": [
98b8021494Sopenharmony_ci            "cond", "rd", "rn", "rm", "ror", "amount"
99b8021494Sopenharmony_ci          ],
100b8021494Sopenharmony_ci          "operand-filter": "cond == 'al'",
101b8021494Sopenharmony_ci          "operand-limit": 1000
102b8021494Sopenharmony_ci        }
103b8021494Sopenharmony_ci      ]
104b8021494Sopenharmony_ci    },
105b8021494Sopenharmony_ci    {
106b8021494Sopenharmony_ci      "type": "simulator",
107b8021494Sopenharmony_ci      "test-cases": [
108b8021494Sopenharmony_ci        {
109b8021494Sopenharmony_ci          "name": "Condition",
110b8021494Sopenharmony_ci          "operands": [
111b8021494Sopenharmony_ci            "cond"
112b8021494Sopenharmony_ci          ],
113b8021494Sopenharmony_ci          "inputs": [
114b8021494Sopenharmony_ci            "apsr"
115b8021494Sopenharmony_ci          ]
116b8021494Sopenharmony_ci        },
117b8021494Sopenharmony_ci        // Test combinations of registers values with rd == rn.
118b8021494Sopenharmony_ci        {
119b8021494Sopenharmony_ci          "name": "RdIsRn",
120b8021494Sopenharmony_ci          "operands": [
121b8021494Sopenharmony_ci            "rd", "rn", "rm"
122b8021494Sopenharmony_ci          ],
123b8021494Sopenharmony_ci          "inputs": [
124b8021494Sopenharmony_ci            "rd", "rn", "rm"
125b8021494Sopenharmony_ci          ],
126b8021494Sopenharmony_ci          "operand-filter": "rd == rn and rn != rm",
127b8021494Sopenharmony_ci          "operand-limit": 10,
128b8021494Sopenharmony_ci          "input-filter": "rd == rn",
129b8021494Sopenharmony_ci          "input-limit": 200
130b8021494Sopenharmony_ci        },
131b8021494Sopenharmony_ci        // Test combinations of registers values with rd == rm.
132b8021494Sopenharmony_ci        {
133b8021494Sopenharmony_ci          "name": "RdIsRm",
134b8021494Sopenharmony_ci          "operands": [
135b8021494Sopenharmony_ci            "rd", "rn", "rm"
136b8021494Sopenharmony_ci          ],
137b8021494Sopenharmony_ci          "inputs": [
138b8021494Sopenharmony_ci            "rd", "rn", "rm"
139b8021494Sopenharmony_ci          ],
140b8021494Sopenharmony_ci          "operand-filter": "rd == rm and rn != rm",
141b8021494Sopenharmony_ci          "operand-limit": 10,
142b8021494Sopenharmony_ci          "input-filter": "rd == rm",
143b8021494Sopenharmony_ci          "input-limit": 200
144b8021494Sopenharmony_ci        },
145b8021494Sopenharmony_ci        // Test combinations of registers values.
146b8021494Sopenharmony_ci        {
147b8021494Sopenharmony_ci          "name": "RdIsNotRnIsNotRm",
148b8021494Sopenharmony_ci          "operands": [
149b8021494Sopenharmony_ci            "rd", "rn", "rm"
150b8021494Sopenharmony_ci          ],
151b8021494Sopenharmony_ci          "inputs": [
152b8021494Sopenharmony_ci            "rd", "rn", "rm"
153b8021494Sopenharmony_ci          ],
154b8021494Sopenharmony_ci          "operand-filter": "rd != rn != rm",
155b8021494Sopenharmony_ci          "operand-limit": 10,
156b8021494Sopenharmony_ci          "input-limit": 200
157b8021494Sopenharmony_ci        },
158b8021494Sopenharmony_ci        // Test combinations of rotation amounts.
159b8021494Sopenharmony_ci        {
160b8021494Sopenharmony_ci          "name": "Rotations",
161b8021494Sopenharmony_ci          "operands": [
162b8021494Sopenharmony_ci            "rd", "rn", "rm", "ror", "amount"
163b8021494Sopenharmony_ci          ],
164b8021494Sopenharmony_ci          "inputs": [
165b8021494Sopenharmony_ci            "rm"
166b8021494Sopenharmony_ci          ],
167b8021494Sopenharmony_ci          // Specify exactly what registers to use in this test to make sure
168b8021494Sopenharmony_ci          // that they are different. It makes the execution trace more
169b8021494Sopenharmony_ci          // understandable.
170b8021494Sopenharmony_ci          "operand-filter": "rd == 'r0' and rn == 'r1' and rm == 'r2'"
171b8021494Sopenharmony_ci        }
172b8021494Sopenharmony_ci      ]
173b8021494Sopenharmony_ci    }
174b8021494Sopenharmony_ci  ]
175b8021494Sopenharmony_ci}
176