xref: /third_party/vixl/test/aarch32/config/cond-rd-rn-operand-imm12-t32.json (revision b8021494)

// Copyright 2016, VIXL authors
// All rights reserved.
//
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// modification, are permitted provided that the following conditions are met:
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// Test description for instructions of the following forms:
//   MNEMONIC{<c>}.W <Rd>, <Rn>, #<imm12>
//   MNEMONIC{<c>}.W <Rd>, SP, #<imm12>

{
  "mnemonics" : [
    "Add",  // ADD{<c>}{<q>} {<Rd>}, <Rn>, #<imm12> ; T4
            // ADD{<c>}{<q>} {<Rd>}, SP, #<imm12> ; T4
    "Addw", // ADDW{<c>}{<q>} {<Rd>}, <Rn>, #<imm12> ; T4
            // ADDW{<c>}{<q>} {<Rd>}, SP, #<imm12> ; T4
    "Sub",  // SUB{<c>}{<q>} {<Rd>}, <Rn>, #<imm12> ; T4
            // SUB{<c>}{<q>} {<Rd>}, SP, #<imm12> ; T3
    "Subw"  // SUBW{<c>}{<q>} {<Rd>}, <Rn>, #<imm12> ; T4
            // SUBW{<c>}{<q>} {<Rd>}, SP, #<imm12> ; T3
  ],
  "description" : {
    "operands": [
      {
        "name": "cond",
        "type": "Always"
      },
      {
        "name": "rd",
        "type": "AllRegistersButPC"
      },
      {
        "name": "rn",
        "type": "AllRegistersButPC"
      },
      {
        "name": "op",
        "wrapper": "Operand",
        "operands": [
          {
            "name": "immediate",
            "type": "OffsetLowerThan4096"
          }
        ]
      }
    ],
    "inputs":[
      {
        "name": "rd",
        "type": "Register"
      },
      {
        "name": "rn",
        "type": "Register"
      }
    ]
  },
  "test-files": [
    {
      "type": "assembler",
      "test-cases": [
        {
          "name": "Operands",
          "operands": [
            "rd", "rn", "immediate"
          ],
          "operand-limit": 1000
        }
      ]
    },
    {
      "type": "simulator",
      "mnemonics" : [
        "Add",  // ADD{<c>}{<q>} {<Rd>}, <Rn>, #<imm12> ; T4
                // ADD{<c>}{<q>} {<Rd>}, SP, #<imm12> ; T4
        "Sub"   // SUB{<c>}{<q>} {<Rd>}, <Rn>, #<imm12> ; T4
                // SUB{<c>}{<q>} {<Rd>}, SP, #<imm12> ; T3
      ],
      "test-cases": [
        {
          "name": "RdIsRn",
          "operands": [
            "rd", "rn", "immediate"
          ],
          "inputs": [
            "rd", "rn"
          ],
          "operand-filter": "rd == rn",
          "operand-limit": 10,
          "input-filter": "rd == rn"
        },
        {
          "name": "RdIsNotRn",
          "operands": [
            "rd", "rn", "immediate"
          ],
          "inputs": [
            "rd", "rn"
          ],
          "operand-filter": "rd != rn",
          "operand-limit": 10
        },
        {
          "name": "Immediate",
          "operands": [
            "immediate"
          ],
          "operand-limit": 20,
          "inputs": [
            "rn"
          ]
        }
      ]
    }
  ]
}