xref: /third_party/vixl/test/aarch32/config/cond-rd-rn-operand-const-a32.json

// Copyright 2016, VIXL authors
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{
  "mnemonics" : [
    "Adc",  // ADC{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
    "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
    "Add",  // ADD{<c>}{<q>} <Rd>, PC, #<const> ; A1
            // ADD{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
            // ADD{<c>}{<q>} {<Rd>}, SP, #<const> ; A1
    "Adds", // ADDS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
            // ADDS{<c>}{<q>} {<Rd>}, SP, #<const> ; A1
    "And",  // AND{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
    "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
    "Bic",  // BIC{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
    "Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
    "Eor",  // EOR{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
    "Eors", // EORS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
    "Orr",  // ORR{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
    "Orrs", // ORRS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
    "Rsb",  // RSB{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
    "Rsbs", // RSBS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
    "Rsc",  // RSC{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
    "Rscs", // RSCS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
    "Sbc",  // SBC{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
    "Sbcs", // SBCS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
    "Sub",  // SUB{<c>}{<q>} <Rd>, PC, #<const> ; A2
            // SUB{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
            // SUB{<c>}{<q>} {<Rd>}, SP, #<const> ; A1
    "Subs"  // SUBS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
            // SUBS{<c>}{<q>} {<Rd>}, SP, #<const> ; A1
  ],
  "description" : {
    "operands": [
      {
        "name": "cond",
        "type": "Condition"
      },
      {
        "name": "rd",
        "type": "AllRegisters"
      },
      {
        "name": "rn",
        "type": "AllRegisters"
      },
      {
        "name": "op",
        "wrapper": "Operand",
        "operands": [
          {
            "name": "immediate",
            "type": "A32ModifiedImmediate"
          }
        ]
      }
    ],
    "inputs":[
      {
        "name": "apsr",
        "type": "NZCV"
      },
      {
        "name": "rd",
        "type": "Register"
      },
      {
        "name": "rn",
        "type": "Register"
      }
    ]
  },
  "test-files": [
    {
      "type": "assembler",
      "test-cases": [
        {
          "name": "Operands",
          "operands": [
            "cond", "rd", "rn", "immediate"
          ],
          "operand-limit": 500
        }
      ]
    },
    {
      "type": "simulator",
      "test-cases": [
        {
          "name": "Condition",
          "operands": [
            "cond"
          ],
          "inputs": [
            "apsr"
          ]
        },
        {
          "name": "RdIsRn",
          "operands": [
            "rd", "rn", "immediate"
          ],
          "inputs": [
            "rd", "rn"
          ],
          "operand-filter": "rd == rn",
          "operand-limit": 10,
          "input-filter": "rd == rn"
        },
        {
          "name": "RdIsNotRn",
          "operands": [
            "rd", "rn", "immediate"
          ],
          "inputs": [
            "rd", "rn"
          ],
          "operand-filter": "rd != rn",
          "operand-limit": 10
        },
        {
          "name": "ModifiedImmediate",
          "operands": [
            "immediate"
          ],
          "inputs": [
            "rn"
          ]
        }
      ]
    }
  ]
}