xref: /third_party/vixl/test/aarch32/config/cond-rd-pc-operand-imm8-t32.json (revision b8021494)

// Copyright 2016, VIXL authors
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// Test description for instructions of the following form:
//   MNEMONIC{<c>}.W <Rd>, PC, #<imm8> ; wide encoding

{
  "mnemonics" : [
    "Add" // ADD{<c>}{<q>} <Rd>, PC, #<imm8> ; T1
  ],
  "description" : {
    "operands": [
      {
        "name": "cond",
        "type": "Always"
      },
      {
        "name": "rd",
        "type": "LowRegisters"
      },
      {
        "name": "rn",
        "type": "RegisterPC"
      },
      {
        "name": "op",
        "wrapper": "Operand",
        "operands": [
          {
            "name": "immediate",
            "type": "OffsetLowerThan256"
          }
        ]
      }
    ],
    "inputs": []
  },
  "test-files": [
    {
      "type": "assembler",
      "test-cases": [
        {
          "name": "Operands",
          "operands": [
            "rd", "rn", "immediate"
          ],
          "operand-limit": 1000
        }
      ]
    }
  ]
}