1b8021494Sopenharmony_ci// Copyright 2016, VIXL authors
2b8021494Sopenharmony_ci// All rights reserved.
3b8021494Sopenharmony_ci//
4b8021494Sopenharmony_ci// Redistribution and use in source and binary forms, with or without
5b8021494Sopenharmony_ci// modification, are permitted provided that the following conditions are met:
6b8021494Sopenharmony_ci//
7b8021494Sopenharmony_ci//   * Redistributions of source code must retain the above copyright notice,
8b8021494Sopenharmony_ci//     this list of conditions and the following disclaimer.
9b8021494Sopenharmony_ci//   * Redistributions in binary form must reproduce the above copyright notice,
10b8021494Sopenharmony_ci//     this list of conditions and the following disclaimer in the documentation
11b8021494Sopenharmony_ci//     and/or other materials provided with the distribution.
12b8021494Sopenharmony_ci//   * Neither the name of ARM Limited nor the names of its contributors may be
13b8021494Sopenharmony_ci//     used to endorse or promote products derived from this software without
14b8021494Sopenharmony_ci//     specific prior written permission.
15b8021494Sopenharmony_ci//
16b8021494Sopenharmony_ci// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
17b8021494Sopenharmony_ci// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18b8021494Sopenharmony_ci// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19b8021494Sopenharmony_ci// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
20b8021494Sopenharmony_ci// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21b8021494Sopenharmony_ci// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22b8021494Sopenharmony_ci// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
23b8021494Sopenharmony_ci// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24b8021494Sopenharmony_ci// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25b8021494Sopenharmony_ci// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26b8021494Sopenharmony_ci
27b8021494Sopenharmony_ci// Test description for instructions of the following form:
28b8021494Sopenharmony_ci//   MNEMONIC{<c>}.N <Rdm>, <Rdm>, ASR <Rs>
29b8021494Sopenharmony_ci//   MNEMONIC{<c>}.N <Rdm>, <Rdm>, LSL <Rs>
30b8021494Sopenharmony_ci//   MNEMONIC{<c>}.N <Rdm>, <Rdm>, LSR <Rs>
31b8021494Sopenharmony_ci//   MNEMONIC{<c>}.N <Rdm>, <Rdm>, ROR <Rs>
32b8021494Sopenharmony_ci//   MNEMONIC{<c>}.W <Rd>, <Rm>, <shift> <Rs>
33b8021494Sopenharmony_ci
34b8021494Sopenharmony_ci{
35b8021494Sopenharmony_ci  "mnemonics": [
36b8021494Sopenharmony_ci    "Mov", // MOV<c>{<q>} <Rdm>, <Rdm>, ASR <Rs> ; T1
37b8021494Sopenharmony_ci           // MOV<c>{<q>} <Rdm>, <Rdm>, LSL <Rs> ; T1
38b8021494Sopenharmony_ci           // MOV<c>{<q>} <Rdm>, <Rdm>, LSR <Rs> ; T1
39b8021494Sopenharmony_ci           // MOV<c>{<q>} <Rdm>, <Rdm>, ROR <Rs> ; T1
40b8021494Sopenharmony_ci           // MOV{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> ; T2
41b8021494Sopenharmony_ci    "Movs" // MOVS{<q>} <Rdm>, <Rdm>, ASR <Rs> ; T1
42b8021494Sopenharmony_ci           // MOVS{<q>} <Rdm>, <Rdm>, LSL <Rs> ; T1
43b8021494Sopenharmony_ci           // MOVS{<q>} <Rdm>, <Rdm>, LSR <Rs> ; T1
44b8021494Sopenharmony_ci           // MOVS{<q>} <Rdm>, <Rdm>, ROR <Rs> ; T1
45b8021494Sopenharmony_ci           // MOVS{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> ; T2
46b8021494Sopenharmony_ci  ],
47b8021494Sopenharmony_ci  "description" : {
48b8021494Sopenharmony_ci    "operands": [
49b8021494Sopenharmony_ci      {
50b8021494Sopenharmony_ci        "name": "cond",
51b8021494Sopenharmony_ci        "type": "Condition"
52b8021494Sopenharmony_ci      },
53b8021494Sopenharmony_ci      {
54b8021494Sopenharmony_ci        "name": "rd",
55b8021494Sopenharmony_ci        "type": "AllRegistersButPC"
56b8021494Sopenharmony_ci      },
57b8021494Sopenharmony_ci      {
58b8021494Sopenharmony_ci        "name": "op",
59b8021494Sopenharmony_ci        "wrapper": "Operand",
60b8021494Sopenharmony_ci        "operands": [
61b8021494Sopenharmony_ci          {
62b8021494Sopenharmony_ci            "name": "rn",
63b8021494Sopenharmony_ci            "type": "AllRegistersButPC"
64b8021494Sopenharmony_ci          },
65b8021494Sopenharmony_ci          {
66b8021494Sopenharmony_ci            "name": "shift",
67b8021494Sopenharmony_ci            "type": "Shift"
68b8021494Sopenharmony_ci          },
69b8021494Sopenharmony_ci          {
70b8021494Sopenharmony_ci            "name": "rs",
71b8021494Sopenharmony_ci            "type": "AllRegistersButPC"
72b8021494Sopenharmony_ci          }
73b8021494Sopenharmony_ci        ]
74b8021494Sopenharmony_ci      }
75b8021494Sopenharmony_ci    ],
76b8021494Sopenharmony_ci    "inputs": [
77b8021494Sopenharmony_ci      {
78b8021494Sopenharmony_ci        "name": "apsr",
79b8021494Sopenharmony_ci        "type": "NZCV"
80b8021494Sopenharmony_ci      },
81b8021494Sopenharmony_ci      {
82b8021494Sopenharmony_ci        "name": "rd",
83b8021494Sopenharmony_ci        "type": "Register"
84b8021494Sopenharmony_ci      },
85b8021494Sopenharmony_ci      {
86b8021494Sopenharmony_ci        "name": "rn",
87b8021494Sopenharmony_ci        "type": "Register"
88b8021494Sopenharmony_ci      },
89b8021494Sopenharmony_ci      {
90b8021494Sopenharmony_ci        "name": "rs",
91b8021494Sopenharmony_ci        "type": "RegisterShift"
92b8021494Sopenharmony_ci      }
93b8021494Sopenharmony_ci    ]
94b8021494Sopenharmony_ci  },
95b8021494Sopenharmony_ci  "test-files": [
96b8021494Sopenharmony_ci    {
97b8021494Sopenharmony_ci      "type": "assembler",
98b8021494Sopenharmony_ci      "test-cases": [
99b8021494Sopenharmony_ci        {
100b8021494Sopenharmony_ci          "name": "Unconditional",
101b8021494Sopenharmony_ci          "operands": [
102b8021494Sopenharmony_ci            "cond", "rd", "rn", "shift", "rs"
103b8021494Sopenharmony_ci          ],
104b8021494Sopenharmony_ci          "operand-filter": "cond == 'al'",
105b8021494Sopenharmony_ci          "operand-limit": 1000
106b8021494Sopenharmony_ci        }
107b8021494Sopenharmony_ci      ]
108b8021494Sopenharmony_ci    },
109b8021494Sopenharmony_ci    {
110b8021494Sopenharmony_ci      "name": "narrow-out-it-block",
111b8021494Sopenharmony_ci      "type": "assembler",
112b8021494Sopenharmony_ci      "mnemonics" : [
113b8021494Sopenharmony_ci        "Movs" // MOVS{<q>} <Rdm>, <Rdm>, ASR <Rs> ; T1
114b8021494Sopenharmony_ci               // MOVS{<q>} <Rdm>, <Rdm>, LSL <Rs> ; T1
115b8021494Sopenharmony_ci               // MOVS{<q>} <Rdm>, <Rdm>, LSR <Rs> ; T1
116b8021494Sopenharmony_ci               // MOVS{<q>} <Rdm>, <Rdm>, ROR <Rs> ; T1
117b8021494Sopenharmony_ci      ],
118b8021494Sopenharmony_ci      "test-cases": [
119b8021494Sopenharmony_ci        {
120b8021494Sopenharmony_ci          "name": "OutITBlock",
121b8021494Sopenharmony_ci          "operands": [
122b8021494Sopenharmony_ci            "cond", "rd", "rn", "shift", "rs"
123b8021494Sopenharmony_ci          ],
124b8021494Sopenharmony_ci          "operand-filter": "cond == 'al' and rd == rn and register_is_low(rd) and register_is_low(rs)"
125b8021494Sopenharmony_ci        }
126b8021494Sopenharmony_ci      ]
127b8021494Sopenharmony_ci    },
128b8021494Sopenharmony_ci    {
129b8021494Sopenharmony_ci      "name": "in-it-block",
130b8021494Sopenharmony_ci      "type": "assembler",
131b8021494Sopenharmony_ci      "mnemonics" : [
132b8021494Sopenharmony_ci        "Mov" // MOV<c>{<q>} <Rdm>, <Rdm>, ASR <Rs> ; T1
133b8021494Sopenharmony_ci              // MOV<c>{<q>} <Rdm>, <Rdm>, LSL <Rs> ; T1
134b8021494Sopenharmony_ci              // MOV<c>{<q>} <Rdm>, <Rdm>, LSR <Rs> ; T1
135b8021494Sopenharmony_ci              // MOV<c>{<q>} <Rdm>, <Rdm>, ROR <Rs> ; T1
136b8021494Sopenharmony_ci      ],
137b8021494Sopenharmony_ci      "test-cases": [
138b8021494Sopenharmony_ci        {
139b8021494Sopenharmony_ci          "name": "InITBlock",
140b8021494Sopenharmony_ci          "operands": [
141b8021494Sopenharmony_ci            "cond", "rd", "rn", "shift", "rs"
142b8021494Sopenharmony_ci          ],
143b8021494Sopenharmony_ci          // Generate an extra IT instruction.
144b8021494Sopenharmony_ci          "in-it-block": "{cond}",
145b8021494Sopenharmony_ci          "operand-filter": "cond != 'al' and rd == rn and register_is_low(rd) and register_is_low(rs)",
146b8021494Sopenharmony_ci          "operand-limit": 1000
147b8021494Sopenharmony_ci        }
148b8021494Sopenharmony_ci      ]
149b8021494Sopenharmony_ci    },
150b8021494Sopenharmony_ci    {
151b8021494Sopenharmony_ci      "type": "simulator",
152b8021494Sopenharmony_ci      "test-cases": [
153b8021494Sopenharmony_ci        {
154b8021494Sopenharmony_ci          "name": "Condition",
155b8021494Sopenharmony_ci          "operands": [
156b8021494Sopenharmony_ci            "cond"
157b8021494Sopenharmony_ci          ],
158b8021494Sopenharmony_ci          "inputs": [
159b8021494Sopenharmony_ci            "apsr"
160b8021494Sopenharmony_ci          ]
161b8021494Sopenharmony_ci        },
162b8021494Sopenharmony_ci        // Test combinations of registers values with rd == rn.
163b8021494Sopenharmony_ci        {
164b8021494Sopenharmony_ci          "name": "RdIsRn",
165b8021494Sopenharmony_ci          "operands": [
166b8021494Sopenharmony_ci            "rd", "rn"
167b8021494Sopenharmony_ci          ],
168b8021494Sopenharmony_ci          "inputs": [
169b8021494Sopenharmony_ci            "rd", "rn"
170b8021494Sopenharmony_ci          ],
171b8021494Sopenharmony_ci          "operand-filter": "rd == rn",
172b8021494Sopenharmony_ci          "input-filter": "rd == rn"
173b8021494Sopenharmony_ci        },
174b8021494Sopenharmony_ci        // Test combinations of registers values with rd != rn.
175b8021494Sopenharmony_ci        {
176b8021494Sopenharmony_ci          "name": "RdIsNotRn",
177b8021494Sopenharmony_ci          "operands": [
178b8021494Sopenharmony_ci            "rd", "rn"
179b8021494Sopenharmony_ci          ],
180b8021494Sopenharmony_ci          "inputs": [
181b8021494Sopenharmony_ci            "rd", "rn"
182b8021494Sopenharmony_ci          ],
183b8021494Sopenharmony_ci          "operand-filter": "rd != rn",
184b8021494Sopenharmony_ci          "operand-limit": 10,
185b8021494Sopenharmony_ci          "input-limit": 200
186b8021494Sopenharmony_ci        },
187b8021494Sopenharmony_ci        // Test combinations of shift types and register values.
188b8021494Sopenharmony_ci        {
189b8021494Sopenharmony_ci          "name": "ShiftTypes",
190b8021494Sopenharmony_ci          "operands": [
191b8021494Sopenharmony_ci            "rn", "shift", "rs"
192b8021494Sopenharmony_ci          ],
193b8021494Sopenharmony_ci          "inputs": [
194b8021494Sopenharmony_ci            "rn", "rs"
195b8021494Sopenharmony_ci          ],
196b8021494Sopenharmony_ci          // Make sure the registers are different.
197b8021494Sopenharmony_ci          "operand-filter": "rn == 'r1' and rs == 'r2'"
198b8021494Sopenharmony_ci        }
199b8021494Sopenharmony_ci      ]
200b8021494Sopenharmony_ci    }
201b8021494Sopenharmony_ci  ]
202b8021494Sopenharmony_ci}
203