1b8021494Sopenharmony_ci// Copyright 2016, VIXL authors 2b8021494Sopenharmony_ci// All rights reserved. 3b8021494Sopenharmony_ci// 4b8021494Sopenharmony_ci// Redistribution and use in source and binary forms, with or without 5b8021494Sopenharmony_ci// modification, are permitted provided that the following conditions are met: 6b8021494Sopenharmony_ci// 7b8021494Sopenharmony_ci// * Redistributions of source code must retain the above copyright notice, 8b8021494Sopenharmony_ci// this list of conditions and the following disclaimer. 9b8021494Sopenharmony_ci// * Redistributions in binary form must reproduce the above copyright notice, 10b8021494Sopenharmony_ci// this list of conditions and the following disclaimer in the documentation 11b8021494Sopenharmony_ci// and/or other materials provided with the distribution. 12b8021494Sopenharmony_ci// * Neither the name of ARM Limited nor the names of its contributors may be 13b8021494Sopenharmony_ci// used to endorse or promote products derived from this software without 14b8021494Sopenharmony_ci// specific prior written permission. 15b8021494Sopenharmony_ci// 16b8021494Sopenharmony_ci// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17b8021494Sopenharmony_ci// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18b8021494Sopenharmony_ci// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19b8021494Sopenharmony_ci// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20b8021494Sopenharmony_ci// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21b8021494Sopenharmony_ci// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22b8021494Sopenharmony_ci// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23b8021494Sopenharmony_ci// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24b8021494Sopenharmony_ci// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25b8021494Sopenharmony_ci// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26b8021494Sopenharmony_ci 27b8021494Sopenharmony_ci{ 28b8021494Sopenharmony_ci "mnemonics": [ 29b8021494Sopenharmony_ci "Cmn", // CMN{<c>}{<q>} <Rn>, <Rm>, <shift> <Rs> ; A1 30b8021494Sopenharmony_ci "Cmp", // CMP{<c>}{<q>} <Rn>, <Rm>, <shift> <Rs> ; A1 31b8021494Sopenharmony_ci "Mov", // MOV{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> ; A1 32b8021494Sopenharmony_ci "Movs", // MOVS{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> ; A1 33b8021494Sopenharmony_ci "Mvn", // MVN{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> ; A1 34b8021494Sopenharmony_ci "Mvns", // MVNS{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> ; A1 35b8021494Sopenharmony_ci "Teq", // TEQ{<c>}{<q>} <Rn>, <Rm>, <shift> <Rs> ; A1 36b8021494Sopenharmony_ci "Tst" // TST{<c>}{<q>} <Rn>, <Rm>, <shift> <Rs> ; A1 37b8021494Sopenharmony_ci ], 38b8021494Sopenharmony_ci "description" : { 39b8021494Sopenharmony_ci "operands": [ 40b8021494Sopenharmony_ci { 41b8021494Sopenharmony_ci "name": "cond", 42b8021494Sopenharmony_ci "type": "Condition" 43b8021494Sopenharmony_ci }, 44b8021494Sopenharmony_ci { 45b8021494Sopenharmony_ci "name": "rd", 46b8021494Sopenharmony_ci "type": "AllRegistersButPC" 47b8021494Sopenharmony_ci }, 48b8021494Sopenharmony_ci { 49b8021494Sopenharmony_ci "name": "op", 50b8021494Sopenharmony_ci "wrapper": "Operand", 51b8021494Sopenharmony_ci "operands": [ 52b8021494Sopenharmony_ci { 53b8021494Sopenharmony_ci "name": "rn", 54b8021494Sopenharmony_ci "type": "AllRegistersButPC" 55b8021494Sopenharmony_ci }, 56b8021494Sopenharmony_ci { 57b8021494Sopenharmony_ci "name": "shift", 58b8021494Sopenharmony_ci "type": "Shift" 59b8021494Sopenharmony_ci }, 60b8021494Sopenharmony_ci { 61b8021494Sopenharmony_ci "name": "rs", 62b8021494Sopenharmony_ci "type": "AllRegistersButPC" 63b8021494Sopenharmony_ci } 64b8021494Sopenharmony_ci ] 65b8021494Sopenharmony_ci } 66b8021494Sopenharmony_ci ], 67b8021494Sopenharmony_ci "inputs": [ 68b8021494Sopenharmony_ci { 69b8021494Sopenharmony_ci "name": "apsr", 70b8021494Sopenharmony_ci "type": "NZCV" 71b8021494Sopenharmony_ci }, 72b8021494Sopenharmony_ci { 73b8021494Sopenharmony_ci "name": "rd", 74b8021494Sopenharmony_ci "type": "Register" 75b8021494Sopenharmony_ci }, 76b8021494Sopenharmony_ci { 77b8021494Sopenharmony_ci "name": "rn", 78b8021494Sopenharmony_ci "type": "Register" 79b8021494Sopenharmony_ci }, 80b8021494Sopenharmony_ci { 81b8021494Sopenharmony_ci "name": "rs", 82b8021494Sopenharmony_ci "type": "RegisterShift" 83b8021494Sopenharmony_ci } 84b8021494Sopenharmony_ci ] 85b8021494Sopenharmony_ci }, 86b8021494Sopenharmony_ci "test-files": [ 87b8021494Sopenharmony_ci { 88b8021494Sopenharmony_ci "type": "assembler", 89b8021494Sopenharmony_ci "test-cases": [ 90b8021494Sopenharmony_ci { 91b8021494Sopenharmony_ci "name": "Operands", 92b8021494Sopenharmony_ci "operands": [ 93b8021494Sopenharmony_ci "cond", "rd", "rn", "shift", "rs" 94b8021494Sopenharmony_ci ], 95b8021494Sopenharmony_ci "operand-limit": 1000 96b8021494Sopenharmony_ci } 97b8021494Sopenharmony_ci ] 98b8021494Sopenharmony_ci }, 99b8021494Sopenharmony_ci { 100b8021494Sopenharmony_ci "type": "simulator", 101b8021494Sopenharmony_ci "test-cases": [ 102b8021494Sopenharmony_ci { 103b8021494Sopenharmony_ci "name": "Condition", 104b8021494Sopenharmony_ci "operands": [ 105b8021494Sopenharmony_ci "cond" 106b8021494Sopenharmony_ci ], 107b8021494Sopenharmony_ci "inputs": [ 108b8021494Sopenharmony_ci "apsr" 109b8021494Sopenharmony_ci ] 110b8021494Sopenharmony_ci }, 111b8021494Sopenharmony_ci // Test combinations of registers values with rd == rn. 112b8021494Sopenharmony_ci { 113b8021494Sopenharmony_ci "name": "RdIsRn", 114b8021494Sopenharmony_ci "operands": [ 115b8021494Sopenharmony_ci "rd", "rn" 116b8021494Sopenharmony_ci ], 117b8021494Sopenharmony_ci "inputs": [ 118b8021494Sopenharmony_ci "rd", "rn" 119b8021494Sopenharmony_ci ], 120b8021494Sopenharmony_ci "operand-filter": "rd == rn", 121b8021494Sopenharmony_ci "input-filter": "rd == rn" 122b8021494Sopenharmony_ci }, 123b8021494Sopenharmony_ci // Test combinations of registers values with rd != rn. 124b8021494Sopenharmony_ci { 125b8021494Sopenharmony_ci "name": "RdIsNotRn", 126b8021494Sopenharmony_ci "operands": [ 127b8021494Sopenharmony_ci "rd", "rn" 128b8021494Sopenharmony_ci ], 129b8021494Sopenharmony_ci "inputs": [ 130b8021494Sopenharmony_ci "rd", "rn" 131b8021494Sopenharmony_ci ], 132b8021494Sopenharmony_ci "operand-filter": "rd != rn", 133b8021494Sopenharmony_ci "operand-limit": 10, 134b8021494Sopenharmony_ci "input-limit": 200 135b8021494Sopenharmony_ci }, 136b8021494Sopenharmony_ci // Test combinations of shift types and register values. 137b8021494Sopenharmony_ci { 138b8021494Sopenharmony_ci "name": "ShiftTypes", 139b8021494Sopenharmony_ci "operands": [ 140b8021494Sopenharmony_ci "rn", "shift", "rs" 141b8021494Sopenharmony_ci ], 142b8021494Sopenharmony_ci "inputs": [ 143b8021494Sopenharmony_ci "rn", "rs" 144b8021494Sopenharmony_ci ], 145b8021494Sopenharmony_ci // Make sure the registers are different. 146b8021494Sopenharmony_ci "operand-filter": "rn == 'r1' and rs == 'r2'" 147b8021494Sopenharmony_ci } 148b8021494Sopenharmony_ci ] 149b8021494Sopenharmony_ci } 150b8021494Sopenharmony_ci ] 151b8021494Sopenharmony_ci} 152