1b8021494Sopenharmony_ci// Copyright 2016, VIXL authors 2b8021494Sopenharmony_ci// All rights reserved. 3b8021494Sopenharmony_ci// 4b8021494Sopenharmony_ci// Redistribution and use in source and binary forms, with or without 5b8021494Sopenharmony_ci// modification, are permitted provided that the following conditions are met: 6b8021494Sopenharmony_ci// 7b8021494Sopenharmony_ci// * Redistributions of source code must retain the above copyright notice, 8b8021494Sopenharmony_ci// this list of conditions and the following disclaimer. 9b8021494Sopenharmony_ci// * Redistributions in binary form must reproduce the above copyright notice, 10b8021494Sopenharmony_ci// this list of conditions and the following disclaimer in the documentation 11b8021494Sopenharmony_ci// and/or other materials provided with the distribution. 12b8021494Sopenharmony_ci// * Neither the name of ARM Limited nor the names of its contributors may be 13b8021494Sopenharmony_ci// used to endorse or promote products derived from this software without 14b8021494Sopenharmony_ci// specific prior written permission. 15b8021494Sopenharmony_ci// 16b8021494Sopenharmony_ci// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17b8021494Sopenharmony_ci// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18b8021494Sopenharmony_ci// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19b8021494Sopenharmony_ci// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20b8021494Sopenharmony_ci// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21b8021494Sopenharmony_ci// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22b8021494Sopenharmony_ci// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23b8021494Sopenharmony_ci// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24b8021494Sopenharmony_ci// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25b8021494Sopenharmony_ci// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26b8021494Sopenharmony_ci 27b8021494Sopenharmony_ci// Test description for instructions of the following form: 28b8021494Sopenharmony_ci// MNEMONIC{<c>}.W <Rd>, <Rn>, ROR #<amount> 29b8021494Sopenharmony_ci 30b8021494Sopenharmony_ci{ 31b8021494Sopenharmony_ci "mnemonics": [ 32b8021494Sopenharmony_ci "Sxtb", // SXTB{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T2 33b8021494Sopenharmony_ci "Sxtb16", // SXTB16{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T1 34b8021494Sopenharmony_ci "Sxth", // SXTH{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T2 35b8021494Sopenharmony_ci "Uxtb", // UXTB{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T2 36b8021494Sopenharmony_ci "Uxtb16", // UXTB16{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T1 37b8021494Sopenharmony_ci "Uxth" // UXTH{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T2 38b8021494Sopenharmony_ci ], 39b8021494Sopenharmony_ci "description": { 40b8021494Sopenharmony_ci "operands": [ 41b8021494Sopenharmony_ci { 42b8021494Sopenharmony_ci "name": "cond", 43b8021494Sopenharmony_ci "type": "Condition" 44b8021494Sopenharmony_ci }, 45b8021494Sopenharmony_ci { 46b8021494Sopenharmony_ci "name": "rd", 47b8021494Sopenharmony_ci "type": "AllRegistersButPC" 48b8021494Sopenharmony_ci }, 49b8021494Sopenharmony_ci { 50b8021494Sopenharmony_ci "name": "op", 51b8021494Sopenharmony_ci "wrapper": "Operand", 52b8021494Sopenharmony_ci "operands": [ 53b8021494Sopenharmony_ci { 54b8021494Sopenharmony_ci "name": "rn", 55b8021494Sopenharmony_ci "type": "AllRegistersButPC" 56b8021494Sopenharmony_ci }, 57b8021494Sopenharmony_ci { 58b8021494Sopenharmony_ci "name": "ror", 59b8021494Sopenharmony_ci "type": "ShiftROR" 60b8021494Sopenharmony_ci }, 61b8021494Sopenharmony_ci { 62b8021494Sopenharmony_ci "name": "amount", 63b8021494Sopenharmony_ci "type": "ShiftRotationAmountX8" 64b8021494Sopenharmony_ci } 65b8021494Sopenharmony_ci ] 66b8021494Sopenharmony_ci } 67b8021494Sopenharmony_ci ], 68b8021494Sopenharmony_ci "inputs": [ 69b8021494Sopenharmony_ci { 70b8021494Sopenharmony_ci "name": "apsr", 71b8021494Sopenharmony_ci "type": "NZCV" 72b8021494Sopenharmony_ci }, 73b8021494Sopenharmony_ci { 74b8021494Sopenharmony_ci "name": "rd", 75b8021494Sopenharmony_ci "type": "Register" 76b8021494Sopenharmony_ci }, 77b8021494Sopenharmony_ci { 78b8021494Sopenharmony_ci "name": "rn", 79b8021494Sopenharmony_ci "type": "Register" 80b8021494Sopenharmony_ci } 81b8021494Sopenharmony_ci ] 82b8021494Sopenharmony_ci }, 83b8021494Sopenharmony_ci "test-files": [ 84b8021494Sopenharmony_ci { 85b8021494Sopenharmony_ci "type": "assembler", 86b8021494Sopenharmony_ci "test-cases": [ 87b8021494Sopenharmony_ci { 88b8021494Sopenharmony_ci "name": "Operands", 89b8021494Sopenharmony_ci "operands": [ 90b8021494Sopenharmony_ci "cond", "rd", "rn", "ror", "amount" 91b8021494Sopenharmony_ci ], 92b8021494Sopenharmony_ci "operand-filter": "cond == 'al'" 93b8021494Sopenharmony_ci } 94b8021494Sopenharmony_ci ] 95b8021494Sopenharmony_ci }, 96b8021494Sopenharmony_ci { 97b8021494Sopenharmony_ci "type": "simulator", 98b8021494Sopenharmony_ci "test-cases": [ 99b8021494Sopenharmony_ci { 100b8021494Sopenharmony_ci "name": "Condition", 101b8021494Sopenharmony_ci "operands": [ 102b8021494Sopenharmony_ci "cond" 103b8021494Sopenharmony_ci ], 104b8021494Sopenharmony_ci "inputs": [ 105b8021494Sopenharmony_ci "apsr" 106b8021494Sopenharmony_ci ] 107b8021494Sopenharmony_ci }, 108b8021494Sopenharmony_ci // Test combinations of registers values with rd == rn. 109b8021494Sopenharmony_ci { 110b8021494Sopenharmony_ci "name": "RdIsRn", 111b8021494Sopenharmony_ci "operands": [ 112b8021494Sopenharmony_ci "rd", "rn" 113b8021494Sopenharmony_ci ], 114b8021494Sopenharmony_ci "inputs": [ 115b8021494Sopenharmony_ci "rd", "rn" 116b8021494Sopenharmony_ci ], 117b8021494Sopenharmony_ci "operand-filter": "rd == rn", 118b8021494Sopenharmony_ci "input-filter": "rd == rn" 119b8021494Sopenharmony_ci }, 120b8021494Sopenharmony_ci // Test combinations of registers values. 121b8021494Sopenharmony_ci { 122b8021494Sopenharmony_ci "name": "RdIsNotRn", 123b8021494Sopenharmony_ci "operands": [ 124b8021494Sopenharmony_ci "rd", "rn" 125b8021494Sopenharmony_ci ], 126b8021494Sopenharmony_ci "inputs": [ 127b8021494Sopenharmony_ci "rd", "rn" 128b8021494Sopenharmony_ci ], 129b8021494Sopenharmony_ci "operand-filter": "rd != rn", 130b8021494Sopenharmony_ci "operand-limit": 10, 131b8021494Sopenharmony_ci "input-limit": 200 132b8021494Sopenharmony_ci }, 133b8021494Sopenharmony_ci // Test combinations of rotation amounts. 134b8021494Sopenharmony_ci { 135b8021494Sopenharmony_ci "name": "Rotations", 136b8021494Sopenharmony_ci "operands": [ 137b8021494Sopenharmony_ci "rd", "rn", "ror", "amount" 138b8021494Sopenharmony_ci ], 139b8021494Sopenharmony_ci "inputs": [ 140b8021494Sopenharmony_ci "rn" 141b8021494Sopenharmony_ci ], 142b8021494Sopenharmony_ci // Specify exactly what registers to use in this test to make sure 143b8021494Sopenharmony_ci // that they are different. It makes the execution trace more 144b8021494Sopenharmony_ci // understandable. 145b8021494Sopenharmony_ci "operand-filter": "rd == 'r0' and rn == 'r1'" 146b8021494Sopenharmony_ci } 147b8021494Sopenharmony_ci ] 148b8021494Sopenharmony_ci } 149b8021494Sopenharmony_ci ] 150b8021494Sopenharmony_ci} 151