1b8021494Sopenharmony_ci// Copyright 2016, VIXL authors 2b8021494Sopenharmony_ci// All rights reserved. 3b8021494Sopenharmony_ci// 4b8021494Sopenharmony_ci// Redistribution and use in source and binary forms, with or without 5b8021494Sopenharmony_ci// modification, are permitted provided that the following conditions are met: 6b8021494Sopenharmony_ci// 7b8021494Sopenharmony_ci// * Redistributions of source code must retain the above copyright notice, 8b8021494Sopenharmony_ci// this list of conditions and the following disclaimer. 9b8021494Sopenharmony_ci// * Redistributions in binary form must reproduce the above copyright notice, 10b8021494Sopenharmony_ci// this list of conditions and the following disclaimer in the documentation 11b8021494Sopenharmony_ci// and/or other materials provided with the distribution. 12b8021494Sopenharmony_ci// * Neither the name of ARM Limited nor the names of its contributors may be 13b8021494Sopenharmony_ci// used to endorse or promote products derived from this software without 14b8021494Sopenharmony_ci// specific prior written permission. 15b8021494Sopenharmony_ci// 16b8021494Sopenharmony_ci// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17b8021494Sopenharmony_ci// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18b8021494Sopenharmony_ci// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19b8021494Sopenharmony_ci// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20b8021494Sopenharmony_ci// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21b8021494Sopenharmony_ci// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22b8021494Sopenharmony_ci// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23b8021494Sopenharmony_ci// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24b8021494Sopenharmony_ci// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25b8021494Sopenharmony_ci// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26b8021494Sopenharmony_ci 27b8021494Sopenharmony_ci// Test description for instructions of the following forms: 28b8021494Sopenharmony_ci// MNEMONIC{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } 29b8021494Sopenharmony_ci// MNEMONIC{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } 30b8021494Sopenharmony_ci// 31b8021494Sopenharmony_ci// Note that this test only covers the cases where the optional shift 32b8021494Sopenharmony_ci// operand is not provided. The shift operands are tested in 33b8021494Sopenharmony_ci// "cond-rd-operand-rn-shift-amount-*-a32.json". 34b8021494Sopenharmony_ci 35b8021494Sopenharmony_ci{ 36b8021494Sopenharmony_ci "mnemonics" : [ 37b8021494Sopenharmony_ci "Cmn", // CMN{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; A1 38b8021494Sopenharmony_ci "Cmp", // CMP{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; A1 39b8021494Sopenharmony_ci "Mov", // MOV{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; A1 40b8021494Sopenharmony_ci "Movs", // MOVS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; A1 41b8021494Sopenharmony_ci "Mvn", // MVN{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; A1 42b8021494Sopenharmony_ci "Mvns", // MVNS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; A1 43b8021494Sopenharmony_ci "Teq", // TEQ{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; A1 44b8021494Sopenharmony_ci "Tst", // TST{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; A1 45b8021494Sopenharmony_ci 46b8021494Sopenharmony_ci "Sxtb", // SXTB{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1 47b8021494Sopenharmony_ci "Sxtb16", // SXTB16{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1 48b8021494Sopenharmony_ci "Sxth", // SXTH{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1 49b8021494Sopenharmony_ci "Uxtb", // UXTB{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1 50b8021494Sopenharmony_ci "Uxtb16", // UXTB16{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1 51b8021494Sopenharmony_ci "Uxth" // UXTH{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1 52b8021494Sopenharmony_ci ], 53b8021494Sopenharmony_ci "description" : { 54b8021494Sopenharmony_ci "operands": [ 55b8021494Sopenharmony_ci { 56b8021494Sopenharmony_ci "name": "cond", 57b8021494Sopenharmony_ci "type": "Condition" 58b8021494Sopenharmony_ci }, 59b8021494Sopenharmony_ci { 60b8021494Sopenharmony_ci "name": "rd", 61b8021494Sopenharmony_ci "type": "AllRegistersButPC" 62b8021494Sopenharmony_ci }, 63b8021494Sopenharmony_ci { 64b8021494Sopenharmony_ci "name": "op", 65b8021494Sopenharmony_ci "wrapper": "Operand", 66b8021494Sopenharmony_ci "operands": [ 67b8021494Sopenharmony_ci { 68b8021494Sopenharmony_ci "name": "rn", 69b8021494Sopenharmony_ci "type": "AllRegistersButPC" 70b8021494Sopenharmony_ci } 71b8021494Sopenharmony_ci ] 72b8021494Sopenharmony_ci } 73b8021494Sopenharmony_ci ], 74b8021494Sopenharmony_ci "inputs": [ 75b8021494Sopenharmony_ci { 76b8021494Sopenharmony_ci "name": "apsr", 77b8021494Sopenharmony_ci "type": "NZCV" 78b8021494Sopenharmony_ci }, 79b8021494Sopenharmony_ci { 80b8021494Sopenharmony_ci "name": "rd", 81b8021494Sopenharmony_ci "type": "Register" 82b8021494Sopenharmony_ci }, 83b8021494Sopenharmony_ci { 84b8021494Sopenharmony_ci "name": "rn", 85b8021494Sopenharmony_ci "type": "Register" 86b8021494Sopenharmony_ci } 87b8021494Sopenharmony_ci ] 88b8021494Sopenharmony_ci }, 89b8021494Sopenharmony_ci "test-files": [ 90b8021494Sopenharmony_ci { 91b8021494Sopenharmony_ci "type": "assembler", 92b8021494Sopenharmony_ci "test-cases": [ 93b8021494Sopenharmony_ci { 94b8021494Sopenharmony_ci "name": "Operands", 95b8021494Sopenharmony_ci "operands": [ 96b8021494Sopenharmony_ci "cond", "rd", "rn" 97b8021494Sopenharmony_ci ], 98b8021494Sopenharmony_ci "operand-limit": 1000 99b8021494Sopenharmony_ci } 100b8021494Sopenharmony_ci ] 101b8021494Sopenharmony_ci }, 102b8021494Sopenharmony_ci { 103b8021494Sopenharmony_ci "type": "simulator", 104b8021494Sopenharmony_ci "test-cases": [ 105b8021494Sopenharmony_ci { 106b8021494Sopenharmony_ci "name": "Condition", 107b8021494Sopenharmony_ci "operands": [ 108b8021494Sopenharmony_ci "cond" 109b8021494Sopenharmony_ci ], 110b8021494Sopenharmony_ci "inputs": [ 111b8021494Sopenharmony_ci "apsr" 112b8021494Sopenharmony_ci ] 113b8021494Sopenharmony_ci }, 114b8021494Sopenharmony_ci // Test combinations of registers values with rd == rn. 115b8021494Sopenharmony_ci { 116b8021494Sopenharmony_ci "name": "RdIsRn", 117b8021494Sopenharmony_ci "operands": [ 118b8021494Sopenharmony_ci "rd", "rn" 119b8021494Sopenharmony_ci ], 120b8021494Sopenharmony_ci "inputs": [ 121b8021494Sopenharmony_ci "rd", "rn" 122b8021494Sopenharmony_ci ], 123b8021494Sopenharmony_ci "operand-filter": "rd == rn", 124b8021494Sopenharmony_ci "input-filter": "rd == rn" 125b8021494Sopenharmony_ci }, 126b8021494Sopenharmony_ci // Test combinations of registers values. 127b8021494Sopenharmony_ci { 128b8021494Sopenharmony_ci "name": "RdIsNotRn", 129b8021494Sopenharmony_ci "operands": [ 130b8021494Sopenharmony_ci "rd", "rn" 131b8021494Sopenharmony_ci ], 132b8021494Sopenharmony_ci "inputs": [ 133b8021494Sopenharmony_ci "rd", "rn" 134b8021494Sopenharmony_ci ], 135b8021494Sopenharmony_ci "operand-filter": "rd != rn", 136b8021494Sopenharmony_ci "operand-limit": 10, 137b8021494Sopenharmony_ci "input-limit": 200 138b8021494Sopenharmony_ci } 139b8021494Sopenharmony_ci ] 140b8021494Sopenharmony_ci } 141b8021494Sopenharmony_ci ] 142b8021494Sopenharmony_ci} 143