xref: /third_party/vixl/test/aarch32/config/cond-rd-memop-rs-shift-amount-1to32-a32.json

// Copyright 2016, VIXL authors
// All rights reserved.
//
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// modification, are permitted provided that the following conditions are met:
//
//   * Redistributions of source code must retain the above copyright notice,
//     this list of conditions and the following disclaimer.
//   * Redistributions in binary form must reproduce the above copyright notice,
//     this list of conditions and the following disclaimer in the documentation
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//     used to endorse or promote products derived from this software without
//     specific prior written permission.
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{
  "mnemonics": [
    "Ldr",
    "Ldrb",
    "Str",
    "Strb"
  ],
  "description": {
    "operands": [
      {
        "name": "cond",
        "type": "Condition"
      },
      {
        "name": "rd",
        "type": "AllRegistersButPC"
      },
      {
        "name": "memop",
        "wrapper": "MemOperand",
        "operands": [
          {
            "name": "rn",
            "type": "AllRegistersButPC"
          },
          {
            "name": "sign",
            "type": "Sign"
          },
          {
            "name": "rm",
            "type": "AllRegistersButPC"
          },
          {
            "name": "shift",
            "type": "Shift1To32"
          },
          {
            "name": "amount",
            "type": "ShiftAmount1To32"
          },
          {
            "name": "addr_mode",
            "type": "AddressingMode"
          }
        ]
      }
    ],
    "inputs": [
      {
        "name": "apsr",
        "type": "NZCV"
      },
      {
        "name": "rd",
        "type": "Register"
      },
      {
        "name": "rm",
        "type": "RegisterOffsetLowerThan4096"
      },
      {
        "name": "memop",
        "type": "MemOperand"
      }
    ]
  },
  "test-files": [
    {
      "type": "assembler",
      "test-cases": [
        {
          "name": "Registers",
          "operands": [
            "cond", "rd", "rn", "rm"
          ],
          "operand-limit": 100
        },
        {
          "name": "MemOperandsOffset",
          "operands": [
            "rn", "sign", "rm", "shift", "amount", "addr_mode"
          ],
          "operand-filter": "addr_mode == 'Offset'",
          "operand-limit": 200
        },
        {
          "name": "MemOperandsWriteBack",
          "operands": [
            "rd", "rn", "sign", "rm", "shift", "amount", "addr_mode"
          ],
          "operand-filter": "addr_mode != 'Offset' and rd != rn",
          "operand-limit": 400
        }
      ]
    },
    {
      // TODO: The simulator tests do not support the case where `rd` ==
      // `rn`. See `data_types.MemOperand.Epilogue()` for details.
      "type": "simulator",
      "test-cases": [
        {
          "name": "Condition",
          "operands": [
            "cond", "rd", "rn", "rm"
          ],
          "operand-filter": "rd == 'r0' and rn == 'r1' and rm == 'r8'",
          "inputs": [
            "apsr"
          ]
        },
        {
          "name": "PositiveOffset",
          "operands": [
            "rd", "rn", "sign", "rm", "shift", "amount", "addr_mode"
          ],
          "operand-filter": "sign == 'plus' and addr_mode == 'Offset' and rd != rm and rd != rn and rn != rm",
          "operand-limit": 100,
          "inputs": [
            "memop", "rm"
          ],
          "input-limit": 10
        },
        {
          "name": "NegativeOffset",
          "operands": [
            "rd", "rn", "sign", "rm", "shift", "amount", "addr_mode"
          ],
          "operand-filter": "sign == 'minus' and addr_mode == 'Offset' and rd != rm and rd != rn and rn != rm",
          "operand-limit": 100,
          "inputs": [
            "memop", "rm"
          ],
          "input-limit": 10
        },
        {
          "name": "PositivePostIndex",
          "operands": [
            "rd", "rn", "sign", "rm", "shift", "amount", "addr_mode"
          ],
          "operand-filter": "sign == 'plus' and addr_mode == 'PostIndex' and rd != rm and rd != rn and rn != rm",
          "operand-limit": 100,
          "inputs": [
            "memop", "rm"
          ],
          "input-limit": 10
        },
        {
          "name": "NegativePostIndex",
          "operands": [
            "rd", "rn", "sign", "rm", "shift", "amount", "addr_mode"
          ],
          "operand-filter": "sign == 'minus' and addr_mode == 'PostIndex' and rd != rm and rd != rn and rn != rm",
          "operand-limit": 100,
          "inputs": [
            "memop", "rm"
          ],
          "input-limit": 10
        },
        {
          "name": "PositivePreIndex",
          "operands": [
            "rd", "rn", "sign", "rm", "shift", "amount", "addr_mode"
          ],
          "operand-filter": "sign == 'plus' and addr_mode == 'PreIndex' and rd != rm and rd != rn and rn != rm",
          "operand-limit": 100,
          "inputs": [
            "memop", "rm"
          ],
          "input-limit": 10
        },
        {
          "name": "NegativePreIndex",
          "operands": [
            "rd", "rn", "sign", "rm", "shift", "amount", "addr_mode"
          ],
          "operand-filter": "sign == 'minus' and addr_mode == 'PreIndex' and rd != rm and rd != rn and rn != rm",
          "operand-limit": 100,
          "inputs": [
            "memop", "rm"
          ],
          "input-limit": 10
        }
      ]
    }
  ]
}