1b8021494Sopenharmony_ci// Copyright 2016, VIXL authors
2b8021494Sopenharmony_ci// All rights reserved.
3b8021494Sopenharmony_ci//
4b8021494Sopenharmony_ci// Redistribution and use in source and binary forms, with or without
5b8021494Sopenharmony_ci// modification, are permitted provided that the following conditions are met:
6b8021494Sopenharmony_ci//
7b8021494Sopenharmony_ci//   * Redistributions of source code must retain the above copyright notice,
8b8021494Sopenharmony_ci//     this list of conditions and the following disclaimer.
9b8021494Sopenharmony_ci//   * Redistributions in binary form must reproduce the above copyright notice,
10b8021494Sopenharmony_ci//     this list of conditions and the following disclaimer in the documentation
11b8021494Sopenharmony_ci//     and/or other materials provided with the distribution.
12b8021494Sopenharmony_ci//   * Neither the name of ARM Limited nor the names of its contributors may be
13b8021494Sopenharmony_ci//     used to endorse or promote products derived from this software without
14b8021494Sopenharmony_ci//     specific prior written permission.
15b8021494Sopenharmony_ci//
16b8021494Sopenharmony_ci// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
17b8021494Sopenharmony_ci// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18b8021494Sopenharmony_ci// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19b8021494Sopenharmony_ci// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
20b8021494Sopenharmony_ci// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21b8021494Sopenharmony_ci// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22b8021494Sopenharmony_ci// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
23b8021494Sopenharmony_ci// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24b8021494Sopenharmony_ci// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25b8021494Sopenharmony_ci// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26b8021494Sopenharmony_ci
27b8021494Sopenharmony_ci{
28b8021494Sopenharmony_ci  "mnemonics": [
29b8021494Sopenharmony_ci    "Ldr",  // LDR{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_3>}] ; A1
30b8021494Sopenharmony_ci            // LDR{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm_3> ; A1
31b8021494Sopenharmony_ci            // LDR{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_3>}]! ; A1
32b8021494Sopenharmony_ci    "Ldrb", // LDRB{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_3>}] ; A1
33b8021494Sopenharmony_ci            // LDRB{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm_3> ; A1
34b8021494Sopenharmony_ci            // LDRB{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_3>}]! ; A1
35b8021494Sopenharmony_ci    "Str",  // STR{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_3>}] ; A1
36b8021494Sopenharmony_ci            // STR{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm_3> ; A1
37b8021494Sopenharmony_ci            // STR{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_3>}]! ; A1
38b8021494Sopenharmony_ci    "Strb"  // STRB{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_3>}] ; A1
39b8021494Sopenharmony_ci            // STRB{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm_3> ; A1
40b8021494Sopenharmony_ci            // STRB{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_3>}]! ; A1
41b8021494Sopenharmony_ci  ],
42b8021494Sopenharmony_ci  "description": {
43b8021494Sopenharmony_ci    "operands": [
44b8021494Sopenharmony_ci      {
45b8021494Sopenharmony_ci        "name": "cond",
46b8021494Sopenharmony_ci        "type": "Condition"
47b8021494Sopenharmony_ci      },
48b8021494Sopenharmony_ci      {
49b8021494Sopenharmony_ci        "name": "rd",
50b8021494Sopenharmony_ci        "type": "AllRegistersButPC"
51b8021494Sopenharmony_ci      },
52b8021494Sopenharmony_ci      {
53b8021494Sopenharmony_ci        "name": "memop",
54b8021494Sopenharmony_ci        "wrapper": "MemOperand",
55b8021494Sopenharmony_ci        "operands": [
56b8021494Sopenharmony_ci          {
57b8021494Sopenharmony_ci            "name": "rn",
58b8021494Sopenharmony_ci            "type": "AllRegistersButPC"
59b8021494Sopenharmony_ci          },
60b8021494Sopenharmony_ci          {
61b8021494Sopenharmony_ci            "name": "sign",
62b8021494Sopenharmony_ci            "type": "Sign"
63b8021494Sopenharmony_ci          },
64b8021494Sopenharmony_ci          {
65b8021494Sopenharmony_ci            "name": "offset",
66b8021494Sopenharmony_ci            "type": "OffsetLowerThan4096"
67b8021494Sopenharmony_ci          },
68b8021494Sopenharmony_ci          {
69b8021494Sopenharmony_ci            "name": "addr_mode",
70b8021494Sopenharmony_ci            "type": "AddressingMode"
71b8021494Sopenharmony_ci          }
72b8021494Sopenharmony_ci        ]
73b8021494Sopenharmony_ci      }
74b8021494Sopenharmony_ci    ],
75b8021494Sopenharmony_ci    "inputs": [
76b8021494Sopenharmony_ci      {
77b8021494Sopenharmony_ci        "name": "apsr",
78b8021494Sopenharmony_ci        "type": "NZCV"
79b8021494Sopenharmony_ci      },
80b8021494Sopenharmony_ci      {
81b8021494Sopenharmony_ci        "name": "rd",
82b8021494Sopenharmony_ci        "type": "Register"
83b8021494Sopenharmony_ci      },
84b8021494Sopenharmony_ci      {
85b8021494Sopenharmony_ci        "name": "memop",
86b8021494Sopenharmony_ci        "type": "MemOperand"
87b8021494Sopenharmony_ci      }
88b8021494Sopenharmony_ci    ]
89b8021494Sopenharmony_ci  },
90b8021494Sopenharmony_ci  "test-files": [
91b8021494Sopenharmony_ci    {
92b8021494Sopenharmony_ci      "type": "assembler",
93b8021494Sopenharmony_ci      "test-cases": [
94b8021494Sopenharmony_ci        {
95b8021494Sopenharmony_ci          "name": "Registers",
96b8021494Sopenharmony_ci          "operands": [
97b8021494Sopenharmony_ci            "cond", "rd", "rn"
98b8021494Sopenharmony_ci          ],
99b8021494Sopenharmony_ci          "operand-limit": 100
100b8021494Sopenharmony_ci        },
101b8021494Sopenharmony_ci        {
102b8021494Sopenharmony_ci          "name": "MemOperandsOffset",
103b8021494Sopenharmony_ci          "operands": [
104b8021494Sopenharmony_ci            "rn", "sign", "offset", "addr_mode"
105b8021494Sopenharmony_ci          ],
106b8021494Sopenharmony_ci          "operand-filter": "addr_mode == 'Offset'",
107b8021494Sopenharmony_ci          "operand-limit": 200
108b8021494Sopenharmony_ci        },
109b8021494Sopenharmony_ci        {
110b8021494Sopenharmony_ci          "name": "MemOperandsWriteBack",
111b8021494Sopenharmony_ci          "operands": [
112b8021494Sopenharmony_ci            "rd", "rn", "sign", "offset", "addr_mode"
113b8021494Sopenharmony_ci          ],
114b8021494Sopenharmony_ci          "operand-filter": "addr_mode != 'Offset' and rd != rn",
115b8021494Sopenharmony_ci          "operand-limit": 400
116b8021494Sopenharmony_ci        }
117b8021494Sopenharmony_ci      ]
118b8021494Sopenharmony_ci    },
119b8021494Sopenharmony_ci    {
120b8021494Sopenharmony_ci      // TODO: The simulator tests do not support the case where `rd` ==
121b8021494Sopenharmony_ci      // `rn`. See `data_types.MemOperand.Epilogue()` for details.
122b8021494Sopenharmony_ci      "type": "simulator",
123b8021494Sopenharmony_ci      "test-cases": [
124b8021494Sopenharmony_ci        {
125b8021494Sopenharmony_ci          "name": "Condition",
126b8021494Sopenharmony_ci          "operands": [
127b8021494Sopenharmony_ci            "cond", "rd", "rn"
128b8021494Sopenharmony_ci          ],
129b8021494Sopenharmony_ci          "operand-filter": "rd == 'r0' and rn == 'r1'",
130b8021494Sopenharmony_ci          "inputs": [
131b8021494Sopenharmony_ci            "apsr"
132b8021494Sopenharmony_ci          ]
133b8021494Sopenharmony_ci        },
134b8021494Sopenharmony_ci        {
135b8021494Sopenharmony_ci          "name": "PositiveOffset",
136b8021494Sopenharmony_ci          "operands": [
137b8021494Sopenharmony_ci            "rd", "rn", "sign", "offset", "addr_mode"
138b8021494Sopenharmony_ci          ],
139b8021494Sopenharmony_ci          "operand-filter": "sign == 'plus' and addr_mode == 'Offset' and rd != rn",
140b8021494Sopenharmony_ci          "operand-limit": 100,
141b8021494Sopenharmony_ci          "inputs": [
142b8021494Sopenharmony_ci            "rd", "memop"
143b8021494Sopenharmony_ci          ],
144b8021494Sopenharmony_ci          "input-limit": 10
145b8021494Sopenharmony_ci        },
146b8021494Sopenharmony_ci        {
147b8021494Sopenharmony_ci          "name": "NegativeOffset",
148b8021494Sopenharmony_ci          "operands": [
149b8021494Sopenharmony_ci            "rd", "rn", "sign", "offset", "addr_mode"
150b8021494Sopenharmony_ci          ],
151b8021494Sopenharmony_ci          "operand-filter": "sign == 'minus' and addr_mode == 'Offset' and rd != rn",
152b8021494Sopenharmony_ci          "operand-limit": 100,
153b8021494Sopenharmony_ci          "inputs": [
154b8021494Sopenharmony_ci            "rd", "memop"
155b8021494Sopenharmony_ci          ],
156b8021494Sopenharmony_ci          "input-limit": 10
157b8021494Sopenharmony_ci        },
158b8021494Sopenharmony_ci        {
159b8021494Sopenharmony_ci          "name": "PositivePostIndex",
160b8021494Sopenharmony_ci          "operands": [
161b8021494Sopenharmony_ci            "rd", "rn", "sign", "offset", "addr_mode"
162b8021494Sopenharmony_ci          ],
163b8021494Sopenharmony_ci          "operand-filter": "sign == 'plus' and addr_mode == 'PostIndex' and rd != rn",
164b8021494Sopenharmony_ci          "operand-limit": 100,
165b8021494Sopenharmony_ci          "inputs": [
166b8021494Sopenharmony_ci            "rd", "memop"
167b8021494Sopenharmony_ci          ],
168b8021494Sopenharmony_ci          "input-limit": 10
169b8021494Sopenharmony_ci        },
170b8021494Sopenharmony_ci        {
171b8021494Sopenharmony_ci          "name": "NegativePostIndex",
172b8021494Sopenharmony_ci          "operands": [
173b8021494Sopenharmony_ci            "rd", "rn", "sign", "offset", "addr_mode"
174b8021494Sopenharmony_ci          ],
175b8021494Sopenharmony_ci          "operand-filter": "sign == 'minus' and addr_mode == 'PostIndex' and rd != rn",
176b8021494Sopenharmony_ci          "operand-limit": 100,
177b8021494Sopenharmony_ci          "inputs": [
178b8021494Sopenharmony_ci            "rd", "memop"
179b8021494Sopenharmony_ci          ],
180b8021494Sopenharmony_ci          "input-limit": 10
181b8021494Sopenharmony_ci        },
182b8021494Sopenharmony_ci        {
183b8021494Sopenharmony_ci          "name": "PositivePreIndex",
184b8021494Sopenharmony_ci          "operands": [
185b8021494Sopenharmony_ci            "rd", "rn", "sign", "offset", "addr_mode"
186b8021494Sopenharmony_ci          ],
187b8021494Sopenharmony_ci          "operand-filter": "sign == 'plus' and addr_mode == 'PreIndex' and rd != rn",
188b8021494Sopenharmony_ci          "operand-limit": 100,
189b8021494Sopenharmony_ci          "inputs": [
190b8021494Sopenharmony_ci            "rd", "memop"
191b8021494Sopenharmony_ci          ],
192b8021494Sopenharmony_ci          "input-limit": 10
193b8021494Sopenharmony_ci        },
194b8021494Sopenharmony_ci        {
195b8021494Sopenharmony_ci          "name": "NegativePreIndex",
196b8021494Sopenharmony_ci          "operands": [
197b8021494Sopenharmony_ci            "rd", "rn", "sign", "offset", "addr_mode"
198b8021494Sopenharmony_ci          ],
199b8021494Sopenharmony_ci          "operand-filter": "sign == 'minus' and addr_mode == 'PreIndex' and rd != rn",
200b8021494Sopenharmony_ci          "operand-limit": 100,
201b8021494Sopenharmony_ci          "inputs": [
202b8021494Sopenharmony_ci            "rd", "memop"
203b8021494Sopenharmony_ci          ],
204b8021494Sopenharmony_ci          "input-limit": 10
205b8021494Sopenharmony_ci        }
206b8021494Sopenharmony_ci      ]
207b8021494Sopenharmony_ci    }
208b8021494Sopenharmony_ci  ]
209b8021494Sopenharmony_ci}
210