1// Copyright 2015, VIXL authors 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are met: 6// 7// * Redistributions of source code must retain the above copyright notice, 8// this list of conditions and the following disclaimer. 9// * Redistributions in binary form must reproduce the above copyright notice, 10// this list of conditions and the following disclaimer in the documentation 11// and/or other materials provided with the distribution. 12// * Neither the name of ARM Limited nor the names of its contributors may be 13// used to endorse or promote products derived from this software without 14// specific prior written permission. 15// 16// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27#ifndef VIXL_AARCH64_CONSTANTS_AARCH64_H_ 28#define VIXL_AARCH64_CONSTANTS_AARCH64_H_ 29 30#include "../globals-vixl.h" 31 32namespace vixl { 33namespace aarch64 { 34 35const unsigned kNumberOfRegisters = 32; 36const unsigned kNumberOfVRegisters = 32; 37const unsigned kNumberOfZRegisters = kNumberOfVRegisters; 38const unsigned kNumberOfPRegisters = 16; 39// Callee saved registers are x21-x30(lr). 40const int kNumberOfCalleeSavedRegisters = 10; 41const int kFirstCalleeSavedRegisterIndex = 21; 42// Callee saved FP registers are d8-d15. Note that the high parts of v8-v15 are 43// still caller-saved. 44const int kNumberOfCalleeSavedFPRegisters = 8; 45const int kFirstCalleeSavedFPRegisterIndex = 8; 46// All predicated instructions accept at least p0-p7 as the governing predicate. 47const unsigned kNumberOfGoverningPRegisters = 8; 48 49// clang-format off 50#define AARCH64_P_REGISTER_CODE_LIST(R) \ 51 R(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) \ 52 R(8) R(9) R(10) R(11) R(12) R(13) R(14) R(15) 53 54#define AARCH64_REGISTER_CODE_LIST(R) \ 55 R(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) \ 56 R(8) R(9) R(10) R(11) R(12) R(13) R(14) R(15) \ 57 R(16) R(17) R(18) R(19) R(20) R(21) R(22) R(23) \ 58 R(24) R(25) R(26) R(27) R(28) R(29) R(30) R(31) 59 60// SVE loads and stores use "w" instead of "s" for word-sized accesses, so the 61// mapping from the load/store variant to constants like k*RegSize is irregular. 62#define VIXL_SVE_LOAD_STORE_VARIANT_LIST(V) \ 63 V(b, B) \ 64 V(h, H) \ 65 V(w, S) \ 66 V(d, D) 67 68// Sign-extending loads don't have double-word variants. 69#define VIXL_SVE_LOAD_STORE_SIGNED_VARIANT_LIST(V) \ 70 V(b, B) \ 71 V(h, H) \ 72 V(w, S) 73 74#define INSTRUCTION_FIELDS_LIST(V_) \ 75/* Register fields */ \ 76V_(Rd, 4, 0, ExtractBits) /* Destination register. */ \ 77V_(Rn, 9, 5, ExtractBits) /* First source register. */ \ 78V_(Rm, 20, 16, ExtractBits) /* Second source register. */ \ 79V_(RmLow16, 19, 16, ExtractBits) /* Second source register (code 0-15). */ \ 80V_(Ra, 14, 10, ExtractBits) /* Third source register. */ \ 81V_(Rt, 4, 0, ExtractBits) /* Load/store register. */ \ 82V_(Rt2, 14, 10, ExtractBits) /* Load/store second register. */ \ 83V_(Rs, 20, 16, ExtractBits) /* Exclusive access status. */ \ 84V_(Pt, 3, 0, ExtractBits) /* Load/store register (p0-p7). */ \ 85V_(Pd, 3, 0, ExtractBits) /* SVE destination predicate register. */ \ 86V_(Pn, 8, 5, ExtractBits) /* SVE first source predicate register. */ \ 87V_(Pm, 19, 16, ExtractBits) /* SVE second source predicate register.*/ \ 88V_(PgLow8, 12, 10, ExtractBits) /* Governing predicate (p0-p7). */ \ 89 \ 90/* Common bits */ \ 91V_(SixtyFourBits, 31, 31, ExtractBits) \ 92V_(FlagsUpdate, 29, 29, ExtractBits) \ 93 \ 94/* PC relative addressing */ \ 95V_(ImmPCRelHi, 23, 5, ExtractSignedBits) \ 96V_(ImmPCRelLo, 30, 29, ExtractBits) \ 97 \ 98/* Add/subtract/logical shift register */ \ 99V_(ShiftDP, 23, 22, ExtractBits) \ 100V_(ImmDPShift, 15, 10, ExtractBits) \ 101 \ 102/* Add/subtract immediate */ \ 103V_(ImmAddSub, 21, 10, ExtractBits) \ 104V_(ImmAddSubShift, 22, 22, ExtractBits) \ 105 \ 106/* Add/substract extend */ \ 107V_(ImmExtendShift, 12, 10, ExtractBits) \ 108V_(ExtendMode, 15, 13, ExtractBits) \ 109 \ 110/* Move wide */ \ 111V_(ImmMoveWide, 20, 5, ExtractBits) \ 112V_(ShiftMoveWide, 22, 21, ExtractBits) \ 113 \ 114/* Logical immediate, bitfield and extract */ \ 115V_(BitN, 22, 22, ExtractBits) \ 116V_(ImmRotate, 21, 16, ExtractBits) \ 117V_(ImmSetBits, 15, 10, ExtractBits) \ 118V_(ImmR, 21, 16, ExtractBits) \ 119V_(ImmS, 15, 10, ExtractBits) \ 120 \ 121/* Test and branch immediate */ \ 122V_(ImmTestBranch, 18, 5, ExtractSignedBits) \ 123V_(ImmTestBranchBit40, 23, 19, ExtractBits) \ 124V_(ImmTestBranchBit5, 31, 31, ExtractBits) \ 125 \ 126/* Conditionals */ \ 127V_(Condition, 15, 12, ExtractBits) \ 128V_(ConditionBranch, 3, 0, ExtractBits) \ 129V_(Nzcv, 3, 0, ExtractBits) \ 130V_(ImmCondCmp, 20, 16, ExtractBits) \ 131V_(ImmCondBranch, 23, 5, ExtractSignedBits) \ 132 \ 133/* Floating point */ \ 134V_(FPType, 23, 22, ExtractBits) \ 135V_(ImmFP, 20, 13, ExtractBits) \ 136V_(FPScale, 15, 10, ExtractBits) \ 137 \ 138/* Load Store */ \ 139V_(ImmLS, 20, 12, ExtractSignedBits) \ 140V_(ImmLSUnsigned, 21, 10, ExtractBits) \ 141V_(ImmLSPair, 21, 15, ExtractSignedBits) \ 142V_(ImmShiftLS, 12, 12, ExtractBits) \ 143V_(LSOpc, 23, 22, ExtractBits) \ 144V_(LSVector, 26, 26, ExtractBits) \ 145V_(LSSize, 31, 30, ExtractBits) \ 146V_(ImmPrefetchOperation, 4, 0, ExtractBits) \ 147V_(PrefetchHint, 4, 3, ExtractBits) \ 148V_(PrefetchTarget, 2, 1, ExtractBits) \ 149V_(PrefetchStream, 0, 0, ExtractBits) \ 150V_(ImmLSPACHi, 22, 22, ExtractSignedBits) \ 151V_(ImmLSPACLo, 20, 12, ExtractBits) \ 152 \ 153/* Other immediates */ \ 154V_(ImmUncondBranch, 25, 0, ExtractSignedBits) \ 155V_(ImmCmpBranch, 23, 5, ExtractSignedBits) \ 156V_(ImmLLiteral, 23, 5, ExtractSignedBits) \ 157V_(ImmException, 20, 5, ExtractBits) \ 158V_(ImmHint, 11, 5, ExtractBits) \ 159V_(ImmBarrierDomain, 11, 10, ExtractBits) \ 160V_(ImmBarrierType, 9, 8, ExtractBits) \ 161V_(ImmUdf, 15, 0, ExtractBits) \ 162 \ 163/* System (MRS, MSR, SYS) */ \ 164V_(ImmSystemRegister, 20, 5, ExtractBits) \ 165V_(SysO0, 19, 19, ExtractBits) \ 166V_(SysOp, 18, 5, ExtractBits) \ 167V_(SysOp0, 20, 19, ExtractBits) \ 168V_(SysOp1, 18, 16, ExtractBits) \ 169V_(SysOp2, 7, 5, ExtractBits) \ 170V_(CRn, 15, 12, ExtractBits) \ 171V_(CRm, 11, 8, ExtractBits) \ 172V_(ImmRMIFRotation, 20, 15, ExtractBits) \ 173 \ 174/* Load-/store-exclusive */ \ 175V_(LdStXLoad, 22, 22, ExtractBits) \ 176V_(LdStXNotExclusive, 23, 23, ExtractBits) \ 177V_(LdStXAcquireRelease, 15, 15, ExtractBits) \ 178V_(LdStXSizeLog2, 31, 30, ExtractBits) \ 179V_(LdStXPair, 21, 21, ExtractBits) \ 180 \ 181/* NEON generic fields */ \ 182V_(NEONQ, 30, 30, ExtractBits) \ 183V_(NEONSize, 23, 22, ExtractBits) \ 184V_(NEONLSSize, 11, 10, ExtractBits) \ 185V_(NEONS, 12, 12, ExtractBits) \ 186V_(NEONL, 21, 21, ExtractBits) \ 187V_(NEONM, 20, 20, ExtractBits) \ 188V_(NEONH, 11, 11, ExtractBits) \ 189V_(ImmNEONExt, 14, 11, ExtractBits) \ 190V_(ImmNEON5, 20, 16, ExtractBits) \ 191V_(ImmNEON4, 14, 11, ExtractBits) \ 192 \ 193/* NEON extra fields */ \ 194V_(ImmRotFcadd, 12, 12, ExtractBits) \ 195V_(ImmRotFcmlaVec, 12, 11, ExtractBits) \ 196V_(ImmRotFcmlaSca, 14, 13, ExtractBits) \ 197 \ 198/* NEON Modified Immediate fields */ \ 199V_(ImmNEONabc, 18, 16, ExtractBits) \ 200V_(ImmNEONdefgh, 9, 5, ExtractBits) \ 201V_(NEONModImmOp, 29, 29, ExtractBits) \ 202V_(NEONCmode, 15, 12, ExtractBits) \ 203 \ 204/* NEON Shift Immediate fields */ \ 205V_(ImmNEONImmhImmb, 22, 16, ExtractBits) \ 206V_(ImmNEONImmh, 22, 19, ExtractBits) \ 207V_(ImmNEONImmb, 18, 16, ExtractBits) \ 208 \ 209/* SVE generic fields */ \ 210V_(SVESize, 23, 22, ExtractBits) \ 211V_(ImmSVEVLScale, 10, 5, ExtractSignedBits) \ 212V_(ImmSVEIntWideSigned, 12, 5, ExtractSignedBits) \ 213V_(ImmSVEIntWideUnsigned, 12, 5, ExtractBits) \ 214V_(ImmSVEPredicateConstraint, 9, 5, ExtractBits) \ 215 \ 216/* SVE Bitwise Immediate bitfield */ \ 217V_(SVEBitN, 17, 17, ExtractBits) \ 218V_(SVEImmRotate, 16, 11, ExtractBits) \ 219V_(SVEImmSetBits, 10, 5, ExtractBits) \ 220 \ 221V_(SVEImmPrefetchOperation, 3, 0, ExtractBits) \ 222V_(SVEPrefetchHint, 3, 3, ExtractBits) 223 224// clang-format on 225 226#define SYSTEM_REGISTER_FIELDS_LIST(V_, M_) \ 227 /* NZCV */ \ 228 V_(Flags, 31, 28, ExtractBits) \ 229 V_(N, 31, 31, ExtractBits) \ 230 V_(Z, 30, 30, ExtractBits) \ 231 V_(C, 29, 29, ExtractBits) \ 232 V_(V, 28, 28, ExtractBits) \ 233 M_(NZCV, Flags_mask) \ 234 /* FPCR */ \ 235 V_(AHP, 26, 26, ExtractBits) \ 236 V_(DN, 25, 25, ExtractBits) \ 237 V_(FZ, 24, 24, ExtractBits) \ 238 V_(RMode, 23, 22, ExtractBits) \ 239 M_(FPCR, AHP_mask | DN_mask | FZ_mask | RMode_mask) 240 241// Fields offsets. 242#define DECLARE_FIELDS_OFFSETS(Name, HighBit, LowBit, X) \ 243 const int Name##_offset = LowBit; \ 244 const int Name##_width = HighBit - LowBit + 1; \ 245 const uint32_t Name##_mask = ((1 << Name##_width) - 1) << LowBit; 246#define NOTHING(A, B) 247INSTRUCTION_FIELDS_LIST(DECLARE_FIELDS_OFFSETS) 248SYSTEM_REGISTER_FIELDS_LIST(DECLARE_FIELDS_OFFSETS, NOTHING) 249#undef NOTHING 250#undef DECLARE_FIELDS_BITS 251 252// ImmPCRel is a compound field (not present in INSTRUCTION_FIELDS_LIST), formed 253// from ImmPCRelLo and ImmPCRelHi. 254const int ImmPCRel_mask = ImmPCRelLo_mask | ImmPCRelHi_mask; 255 256// Disable `clang-format` for the `enum`s below. We care about the manual 257// formatting that `clang-format` would destroy. 258// clang-format off 259 260// Condition codes. 261enum Condition { 262 eq = 0, // Z set Equal. 263 ne = 1, // Z clear Not equal. 264 cs = 2, // C set Carry set. 265 cc = 3, // C clear Carry clear. 266 mi = 4, // N set Negative. 267 pl = 5, // N clear Positive or zero. 268 vs = 6, // V set Overflow. 269 vc = 7, // V clear No overflow. 270 hi = 8, // C set, Z clear Unsigned higher. 271 ls = 9, // C clear or Z set Unsigned lower or same. 272 ge = 10, // N == V Greater or equal. 273 lt = 11, // N != V Less than. 274 gt = 12, // Z clear, N == V Greater than. 275 le = 13, // Z set or N != V Less then or equal 276 al = 14, // Always. 277 nv = 15, // Behaves as always/al. 278 279 // Aliases. 280 hs = cs, // C set Unsigned higher or same. 281 lo = cc, // C clear Unsigned lower. 282 283 // Floating-point additional condition code. 284 uo, // Unordered comparison. 285 286 // SVE predicate condition aliases. 287 sve_none = eq, // No active elements were true. 288 sve_any = ne, // An active element was true. 289 sve_nlast = cs, // The last element was not true. 290 sve_last = cc, // The last element was true. 291 sve_first = mi, // The first element was true. 292 sve_nfrst = pl, // The first element was not true. 293 sve_pmore = hi, // An active element was true but not the last element. 294 sve_plast = ls, // The last active element was true or no active elements were true. 295 sve_tcont = ge, // CTERM termination condition not deleted. 296 sve_tstop = lt // CTERM termination condition deleted. 297}; 298 299inline Condition InvertCondition(Condition cond) { 300 // Conditions al and nv behave identically, as "always true". They can't be 301 // inverted, because there is no "always false" condition. 302 VIXL_ASSERT((cond != al) && (cond != nv)); 303 return static_cast<Condition>(cond ^ 1); 304} 305 306enum FPTrapFlags { 307 EnableTrap = 1, 308 DisableTrap = 0 309}; 310 311enum FlagsUpdate { 312 SetFlags = 1, 313 LeaveFlags = 0 314}; 315 316enum StatusFlags { 317 NoFlag = 0, 318 319 // Derive the flag combinations from the system register bit descriptions. 320 NFlag = N_mask, 321 ZFlag = Z_mask, 322 CFlag = C_mask, 323 VFlag = V_mask, 324 NZFlag = NFlag | ZFlag, 325 NCFlag = NFlag | CFlag, 326 NVFlag = NFlag | VFlag, 327 ZCFlag = ZFlag | CFlag, 328 ZVFlag = ZFlag | VFlag, 329 CVFlag = CFlag | VFlag, 330 NZCFlag = NFlag | ZFlag | CFlag, 331 NZVFlag = NFlag | ZFlag | VFlag, 332 NCVFlag = NFlag | CFlag | VFlag, 333 ZCVFlag = ZFlag | CFlag | VFlag, 334 NZCVFlag = NFlag | ZFlag | CFlag | VFlag, 335 336 // Floating-point comparison results. 337 FPEqualFlag = ZCFlag, 338 FPLessThanFlag = NFlag, 339 FPGreaterThanFlag = CFlag, 340 FPUnorderedFlag = CVFlag, 341 342 // SVE condition flags. 343 SVEFirstFlag = NFlag, 344 SVENoneFlag = ZFlag, 345 SVENotLastFlag = CFlag 346}; 347 348enum Shift { 349 NO_SHIFT = -1, 350 LSL = 0x0, 351 LSR = 0x1, 352 ASR = 0x2, 353 ROR = 0x3, 354 MSL = 0x4 355}; 356 357enum Extend { 358 NO_EXTEND = -1, 359 UXTB = 0, 360 UXTH = 1, 361 UXTW = 2, 362 UXTX = 3, 363 SXTB = 4, 364 SXTH = 5, 365 SXTW = 6, 366 SXTX = 7 367}; 368 369enum SVEOffsetModifier { 370 NO_SVE_OFFSET_MODIFIER, 371 // Multiply (each element of) the offset by either the vector or predicate 372 // length, according to the context. 373 SVE_MUL_VL, 374 // Shift or extend modifiers (as in `Shift` or `Extend`). 375 SVE_LSL, 376 SVE_UXTW, 377 SVE_SXTW 378}; 379 380enum SystemHint { 381 NOP = 0, 382 YIELD = 1, 383 WFE = 2, 384 WFI = 3, 385 SEV = 4, 386 SEVL = 5, 387 ESB = 16, 388 CSDB = 20, 389 BTI = 32, 390 BTI_c = 34, 391 BTI_j = 36, 392 BTI_jc = 38 393}; 394 395enum BranchTargetIdentifier { 396 EmitBTI_none = NOP, 397 EmitBTI = BTI, 398 EmitBTI_c = BTI_c, 399 EmitBTI_j = BTI_j, 400 EmitBTI_jc = BTI_jc, 401 402 // These correspond to the values of the CRm:op2 fields in the equivalent HINT 403 // instruction. 404 EmitPACIASP = 25, 405 EmitPACIBSP = 27 406}; 407 408enum BarrierDomain { 409 OuterShareable = 0, 410 NonShareable = 1, 411 InnerShareable = 2, 412 FullSystem = 3 413}; 414 415enum BarrierType { 416 BarrierOther = 0, 417 BarrierReads = 1, 418 BarrierWrites = 2, 419 BarrierAll = 3 420}; 421 422enum PrefetchOperation { 423 PLDL1KEEP = 0x00, 424 PLDL1STRM = 0x01, 425 PLDL2KEEP = 0x02, 426 PLDL2STRM = 0x03, 427 PLDL3KEEP = 0x04, 428 PLDL3STRM = 0x05, 429 430 PrfUnallocated06 = 0x06, 431 PrfUnallocated07 = 0x07, 432 433 PLIL1KEEP = 0x08, 434 PLIL1STRM = 0x09, 435 PLIL2KEEP = 0x0a, 436 PLIL2STRM = 0x0b, 437 PLIL3KEEP = 0x0c, 438 PLIL3STRM = 0x0d, 439 440 PrfUnallocated0e = 0x0e, 441 PrfUnallocated0f = 0x0f, 442 443 PSTL1KEEP = 0x10, 444 PSTL1STRM = 0x11, 445 PSTL2KEEP = 0x12, 446 PSTL2STRM = 0x13, 447 PSTL3KEEP = 0x14, 448 PSTL3STRM = 0x15, 449 450 PrfUnallocated16 = 0x16, 451 PrfUnallocated17 = 0x17, 452 PrfUnallocated18 = 0x18, 453 PrfUnallocated19 = 0x19, 454 PrfUnallocated1a = 0x1a, 455 PrfUnallocated1b = 0x1b, 456 PrfUnallocated1c = 0x1c, 457 PrfUnallocated1d = 0x1d, 458 PrfUnallocated1e = 0x1e, 459 PrfUnallocated1f = 0x1f, 460}; 461 462constexpr bool IsNamedPrefetchOperation(int op) { 463 return ((op >= PLDL1KEEP) && (op <= PLDL3STRM)) || 464 ((op >= PLIL1KEEP) && (op <= PLIL3STRM)) || 465 ((op >= PSTL1KEEP) && (op <= PSTL3STRM)); 466} 467 468enum BType { 469 // Set when executing any instruction on a guarded page, except those cases 470 // listed below. 471 DefaultBType = 0, 472 473 // Set when an indirect branch is taken from an unguarded page to a guarded 474 // page, or from a guarded page to ip0 or ip1 (x16 or x17), eg "br ip0". 475 BranchFromUnguardedOrToIP = 1, 476 477 // Set when an indirect branch and link (call) is taken, eg. "blr x0". 478 BranchAndLink = 2, 479 480 // Set when an indirect branch is taken from a guarded page to a register 481 // that is not ip0 or ip1 (x16 or x17), eg, "br x0". 482 BranchFromGuardedNotToIP = 3 483}; 484 485template<int op0, int op1, int crn, int crm, int op2> 486class SystemRegisterEncoder { 487 public: 488 static const uint32_t value = 489 ((op0 << SysO0_offset) | 490 (op1 << SysOp1_offset) | 491 (crn << CRn_offset) | 492 (crm << CRm_offset) | 493 (op2 << SysOp2_offset)) >> ImmSystemRegister_offset; 494}; 495 496// System/special register names. 497// This information is not encoded as one field but as the concatenation of 498// multiple fields (Op0, Op1, Crn, Crm, Op2). 499enum SystemRegister { 500 NZCV = SystemRegisterEncoder<3, 3, 4, 2, 0>::value, 501 FPCR = SystemRegisterEncoder<3, 3, 4, 4, 0>::value, 502 RNDR = SystemRegisterEncoder<3, 3, 2, 4, 0>::value, // Random number. 503 RNDRRS = SystemRegisterEncoder<3, 3, 2, 4, 1>::value // Reseeded random number. 504}; 505 506template<int op1, int crn, int crm, int op2> 507class CacheOpEncoder { 508 public: 509 static const uint32_t value = 510 ((op1 << SysOp1_offset) | 511 (crn << CRn_offset) | 512 (crm << CRm_offset) | 513 (op2 << SysOp2_offset)) >> SysOp_offset; 514}; 515 516enum InstructionCacheOp { 517 IVAU = CacheOpEncoder<3, 7, 5, 1>::value 518}; 519 520enum DataCacheOp { 521 CVAC = CacheOpEncoder<3, 7, 10, 1>::value, 522 CVAU = CacheOpEncoder<3, 7, 11, 1>::value, 523 CVAP = CacheOpEncoder<3, 7, 12, 1>::value, 524 CVADP = CacheOpEncoder<3, 7, 13, 1>::value, 525 CIVAC = CacheOpEncoder<3, 7, 14, 1>::value, 526 ZVA = CacheOpEncoder<3, 7, 4, 1>::value, 527 GVA = CacheOpEncoder<3, 7, 4, 3>::value, 528 GZVA = CacheOpEncoder<3, 7, 4, 4>::value, 529 CGVAC = CacheOpEncoder<3, 7, 10, 3>::value, 530 CGDVAC = CacheOpEncoder<3, 7, 10, 5>::value, 531 CGVAP = CacheOpEncoder<3, 7, 12, 3>::value, 532 CGDVAP = CacheOpEncoder<3, 7, 12, 5>::value, 533 CIGVAC = CacheOpEncoder<3, 7, 14, 3>::value, 534 CIGDVAC = CacheOpEncoder<3, 7, 14, 5>::value 535}; 536 537// Some SVE instructions support a predicate constraint pattern. This is 538// interpreted as a VL-dependent value, and is typically used to initialise 539// predicates, or to otherwise limit the number of processed elements. 540enum SVEPredicateConstraint { 541 // Select 2^N elements, for the largest possible N. 542 SVE_POW2 = 0x0, 543 // Each VL<N> selects exactly N elements if possible, or zero if N is greater 544 // than the number of elements. Note that the encoding values for VL<N> are 545 // not linearly related to N. 546 SVE_VL1 = 0x1, 547 SVE_VL2 = 0x2, 548 SVE_VL3 = 0x3, 549 SVE_VL4 = 0x4, 550 SVE_VL5 = 0x5, 551 SVE_VL6 = 0x6, 552 SVE_VL7 = 0x7, 553 SVE_VL8 = 0x8, 554 SVE_VL16 = 0x9, 555 SVE_VL32 = 0xa, 556 SVE_VL64 = 0xb, 557 SVE_VL128 = 0xc, 558 SVE_VL256 = 0xd, 559 // Each MUL<N> selects the largest multiple of N elements that the vector 560 // length supports. Note that for D-sized lanes, this can be zero. 561 SVE_MUL4 = 0x1d, 562 SVE_MUL3 = 0x1e, 563 // Select all elements. 564 SVE_ALL = 0x1f 565}; 566 567// Instruction enumerations. 568// 569// These are the masks that define a class of instructions, and the list of 570// instructions within each class. Each enumeration has a Fixed, FMask and 571// Mask value. 572// 573// Fixed: The fixed bits in this instruction class. 574// FMask: The mask used to extract the fixed bits in the class. 575// Mask: The mask used to identify the instructions within a class. 576// 577// The enumerations can be used like this: 578// 579// VIXL_ASSERT(instr->Mask(PCRelAddressingFMask) == PCRelAddressingFixed); 580// switch(instr->Mask(PCRelAddressingMask)) { 581// case ADR: Format("adr 'Xd, 'AddrPCRelByte"); break; 582// case ADRP: Format("adrp 'Xd, 'AddrPCRelPage"); break; 583// default: printf("Unknown instruction\n"); 584// } 585 586 587// Generic fields. 588enum GenericInstrField { 589 SixtyFourBits = 0x80000000, 590 ThirtyTwoBits = 0x00000000, 591 592 FPTypeMask = 0x00C00000, 593 FP16 = 0x00C00000, 594 FP32 = 0x00000000, 595 FP64 = 0x00400000 596}; 597 598enum NEONFormatField { 599 NEONFormatFieldMask = 0x40C00000, 600 NEON_Q = 0x40000000, 601 NEON_8B = 0x00000000, 602 NEON_16B = NEON_8B | NEON_Q, 603 NEON_4H = 0x00400000, 604 NEON_8H = NEON_4H | NEON_Q, 605 NEON_2S = 0x00800000, 606 NEON_4S = NEON_2S | NEON_Q, 607 NEON_1D = 0x00C00000, 608 NEON_2D = 0x00C00000 | NEON_Q 609}; 610 611enum NEONFPFormatField { 612 NEONFPFormatFieldMask = 0x40400000, 613 NEON_FP_4H = FP16, 614 NEON_FP_2S = FP32, 615 NEON_FP_8H = FP16 | NEON_Q, 616 NEON_FP_4S = FP32 | NEON_Q, 617 NEON_FP_2D = FP64 | NEON_Q 618}; 619 620enum NEONLSFormatField { 621 NEONLSFormatFieldMask = 0x40000C00, 622 LS_NEON_8B = 0x00000000, 623 LS_NEON_16B = LS_NEON_8B | NEON_Q, 624 LS_NEON_4H = 0x00000400, 625 LS_NEON_8H = LS_NEON_4H | NEON_Q, 626 LS_NEON_2S = 0x00000800, 627 LS_NEON_4S = LS_NEON_2S | NEON_Q, 628 LS_NEON_1D = 0x00000C00, 629 LS_NEON_2D = LS_NEON_1D | NEON_Q 630}; 631 632enum NEONScalarFormatField { 633 NEONScalarFormatFieldMask = 0x00C00000, 634 NEONScalar = 0x10000000, 635 NEON_B = 0x00000000, 636 NEON_H = 0x00400000, 637 NEON_S = 0x00800000, 638 NEON_D = 0x00C00000 639}; 640 641enum SVESizeField { 642 SVESizeFieldMask = 0x00C00000, 643 SVE_B = 0x00000000, 644 SVE_H = 0x00400000, 645 SVE_S = 0x00800000, 646 SVE_D = 0x00C00000 647}; 648 649// PC relative addressing. 650enum PCRelAddressingOp { 651 PCRelAddressingFixed = 0x10000000, 652 PCRelAddressingFMask = 0x1F000000, 653 PCRelAddressingMask = 0x9F000000, 654 ADR = PCRelAddressingFixed | 0x00000000, 655 ADRP = PCRelAddressingFixed | 0x80000000 656}; 657 658// Add/sub (immediate, shifted and extended.) 659const int kSFOffset = 31; 660enum AddSubOp { 661 AddSubOpMask = 0x60000000, 662 AddSubSetFlagsBit = 0x20000000, 663 ADD = 0x00000000, 664 ADDS = ADD | AddSubSetFlagsBit, 665 SUB = 0x40000000, 666 SUBS = SUB | AddSubSetFlagsBit 667}; 668 669#define ADD_SUB_OP_LIST(V) \ 670 V(ADD), \ 671 V(ADDS), \ 672 V(SUB), \ 673 V(SUBS) 674 675enum AddSubImmediateOp { 676 AddSubImmediateFixed = 0x11000000, 677 AddSubImmediateFMask = 0x1F800000, 678 AddSubImmediateMask = 0xFF800000, 679 #define ADD_SUB_IMMEDIATE(A) \ 680 A##_w_imm = AddSubImmediateFixed | A, \ 681 A##_x_imm = AddSubImmediateFixed | A | SixtyFourBits 682 ADD_SUB_OP_LIST(ADD_SUB_IMMEDIATE) 683 #undef ADD_SUB_IMMEDIATE 684}; 685 686enum AddSubShiftedOp { 687 AddSubShiftedFixed = 0x0B000000, 688 AddSubShiftedFMask = 0x1F200000, 689 AddSubShiftedMask = 0xFF200000, 690 #define ADD_SUB_SHIFTED(A) \ 691 A##_w_shift = AddSubShiftedFixed | A, \ 692 A##_x_shift = AddSubShiftedFixed | A | SixtyFourBits 693 ADD_SUB_OP_LIST(ADD_SUB_SHIFTED) 694 #undef ADD_SUB_SHIFTED 695}; 696 697enum AddSubExtendedOp { 698 AddSubExtendedFixed = 0x0B200000, 699 AddSubExtendedFMask = 0x1F200000, 700 AddSubExtendedMask = 0xFFE00000, 701 #define ADD_SUB_EXTENDED(A) \ 702 A##_w_ext = AddSubExtendedFixed | A, \ 703 A##_x_ext = AddSubExtendedFixed | A | SixtyFourBits 704 ADD_SUB_OP_LIST(ADD_SUB_EXTENDED) 705 #undef ADD_SUB_EXTENDED 706}; 707 708// Add/sub with carry. 709enum AddSubWithCarryOp { 710 AddSubWithCarryFixed = 0x1A000000, 711 AddSubWithCarryFMask = 0x1FE00000, 712 AddSubWithCarryMask = 0xFFE0FC00, 713 ADC_w = AddSubWithCarryFixed | ADD, 714 ADC_x = AddSubWithCarryFixed | ADD | SixtyFourBits, 715 ADC = ADC_w, 716 ADCS_w = AddSubWithCarryFixed | ADDS, 717 ADCS_x = AddSubWithCarryFixed | ADDS | SixtyFourBits, 718 SBC_w = AddSubWithCarryFixed | SUB, 719 SBC_x = AddSubWithCarryFixed | SUB | SixtyFourBits, 720 SBC = SBC_w, 721 SBCS_w = AddSubWithCarryFixed | SUBS, 722 SBCS_x = AddSubWithCarryFixed | SUBS | SixtyFourBits 723}; 724 725// Rotate right into flags. 726enum RotateRightIntoFlagsOp { 727 RotateRightIntoFlagsFixed = 0x1A000400, 728 RotateRightIntoFlagsFMask = 0x1FE07C00, 729 RotateRightIntoFlagsMask = 0xFFE07C10, 730 RMIF = RotateRightIntoFlagsFixed | 0xA0000000 731}; 732 733// Evaluate into flags. 734enum EvaluateIntoFlagsOp { 735 EvaluateIntoFlagsFixed = 0x1A000800, 736 EvaluateIntoFlagsFMask = 0x1FE03C00, 737 EvaluateIntoFlagsMask = 0xFFE07C1F, 738 SETF8 = EvaluateIntoFlagsFixed | 0x2000000D, 739 SETF16 = EvaluateIntoFlagsFixed | 0x2000400D 740}; 741 742 743// Logical (immediate and shifted register). 744enum LogicalOp { 745 LogicalOpMask = 0x60200000, 746 NOT = 0x00200000, 747 AND = 0x00000000, 748 BIC = AND | NOT, 749 ORR = 0x20000000, 750 ORN = ORR | NOT, 751 EOR = 0x40000000, 752 EON = EOR | NOT, 753 ANDS = 0x60000000, 754 BICS = ANDS | NOT 755}; 756 757// Logical immediate. 758enum LogicalImmediateOp { 759 LogicalImmediateFixed = 0x12000000, 760 LogicalImmediateFMask = 0x1F800000, 761 LogicalImmediateMask = 0xFF800000, 762 AND_w_imm = LogicalImmediateFixed | AND, 763 AND_x_imm = LogicalImmediateFixed | AND | SixtyFourBits, 764 ORR_w_imm = LogicalImmediateFixed | ORR, 765 ORR_x_imm = LogicalImmediateFixed | ORR | SixtyFourBits, 766 EOR_w_imm = LogicalImmediateFixed | EOR, 767 EOR_x_imm = LogicalImmediateFixed | EOR | SixtyFourBits, 768 ANDS_w_imm = LogicalImmediateFixed | ANDS, 769 ANDS_x_imm = LogicalImmediateFixed | ANDS | SixtyFourBits 770}; 771 772// Logical shifted register. 773enum LogicalShiftedOp { 774 LogicalShiftedFixed = 0x0A000000, 775 LogicalShiftedFMask = 0x1F000000, 776 LogicalShiftedMask = 0xFF200000, 777 AND_w = LogicalShiftedFixed | AND, 778 AND_x = LogicalShiftedFixed | AND | SixtyFourBits, 779 AND_shift = AND_w, 780 BIC_w = LogicalShiftedFixed | BIC, 781 BIC_x = LogicalShiftedFixed | BIC | SixtyFourBits, 782 BIC_shift = BIC_w, 783 ORR_w = LogicalShiftedFixed | ORR, 784 ORR_x = LogicalShiftedFixed | ORR | SixtyFourBits, 785 ORR_shift = ORR_w, 786 ORN_w = LogicalShiftedFixed | ORN, 787 ORN_x = LogicalShiftedFixed | ORN | SixtyFourBits, 788 ORN_shift = ORN_w, 789 EOR_w = LogicalShiftedFixed | EOR, 790 EOR_x = LogicalShiftedFixed | EOR | SixtyFourBits, 791 EOR_shift = EOR_w, 792 EON_w = LogicalShiftedFixed | EON, 793 EON_x = LogicalShiftedFixed | EON | SixtyFourBits, 794 EON_shift = EON_w, 795 ANDS_w = LogicalShiftedFixed | ANDS, 796 ANDS_x = LogicalShiftedFixed | ANDS | SixtyFourBits, 797 ANDS_shift = ANDS_w, 798 BICS_w = LogicalShiftedFixed | BICS, 799 BICS_x = LogicalShiftedFixed | BICS | SixtyFourBits, 800 BICS_shift = BICS_w 801}; 802 803// Move wide immediate. 804enum MoveWideImmediateOp { 805 MoveWideImmediateFixed = 0x12800000, 806 MoveWideImmediateFMask = 0x1F800000, 807 MoveWideImmediateMask = 0xFF800000, 808 MOVN = 0x00000000, 809 MOVZ = 0x40000000, 810 MOVK = 0x60000000, 811 MOVN_w = MoveWideImmediateFixed | MOVN, 812 MOVN_x = MoveWideImmediateFixed | MOVN | SixtyFourBits, 813 MOVZ_w = MoveWideImmediateFixed | MOVZ, 814 MOVZ_x = MoveWideImmediateFixed | MOVZ | SixtyFourBits, 815 MOVK_w = MoveWideImmediateFixed | MOVK, 816 MOVK_x = MoveWideImmediateFixed | MOVK | SixtyFourBits 817}; 818 819// Bitfield. 820const int kBitfieldNOffset = 22; 821enum BitfieldOp { 822 BitfieldFixed = 0x13000000, 823 BitfieldFMask = 0x1F800000, 824 BitfieldMask = 0xFF800000, 825 SBFM_w = BitfieldFixed | 0x00000000, 826 SBFM_x = BitfieldFixed | 0x80000000, 827 SBFM = SBFM_w, 828 BFM_w = BitfieldFixed | 0x20000000, 829 BFM_x = BitfieldFixed | 0xA0000000, 830 BFM = BFM_w, 831 UBFM_w = BitfieldFixed | 0x40000000, 832 UBFM_x = BitfieldFixed | 0xC0000000, 833 UBFM = UBFM_w 834 // Bitfield N field. 835}; 836 837// Extract. 838enum ExtractOp { 839 ExtractFixed = 0x13800000, 840 ExtractFMask = 0x1F800000, 841 ExtractMask = 0xFFA00000, 842 EXTR_w = ExtractFixed | 0x00000000, 843 EXTR_x = ExtractFixed | 0x80000000, 844 EXTR = EXTR_w 845}; 846 847// Unconditional branch. 848enum UnconditionalBranchOp { 849 UnconditionalBranchFixed = 0x14000000, 850 UnconditionalBranchFMask = 0x7C000000, 851 UnconditionalBranchMask = 0xFC000000, 852 B = UnconditionalBranchFixed | 0x00000000, 853 BL = UnconditionalBranchFixed | 0x80000000 854}; 855 856// Unconditional branch to register. 857enum UnconditionalBranchToRegisterOp { 858 UnconditionalBranchToRegisterFixed = 0xD6000000, 859 UnconditionalBranchToRegisterFMask = 0xFE000000, 860 UnconditionalBranchToRegisterMask = 0xFFFFFC00, 861 BR = UnconditionalBranchToRegisterFixed | 0x001F0000, 862 BLR = UnconditionalBranchToRegisterFixed | 0x003F0000, 863 RET = UnconditionalBranchToRegisterFixed | 0x005F0000, 864 865 BRAAZ = UnconditionalBranchToRegisterFixed | 0x001F0800, 866 BRABZ = UnconditionalBranchToRegisterFixed | 0x001F0C00, 867 BLRAAZ = UnconditionalBranchToRegisterFixed | 0x003F0800, 868 BLRABZ = UnconditionalBranchToRegisterFixed | 0x003F0C00, 869 RETAA = UnconditionalBranchToRegisterFixed | 0x005F0800, 870 RETAB = UnconditionalBranchToRegisterFixed | 0x005F0C00, 871 BRAA = UnconditionalBranchToRegisterFixed | 0x011F0800, 872 BRAB = UnconditionalBranchToRegisterFixed | 0x011F0C00, 873 BLRAA = UnconditionalBranchToRegisterFixed | 0x013F0800, 874 BLRAB = UnconditionalBranchToRegisterFixed | 0x013F0C00 875}; 876 877// Compare and branch. 878enum CompareBranchOp { 879 CompareBranchFixed = 0x34000000, 880 CompareBranchFMask = 0x7E000000, 881 CompareBranchMask = 0xFF000000, 882 CBZ_w = CompareBranchFixed | 0x00000000, 883 CBZ_x = CompareBranchFixed | 0x80000000, 884 CBZ = CBZ_w, 885 CBNZ_w = CompareBranchFixed | 0x01000000, 886 CBNZ_x = CompareBranchFixed | 0x81000000, 887 CBNZ = CBNZ_w 888}; 889 890// Test and branch. 891enum TestBranchOp { 892 TestBranchFixed = 0x36000000, 893 TestBranchFMask = 0x7E000000, 894 TestBranchMask = 0x7F000000, 895 TBZ = TestBranchFixed | 0x00000000, 896 TBNZ = TestBranchFixed | 0x01000000 897}; 898 899// Conditional branch. 900enum ConditionalBranchOp { 901 ConditionalBranchFixed = 0x54000000, 902 ConditionalBranchFMask = 0xFE000000, 903 ConditionalBranchMask = 0xFF000010, 904 B_cond = ConditionalBranchFixed | 0x00000000 905}; 906 907// System. 908// System instruction encoding is complicated because some instructions use op 909// and CR fields to encode parameters. To handle this cleanly, the system 910// instructions are split into more than one enum. 911 912enum SystemOp { 913 SystemFixed = 0xD5000000, 914 SystemFMask = 0xFFC00000 915}; 916 917enum SystemSysRegOp { 918 SystemSysRegFixed = 0xD5100000, 919 SystemSysRegFMask = 0xFFD00000, 920 SystemSysRegMask = 0xFFF00000, 921 MRS = SystemSysRegFixed | 0x00200000, 922 MSR = SystemSysRegFixed | 0x00000000 923}; 924 925enum SystemPStateOp { 926 SystemPStateFixed = 0xD5004000, 927 SystemPStateFMask = 0xFFF8F000, 928 SystemPStateMask = 0xFFFFF0FF, 929 CFINV = SystemPStateFixed | 0x0000001F, 930 XAFLAG = SystemPStateFixed | 0x0000003F, 931 AXFLAG = SystemPStateFixed | 0x0000005F 932}; 933 934enum SystemHintOp { 935 SystemHintFixed = 0xD503201F, 936 SystemHintFMask = 0xFFFFF01F, 937 SystemHintMask = 0xFFFFF01F, 938 HINT = SystemHintFixed | 0x00000000 939}; 940 941enum SystemSysOp { 942 SystemSysFixed = 0xD5080000, 943 SystemSysFMask = 0xFFF80000, 944 SystemSysMask = 0xFFF80000, 945 SYS = SystemSysFixed | 0x00000000 946}; 947 948// Exception. 949enum ExceptionOp { 950 ExceptionFixed = 0xD4000000, 951 ExceptionFMask = 0xFF000000, 952 ExceptionMask = 0xFFE0001F, 953 HLT = ExceptionFixed | 0x00400000, 954 BRK = ExceptionFixed | 0x00200000, 955 SVC = ExceptionFixed | 0x00000001, 956 HVC = ExceptionFixed | 0x00000002, 957 SMC = ExceptionFixed | 0x00000003, 958 DCPS1 = ExceptionFixed | 0x00A00001, 959 DCPS2 = ExceptionFixed | 0x00A00002, 960 DCPS3 = ExceptionFixed | 0x00A00003 961}; 962 963enum MemBarrierOp { 964 MemBarrierFixed = 0xD503309F, 965 MemBarrierFMask = 0xFFFFF09F, 966 MemBarrierMask = 0xFFFFF0FF, 967 DSB = MemBarrierFixed | 0x00000000, 968 DMB = MemBarrierFixed | 0x00000020, 969 ISB = MemBarrierFixed | 0x00000040 970}; 971 972enum SystemExclusiveMonitorOp { 973 SystemExclusiveMonitorFixed = 0xD503305F, 974 SystemExclusiveMonitorFMask = 0xFFFFF0FF, 975 SystemExclusiveMonitorMask = 0xFFFFF0FF, 976 CLREX = SystemExclusiveMonitorFixed 977}; 978 979enum SystemPAuthOp { 980 SystemPAuthFixed = 0xD503211F, 981 SystemPAuthFMask = 0xFFFFFD1F, 982 SystemPAuthMask = 0xFFFFFFFF, 983 PACIA1716 = SystemPAuthFixed | 0x00000100, 984 PACIB1716 = SystemPAuthFixed | 0x00000140, 985 AUTIA1716 = SystemPAuthFixed | 0x00000180, 986 AUTIB1716 = SystemPAuthFixed | 0x000001C0, 987 PACIAZ = SystemPAuthFixed | 0x00000300, 988 PACIASP = SystemPAuthFixed | 0x00000320, 989 PACIBZ = SystemPAuthFixed | 0x00000340, 990 PACIBSP = SystemPAuthFixed | 0x00000360, 991 AUTIAZ = SystemPAuthFixed | 0x00000380, 992 AUTIASP = SystemPAuthFixed | 0x000003A0, 993 AUTIBZ = SystemPAuthFixed | 0x000003C0, 994 AUTIBSP = SystemPAuthFixed | 0x000003E0, 995 996 // XPACLRI has the same fixed mask as System Hints and needs to be handled 997 // differently. 998 XPACLRI = 0xD50320FF 999}; 1000 1001// Any load or store. 1002enum LoadStoreAnyOp { 1003 LoadStoreAnyFMask = 0x0a000000, 1004 LoadStoreAnyFixed = 0x08000000 1005}; 1006 1007// Any load pair or store pair. 1008enum LoadStorePairAnyOp { 1009 LoadStorePairAnyFMask = 0x3a000000, 1010 LoadStorePairAnyFixed = 0x28000000 1011}; 1012 1013#define LOAD_STORE_PAIR_OP_LIST(V) \ 1014 V(STP, w, 0x00000000), \ 1015 V(LDP, w, 0x00400000), \ 1016 V(LDPSW, x, 0x40400000), \ 1017 V(STP, x, 0x80000000), \ 1018 V(LDP, x, 0x80400000), \ 1019 V(STP, s, 0x04000000), \ 1020 V(LDP, s, 0x04400000), \ 1021 V(STP, d, 0x44000000), \ 1022 V(LDP, d, 0x44400000), \ 1023 V(STP, q, 0x84000000), \ 1024 V(LDP, q, 0x84400000) 1025 1026// Load/store pair (post, pre and offset.) 1027enum LoadStorePairOp { 1028 LoadStorePairMask = 0xC4400000, 1029 LoadStorePairLBit = 1 << 22, 1030 #define LOAD_STORE_PAIR(A, B, C) \ 1031 A##_##B = C 1032 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR) 1033 #undef LOAD_STORE_PAIR 1034}; 1035 1036enum LoadStorePairPostIndexOp { 1037 LoadStorePairPostIndexFixed = 0x28800000, 1038 LoadStorePairPostIndexFMask = 0x3B800000, 1039 LoadStorePairPostIndexMask = 0xFFC00000, 1040 #define LOAD_STORE_PAIR_POST_INDEX(A, B, C) \ 1041 A##_##B##_post = LoadStorePairPostIndexFixed | A##_##B 1042 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_POST_INDEX) 1043 #undef LOAD_STORE_PAIR_POST_INDEX 1044}; 1045 1046enum LoadStorePairPreIndexOp { 1047 LoadStorePairPreIndexFixed = 0x29800000, 1048 LoadStorePairPreIndexFMask = 0x3B800000, 1049 LoadStorePairPreIndexMask = 0xFFC00000, 1050 #define LOAD_STORE_PAIR_PRE_INDEX(A, B, C) \ 1051 A##_##B##_pre = LoadStorePairPreIndexFixed | A##_##B 1052 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_PRE_INDEX) 1053 #undef LOAD_STORE_PAIR_PRE_INDEX 1054}; 1055 1056enum LoadStorePairOffsetOp { 1057 LoadStorePairOffsetFixed = 0x29000000, 1058 LoadStorePairOffsetFMask = 0x3B800000, 1059 LoadStorePairOffsetMask = 0xFFC00000, 1060 #define LOAD_STORE_PAIR_OFFSET(A, B, C) \ 1061 A##_##B##_off = LoadStorePairOffsetFixed | A##_##B 1062 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_OFFSET) 1063 #undef LOAD_STORE_PAIR_OFFSET 1064}; 1065 1066enum LoadStorePairNonTemporalOp { 1067 LoadStorePairNonTemporalFixed = 0x28000000, 1068 LoadStorePairNonTemporalFMask = 0x3B800000, 1069 LoadStorePairNonTemporalMask = 0xFFC00000, 1070 LoadStorePairNonTemporalLBit = 1 << 22, 1071 STNP_w = LoadStorePairNonTemporalFixed | STP_w, 1072 LDNP_w = LoadStorePairNonTemporalFixed | LDP_w, 1073 STNP_x = LoadStorePairNonTemporalFixed | STP_x, 1074 LDNP_x = LoadStorePairNonTemporalFixed | LDP_x, 1075 STNP_s = LoadStorePairNonTemporalFixed | STP_s, 1076 LDNP_s = LoadStorePairNonTemporalFixed | LDP_s, 1077 STNP_d = LoadStorePairNonTemporalFixed | STP_d, 1078 LDNP_d = LoadStorePairNonTemporalFixed | LDP_d, 1079 STNP_q = LoadStorePairNonTemporalFixed | STP_q, 1080 LDNP_q = LoadStorePairNonTemporalFixed | LDP_q 1081}; 1082 1083// Load with pointer authentication. 1084enum LoadStorePACOp { 1085 LoadStorePACFixed = 0xF8200400, 1086 LoadStorePACFMask = 0xFF200400, 1087 LoadStorePACMask = 0xFFA00C00, 1088 LoadStorePACPreBit = 0x00000800, 1089 LDRAA = LoadStorePACFixed | 0x00000000, 1090 LDRAA_pre = LoadStorePACPreBit | LDRAA, 1091 LDRAB = LoadStorePACFixed | 0x00800000, 1092 LDRAB_pre = LoadStorePACPreBit | LDRAB 1093}; 1094 1095// Load literal. 1096enum LoadLiteralOp { 1097 LoadLiteralFixed = 0x18000000, 1098 LoadLiteralFMask = 0x3B000000, 1099 LoadLiteralMask = 0xFF000000, 1100 LDR_w_lit = LoadLiteralFixed | 0x00000000, 1101 LDR_x_lit = LoadLiteralFixed | 0x40000000, 1102 LDRSW_x_lit = LoadLiteralFixed | 0x80000000, 1103 PRFM_lit = LoadLiteralFixed | 0xC0000000, 1104 LDR_s_lit = LoadLiteralFixed | 0x04000000, 1105 LDR_d_lit = LoadLiteralFixed | 0x44000000, 1106 LDR_q_lit = LoadLiteralFixed | 0x84000000 1107}; 1108 1109#define LOAD_STORE_OP_LIST(V) \ 1110 V(ST, RB, w, 0x00000000), \ 1111 V(ST, RH, w, 0x40000000), \ 1112 V(ST, R, w, 0x80000000), \ 1113 V(ST, R, x, 0xC0000000), \ 1114 V(LD, RB, w, 0x00400000), \ 1115 V(LD, RH, w, 0x40400000), \ 1116 V(LD, R, w, 0x80400000), \ 1117 V(LD, R, x, 0xC0400000), \ 1118 V(LD, RSB, x, 0x00800000), \ 1119 V(LD, RSH, x, 0x40800000), \ 1120 V(LD, RSW, x, 0x80800000), \ 1121 V(LD, RSB, w, 0x00C00000), \ 1122 V(LD, RSH, w, 0x40C00000), \ 1123 V(ST, R, b, 0x04000000), \ 1124 V(ST, R, h, 0x44000000), \ 1125 V(ST, R, s, 0x84000000), \ 1126 V(ST, R, d, 0xC4000000), \ 1127 V(ST, R, q, 0x04800000), \ 1128 V(LD, R, b, 0x04400000), \ 1129 V(LD, R, h, 0x44400000), \ 1130 V(LD, R, s, 0x84400000), \ 1131 V(LD, R, d, 0xC4400000), \ 1132 V(LD, R, q, 0x04C00000) 1133 1134// Load/store (post, pre, offset and unsigned.) 1135enum LoadStoreOp { 1136 LoadStoreMask = 0xC4C00000, 1137 LoadStoreVMask = 0x04000000, 1138 #define LOAD_STORE(A, B, C, D) \ 1139 A##B##_##C = D 1140 LOAD_STORE_OP_LIST(LOAD_STORE), 1141 #undef LOAD_STORE 1142 PRFM = 0xC0800000 1143}; 1144 1145// Load/store unscaled offset. 1146enum LoadStoreUnscaledOffsetOp { 1147 LoadStoreUnscaledOffsetFixed = 0x38000000, 1148 LoadStoreUnscaledOffsetFMask = 0x3B200C00, 1149 LoadStoreUnscaledOffsetMask = 0xFFE00C00, 1150 PRFUM = LoadStoreUnscaledOffsetFixed | PRFM, 1151 #define LOAD_STORE_UNSCALED(A, B, C, D) \ 1152 A##U##B##_##C = LoadStoreUnscaledOffsetFixed | D 1153 LOAD_STORE_OP_LIST(LOAD_STORE_UNSCALED) 1154 #undef LOAD_STORE_UNSCALED 1155}; 1156 1157// Load/store post index. 1158enum LoadStorePostIndex { 1159 LoadStorePostIndexFixed = 0x38000400, 1160 LoadStorePostIndexFMask = 0x3B200C00, 1161 LoadStorePostIndexMask = 0xFFE00C00, 1162 #define LOAD_STORE_POST_INDEX(A, B, C, D) \ 1163 A##B##_##C##_post = LoadStorePostIndexFixed | D 1164 LOAD_STORE_OP_LIST(LOAD_STORE_POST_INDEX) 1165 #undef LOAD_STORE_POST_INDEX 1166}; 1167 1168// Load/store pre index. 1169enum LoadStorePreIndex { 1170 LoadStorePreIndexFixed = 0x38000C00, 1171 LoadStorePreIndexFMask = 0x3B200C00, 1172 LoadStorePreIndexMask = 0xFFE00C00, 1173 #define LOAD_STORE_PRE_INDEX(A, B, C, D) \ 1174 A##B##_##C##_pre = LoadStorePreIndexFixed | D 1175 LOAD_STORE_OP_LIST(LOAD_STORE_PRE_INDEX) 1176 #undef LOAD_STORE_PRE_INDEX 1177}; 1178 1179// Load/store unsigned offset. 1180enum LoadStoreUnsignedOffset { 1181 LoadStoreUnsignedOffsetFixed = 0x39000000, 1182 LoadStoreUnsignedOffsetFMask = 0x3B000000, 1183 LoadStoreUnsignedOffsetMask = 0xFFC00000, 1184 PRFM_unsigned = LoadStoreUnsignedOffsetFixed | PRFM, 1185 #define LOAD_STORE_UNSIGNED_OFFSET(A, B, C, D) \ 1186 A##B##_##C##_unsigned = LoadStoreUnsignedOffsetFixed | D 1187 LOAD_STORE_OP_LIST(LOAD_STORE_UNSIGNED_OFFSET) 1188 #undef LOAD_STORE_UNSIGNED_OFFSET 1189}; 1190 1191// Load/store register offset. 1192enum LoadStoreRegisterOffset { 1193 LoadStoreRegisterOffsetFixed = 0x38200800, 1194 LoadStoreRegisterOffsetFMask = 0x3B200C00, 1195 LoadStoreRegisterOffsetMask = 0xFFE00C00, 1196 PRFM_reg = LoadStoreRegisterOffsetFixed | PRFM, 1197 #define LOAD_STORE_REGISTER_OFFSET(A, B, C, D) \ 1198 A##B##_##C##_reg = LoadStoreRegisterOffsetFixed | D 1199 LOAD_STORE_OP_LIST(LOAD_STORE_REGISTER_OFFSET) 1200 #undef LOAD_STORE_REGISTER_OFFSET 1201}; 1202 1203enum LoadStoreExclusive { 1204 LoadStoreExclusiveFixed = 0x08000000, 1205 LoadStoreExclusiveFMask = 0x3F000000, 1206 LoadStoreExclusiveMask = 0xFFE08000, 1207 STXRB_w = LoadStoreExclusiveFixed | 0x00000000, 1208 STXRH_w = LoadStoreExclusiveFixed | 0x40000000, 1209 STXR_w = LoadStoreExclusiveFixed | 0x80000000, 1210 STXR_x = LoadStoreExclusiveFixed | 0xC0000000, 1211 LDXRB_w = LoadStoreExclusiveFixed | 0x00400000, 1212 LDXRH_w = LoadStoreExclusiveFixed | 0x40400000, 1213 LDXR_w = LoadStoreExclusiveFixed | 0x80400000, 1214 LDXR_x = LoadStoreExclusiveFixed | 0xC0400000, 1215 STXP_w = LoadStoreExclusiveFixed | 0x80200000, 1216 STXP_x = LoadStoreExclusiveFixed | 0xC0200000, 1217 LDXP_w = LoadStoreExclusiveFixed | 0x80600000, 1218 LDXP_x = LoadStoreExclusiveFixed | 0xC0600000, 1219 STLXRB_w = LoadStoreExclusiveFixed | 0x00008000, 1220 STLXRH_w = LoadStoreExclusiveFixed | 0x40008000, 1221 STLXR_w = LoadStoreExclusiveFixed | 0x80008000, 1222 STLXR_x = LoadStoreExclusiveFixed | 0xC0008000, 1223 LDAXRB_w = LoadStoreExclusiveFixed | 0x00408000, 1224 LDAXRH_w = LoadStoreExclusiveFixed | 0x40408000, 1225 LDAXR_w = LoadStoreExclusiveFixed | 0x80408000, 1226 LDAXR_x = LoadStoreExclusiveFixed | 0xC0408000, 1227 STLXP_w = LoadStoreExclusiveFixed | 0x80208000, 1228 STLXP_x = LoadStoreExclusiveFixed | 0xC0208000, 1229 LDAXP_w = LoadStoreExclusiveFixed | 0x80608000, 1230 LDAXP_x = LoadStoreExclusiveFixed | 0xC0608000, 1231 STLRB_w = LoadStoreExclusiveFixed | 0x00808000, 1232 STLRH_w = LoadStoreExclusiveFixed | 0x40808000, 1233 STLR_w = LoadStoreExclusiveFixed | 0x80808000, 1234 STLR_x = LoadStoreExclusiveFixed | 0xC0808000, 1235 LDARB_w = LoadStoreExclusiveFixed | 0x00C08000, 1236 LDARH_w = LoadStoreExclusiveFixed | 0x40C08000, 1237 LDAR_w = LoadStoreExclusiveFixed | 0x80C08000, 1238 LDAR_x = LoadStoreExclusiveFixed | 0xC0C08000, 1239 1240 // v8.1 Load/store LORegion ops 1241 STLLRB = LoadStoreExclusiveFixed | 0x00800000, 1242 LDLARB = LoadStoreExclusiveFixed | 0x00C00000, 1243 STLLRH = LoadStoreExclusiveFixed | 0x40800000, 1244 LDLARH = LoadStoreExclusiveFixed | 0x40C00000, 1245 STLLR_w = LoadStoreExclusiveFixed | 0x80800000, 1246 LDLAR_w = LoadStoreExclusiveFixed | 0x80C00000, 1247 STLLR_x = LoadStoreExclusiveFixed | 0xC0800000, 1248 LDLAR_x = LoadStoreExclusiveFixed | 0xC0C00000, 1249 1250 // v8.1 Load/store exclusive ops 1251 LSEBit_l = 0x00400000, 1252 LSEBit_o0 = 0x00008000, 1253 LSEBit_sz = 0x40000000, 1254 CASFixed = LoadStoreExclusiveFixed | 0x80A00000, 1255 CASBFixed = LoadStoreExclusiveFixed | 0x00A00000, 1256 CASHFixed = LoadStoreExclusiveFixed | 0x40A00000, 1257 CASPFixed = LoadStoreExclusiveFixed | 0x00200000, 1258 CAS_w = CASFixed, 1259 CAS_x = CASFixed | LSEBit_sz, 1260 CASA_w = CASFixed | LSEBit_l, 1261 CASA_x = CASFixed | LSEBit_l | LSEBit_sz, 1262 CASL_w = CASFixed | LSEBit_o0, 1263 CASL_x = CASFixed | LSEBit_o0 | LSEBit_sz, 1264 CASAL_w = CASFixed | LSEBit_l | LSEBit_o0, 1265 CASAL_x = CASFixed | LSEBit_l | LSEBit_o0 | LSEBit_sz, 1266 CASB = CASBFixed, 1267 CASAB = CASBFixed | LSEBit_l, 1268 CASLB = CASBFixed | LSEBit_o0, 1269 CASALB = CASBFixed | LSEBit_l | LSEBit_o0, 1270 CASH = CASHFixed, 1271 CASAH = CASHFixed | LSEBit_l, 1272 CASLH = CASHFixed | LSEBit_o0, 1273 CASALH = CASHFixed | LSEBit_l | LSEBit_o0, 1274 CASP_w = CASPFixed, 1275 CASP_x = CASPFixed | LSEBit_sz, 1276 CASPA_w = CASPFixed | LSEBit_l, 1277 CASPA_x = CASPFixed | LSEBit_l | LSEBit_sz, 1278 CASPL_w = CASPFixed | LSEBit_o0, 1279 CASPL_x = CASPFixed | LSEBit_o0 | LSEBit_sz, 1280 CASPAL_w = CASPFixed | LSEBit_l | LSEBit_o0, 1281 CASPAL_x = CASPFixed | LSEBit_l | LSEBit_o0 | LSEBit_sz 1282}; 1283 1284// Load/store RCpc unscaled offset. 1285enum LoadStoreRCpcUnscaledOffsetOp { 1286 LoadStoreRCpcUnscaledOffsetFixed = 0x19000000, 1287 LoadStoreRCpcUnscaledOffsetFMask = 0x3F200C00, 1288 LoadStoreRCpcUnscaledOffsetMask = 0xFFE00C00, 1289 STLURB = LoadStoreRCpcUnscaledOffsetFixed | 0x00000000, 1290 LDAPURB = LoadStoreRCpcUnscaledOffsetFixed | 0x00400000, 1291 LDAPURSB_x = LoadStoreRCpcUnscaledOffsetFixed | 0x00800000, 1292 LDAPURSB_w = LoadStoreRCpcUnscaledOffsetFixed | 0x00C00000, 1293 STLURH = LoadStoreRCpcUnscaledOffsetFixed | 0x40000000, 1294 LDAPURH = LoadStoreRCpcUnscaledOffsetFixed | 0x40400000, 1295 LDAPURSH_x = LoadStoreRCpcUnscaledOffsetFixed | 0x40800000, 1296 LDAPURSH_w = LoadStoreRCpcUnscaledOffsetFixed | 0x40C00000, 1297 STLUR_w = LoadStoreRCpcUnscaledOffsetFixed | 0x80000000, 1298 LDAPUR_w = LoadStoreRCpcUnscaledOffsetFixed | 0x80400000, 1299 LDAPURSW = LoadStoreRCpcUnscaledOffsetFixed | 0x80800000, 1300 STLUR_x = LoadStoreRCpcUnscaledOffsetFixed | 0xC0000000, 1301 LDAPUR_x = LoadStoreRCpcUnscaledOffsetFixed | 0xC0400000 1302}; 1303 1304#define ATOMIC_MEMORY_SIMPLE_OPC_LIST(V) \ 1305 V(LDADD, 0x00000000), \ 1306 V(LDCLR, 0x00001000), \ 1307 V(LDEOR, 0x00002000), \ 1308 V(LDSET, 0x00003000), \ 1309 V(LDSMAX, 0x00004000), \ 1310 V(LDSMIN, 0x00005000), \ 1311 V(LDUMAX, 0x00006000), \ 1312 V(LDUMIN, 0x00007000) 1313 1314// Atomic memory. 1315enum AtomicMemoryOp { 1316 AtomicMemoryFixed = 0x38200000, 1317 AtomicMemoryFMask = 0x3B200C00, 1318 AtomicMemoryMask = 0xFFE0FC00, 1319 SWPB = AtomicMemoryFixed | 0x00008000, 1320 SWPAB = AtomicMemoryFixed | 0x00808000, 1321 SWPLB = AtomicMemoryFixed | 0x00408000, 1322 SWPALB = AtomicMemoryFixed | 0x00C08000, 1323 SWPH = AtomicMemoryFixed | 0x40008000, 1324 SWPAH = AtomicMemoryFixed | 0x40808000, 1325 SWPLH = AtomicMemoryFixed | 0x40408000, 1326 SWPALH = AtomicMemoryFixed | 0x40C08000, 1327 SWP_w = AtomicMemoryFixed | 0x80008000, 1328 SWPA_w = AtomicMemoryFixed | 0x80808000, 1329 SWPL_w = AtomicMemoryFixed | 0x80408000, 1330 SWPAL_w = AtomicMemoryFixed | 0x80C08000, 1331 SWP_x = AtomicMemoryFixed | 0xC0008000, 1332 SWPA_x = AtomicMemoryFixed | 0xC0808000, 1333 SWPL_x = AtomicMemoryFixed | 0xC0408000, 1334 SWPAL_x = AtomicMemoryFixed | 0xC0C08000, 1335 LDAPRB = AtomicMemoryFixed | 0x0080C000, 1336 LDAPRH = AtomicMemoryFixed | 0x4080C000, 1337 LDAPR_w = AtomicMemoryFixed | 0x8080C000, 1338 LDAPR_x = AtomicMemoryFixed | 0xC080C000, 1339 1340 AtomicMemorySimpleFMask = 0x3B208C00, 1341 AtomicMemorySimpleOpMask = 0x00007000, 1342#define ATOMIC_MEMORY_SIMPLE(N, OP) \ 1343 N##Op = OP, \ 1344 N##B = AtomicMemoryFixed | OP, \ 1345 N##AB = AtomicMemoryFixed | OP | 0x00800000, \ 1346 N##LB = AtomicMemoryFixed | OP | 0x00400000, \ 1347 N##ALB = AtomicMemoryFixed | OP | 0x00C00000, \ 1348 N##H = AtomicMemoryFixed | OP | 0x40000000, \ 1349 N##AH = AtomicMemoryFixed | OP | 0x40800000, \ 1350 N##LH = AtomicMemoryFixed | OP | 0x40400000, \ 1351 N##ALH = AtomicMemoryFixed | OP | 0x40C00000, \ 1352 N##_w = AtomicMemoryFixed | OP | 0x80000000, \ 1353 N##A_w = AtomicMemoryFixed | OP | 0x80800000, \ 1354 N##L_w = AtomicMemoryFixed | OP | 0x80400000, \ 1355 N##AL_w = AtomicMemoryFixed | OP | 0x80C00000, \ 1356 N##_x = AtomicMemoryFixed | OP | 0xC0000000, \ 1357 N##A_x = AtomicMemoryFixed | OP | 0xC0800000, \ 1358 N##L_x = AtomicMemoryFixed | OP | 0xC0400000, \ 1359 N##AL_x = AtomicMemoryFixed | OP | 0xC0C00000 1360 1361 ATOMIC_MEMORY_SIMPLE_OPC_LIST(ATOMIC_MEMORY_SIMPLE) 1362#undef ATOMIC_MEMORY_SIMPLE 1363}; 1364 1365// Conditional compare. 1366enum ConditionalCompareOp { 1367 ConditionalCompareMask = 0x60000000, 1368 CCMN = 0x20000000, 1369 CCMP = 0x60000000 1370}; 1371 1372// Conditional compare register. 1373enum ConditionalCompareRegisterOp { 1374 ConditionalCompareRegisterFixed = 0x1A400000, 1375 ConditionalCompareRegisterFMask = 0x1FE00800, 1376 ConditionalCompareRegisterMask = 0xFFE00C10, 1377 CCMN_w = ConditionalCompareRegisterFixed | CCMN, 1378 CCMN_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMN, 1379 CCMP_w = ConditionalCompareRegisterFixed | CCMP, 1380 CCMP_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMP 1381}; 1382 1383// Conditional compare immediate. 1384enum ConditionalCompareImmediateOp { 1385 ConditionalCompareImmediateFixed = 0x1A400800, 1386 ConditionalCompareImmediateFMask = 0x1FE00800, 1387 ConditionalCompareImmediateMask = 0xFFE00C10, 1388 CCMN_w_imm = ConditionalCompareImmediateFixed | CCMN, 1389 CCMN_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMN, 1390 CCMP_w_imm = ConditionalCompareImmediateFixed | CCMP, 1391 CCMP_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMP 1392}; 1393 1394// Conditional select. 1395enum ConditionalSelectOp { 1396 ConditionalSelectFixed = 0x1A800000, 1397 ConditionalSelectFMask = 0x1FE00000, 1398 ConditionalSelectMask = 0xFFE00C00, 1399 CSEL_w = ConditionalSelectFixed | 0x00000000, 1400 CSEL_x = ConditionalSelectFixed | 0x80000000, 1401 CSEL = CSEL_w, 1402 CSINC_w = ConditionalSelectFixed | 0x00000400, 1403 CSINC_x = ConditionalSelectFixed | 0x80000400, 1404 CSINC = CSINC_w, 1405 CSINV_w = ConditionalSelectFixed | 0x40000000, 1406 CSINV_x = ConditionalSelectFixed | 0xC0000000, 1407 CSINV = CSINV_w, 1408 CSNEG_w = ConditionalSelectFixed | 0x40000400, 1409 CSNEG_x = ConditionalSelectFixed | 0xC0000400, 1410 CSNEG = CSNEG_w 1411}; 1412 1413// Data processing 1 source. 1414enum DataProcessing1SourceOp { 1415 DataProcessing1SourceFixed = 0x5AC00000, 1416 DataProcessing1SourceFMask = 0x5FE00000, 1417 DataProcessing1SourceMask = 0xFFFFFC00, 1418 RBIT = DataProcessing1SourceFixed | 0x00000000, 1419 RBIT_w = RBIT, 1420 RBIT_x = RBIT | SixtyFourBits, 1421 REV16 = DataProcessing1SourceFixed | 0x00000400, 1422 REV16_w = REV16, 1423 REV16_x = REV16 | SixtyFourBits, 1424 REV = DataProcessing1SourceFixed | 0x00000800, 1425 REV_w = REV, 1426 REV32_x = REV | SixtyFourBits, 1427 REV_x = DataProcessing1SourceFixed | SixtyFourBits | 0x00000C00, 1428 CLZ = DataProcessing1SourceFixed | 0x00001000, 1429 CLZ_w = CLZ, 1430 CLZ_x = CLZ | SixtyFourBits, 1431 CLS = DataProcessing1SourceFixed | 0x00001400, 1432 CLS_w = CLS, 1433 CLS_x = CLS | SixtyFourBits, 1434 1435 // Pointer authentication instructions in Armv8.3. 1436 PACIA = DataProcessing1SourceFixed | 0x80010000, 1437 PACIB = DataProcessing1SourceFixed | 0x80010400, 1438 PACDA = DataProcessing1SourceFixed | 0x80010800, 1439 PACDB = DataProcessing1SourceFixed | 0x80010C00, 1440 AUTIA = DataProcessing1SourceFixed | 0x80011000, 1441 AUTIB = DataProcessing1SourceFixed | 0x80011400, 1442 AUTDA = DataProcessing1SourceFixed | 0x80011800, 1443 AUTDB = DataProcessing1SourceFixed | 0x80011C00, 1444 PACIZA = DataProcessing1SourceFixed | 0x80012000, 1445 PACIZB = DataProcessing1SourceFixed | 0x80012400, 1446 PACDZA = DataProcessing1SourceFixed | 0x80012800, 1447 PACDZB = DataProcessing1SourceFixed | 0x80012C00, 1448 AUTIZA = DataProcessing1SourceFixed | 0x80013000, 1449 AUTIZB = DataProcessing1SourceFixed | 0x80013400, 1450 AUTDZA = DataProcessing1SourceFixed | 0x80013800, 1451 AUTDZB = DataProcessing1SourceFixed | 0x80013C00, 1452 XPACI = DataProcessing1SourceFixed | 0x80014000, 1453 XPACD = DataProcessing1SourceFixed | 0x80014400 1454}; 1455 1456// Data processing 2 source. 1457enum DataProcessing2SourceOp { 1458 DataProcessing2SourceFixed = 0x1AC00000, 1459 DataProcessing2SourceFMask = 0x5FE00000, 1460 DataProcessing2SourceMask = 0xFFE0FC00, 1461 UDIV_w = DataProcessing2SourceFixed | 0x00000800, 1462 UDIV_x = DataProcessing2SourceFixed | 0x80000800, 1463 UDIV = UDIV_w, 1464 SDIV_w = DataProcessing2SourceFixed | 0x00000C00, 1465 SDIV_x = DataProcessing2SourceFixed | 0x80000C00, 1466 SDIV = SDIV_w, 1467 LSLV_w = DataProcessing2SourceFixed | 0x00002000, 1468 LSLV_x = DataProcessing2SourceFixed | 0x80002000, 1469 LSLV = LSLV_w, 1470 LSRV_w = DataProcessing2SourceFixed | 0x00002400, 1471 LSRV_x = DataProcessing2SourceFixed | 0x80002400, 1472 LSRV = LSRV_w, 1473 ASRV_w = DataProcessing2SourceFixed | 0x00002800, 1474 ASRV_x = DataProcessing2SourceFixed | 0x80002800, 1475 ASRV = ASRV_w, 1476 RORV_w = DataProcessing2SourceFixed | 0x00002C00, 1477 RORV_x = DataProcessing2SourceFixed | 0x80002C00, 1478 RORV = RORV_w, 1479 PACGA = DataProcessing2SourceFixed | SixtyFourBits | 0x00003000, 1480 CRC32B = DataProcessing2SourceFixed | 0x00004000, 1481 CRC32H = DataProcessing2SourceFixed | 0x00004400, 1482 CRC32W = DataProcessing2SourceFixed | 0x00004800, 1483 CRC32X = DataProcessing2SourceFixed | SixtyFourBits | 0x00004C00, 1484 CRC32CB = DataProcessing2SourceFixed | 0x00005000, 1485 CRC32CH = DataProcessing2SourceFixed | 0x00005400, 1486 CRC32CW = DataProcessing2SourceFixed | 0x00005800, 1487 CRC32CX = DataProcessing2SourceFixed | SixtyFourBits | 0x00005C00 1488}; 1489 1490// Data processing 3 source. 1491enum DataProcessing3SourceOp { 1492 DataProcessing3SourceFixed = 0x1B000000, 1493 DataProcessing3SourceFMask = 0x1F000000, 1494 DataProcessing3SourceMask = 0xFFE08000, 1495 MADD_w = DataProcessing3SourceFixed | 0x00000000, 1496 MADD_x = DataProcessing3SourceFixed | 0x80000000, 1497 MADD = MADD_w, 1498 MSUB_w = DataProcessing3SourceFixed | 0x00008000, 1499 MSUB_x = DataProcessing3SourceFixed | 0x80008000, 1500 MSUB = MSUB_w, 1501 SMADDL_x = DataProcessing3SourceFixed | 0x80200000, 1502 SMSUBL_x = DataProcessing3SourceFixed | 0x80208000, 1503 SMULH_x = DataProcessing3SourceFixed | 0x80400000, 1504 UMADDL_x = DataProcessing3SourceFixed | 0x80A00000, 1505 UMSUBL_x = DataProcessing3SourceFixed | 0x80A08000, 1506 UMULH_x = DataProcessing3SourceFixed | 0x80C00000 1507}; 1508 1509// Floating point compare. 1510enum FPCompareOp { 1511 FPCompareFixed = 0x1E202000, 1512 FPCompareFMask = 0x5F203C00, 1513 FPCompareMask = 0xFFE0FC1F, 1514 FCMP_h = FPCompareFixed | FP16 | 0x00000000, 1515 FCMP_s = FPCompareFixed | 0x00000000, 1516 FCMP_d = FPCompareFixed | FP64 | 0x00000000, 1517 FCMP = FCMP_s, 1518 FCMP_h_zero = FPCompareFixed | FP16 | 0x00000008, 1519 FCMP_s_zero = FPCompareFixed | 0x00000008, 1520 FCMP_d_zero = FPCompareFixed | FP64 | 0x00000008, 1521 FCMP_zero = FCMP_s_zero, 1522 FCMPE_h = FPCompareFixed | FP16 | 0x00000010, 1523 FCMPE_s = FPCompareFixed | 0x00000010, 1524 FCMPE_d = FPCompareFixed | FP64 | 0x00000010, 1525 FCMPE = FCMPE_s, 1526 FCMPE_h_zero = FPCompareFixed | FP16 | 0x00000018, 1527 FCMPE_s_zero = FPCompareFixed | 0x00000018, 1528 FCMPE_d_zero = FPCompareFixed | FP64 | 0x00000018, 1529 FCMPE_zero = FCMPE_s_zero 1530}; 1531 1532// Floating point conditional compare. 1533enum FPConditionalCompareOp { 1534 FPConditionalCompareFixed = 0x1E200400, 1535 FPConditionalCompareFMask = 0x5F200C00, 1536 FPConditionalCompareMask = 0xFFE00C10, 1537 FCCMP_h = FPConditionalCompareFixed | FP16 | 0x00000000, 1538 FCCMP_s = FPConditionalCompareFixed | 0x00000000, 1539 FCCMP_d = FPConditionalCompareFixed | FP64 | 0x00000000, 1540 FCCMP = FCCMP_s, 1541 FCCMPE_h = FPConditionalCompareFixed | FP16 | 0x00000010, 1542 FCCMPE_s = FPConditionalCompareFixed | 0x00000010, 1543 FCCMPE_d = FPConditionalCompareFixed | FP64 | 0x00000010, 1544 FCCMPE = FCCMPE_s 1545}; 1546 1547// Floating point conditional select. 1548enum FPConditionalSelectOp { 1549 FPConditionalSelectFixed = 0x1E200C00, 1550 FPConditionalSelectFMask = 0x5F200C00, 1551 FPConditionalSelectMask = 0xFFE00C00, 1552 FCSEL_h = FPConditionalSelectFixed | FP16 | 0x00000000, 1553 FCSEL_s = FPConditionalSelectFixed | 0x00000000, 1554 FCSEL_d = FPConditionalSelectFixed | FP64 | 0x00000000, 1555 FCSEL = FCSEL_s 1556}; 1557 1558// Floating point immediate. 1559enum FPImmediateOp { 1560 FPImmediateFixed = 0x1E201000, 1561 FPImmediateFMask = 0x5F201C00, 1562 FPImmediateMask = 0xFFE01C00, 1563 FMOV_h_imm = FPImmediateFixed | FP16 | 0x00000000, 1564 FMOV_s_imm = FPImmediateFixed | 0x00000000, 1565 FMOV_d_imm = FPImmediateFixed | FP64 | 0x00000000 1566}; 1567 1568// Floating point data processing 1 source. 1569enum FPDataProcessing1SourceOp { 1570 FPDataProcessing1SourceFixed = 0x1E204000, 1571 FPDataProcessing1SourceFMask = 0x5F207C00, 1572 FPDataProcessing1SourceMask = 0xFFFFFC00, 1573 FMOV_h = FPDataProcessing1SourceFixed | FP16 | 0x00000000, 1574 FMOV_s = FPDataProcessing1SourceFixed | 0x00000000, 1575 FMOV_d = FPDataProcessing1SourceFixed | FP64 | 0x00000000, 1576 FMOV = FMOV_s, 1577 FABS_h = FPDataProcessing1SourceFixed | FP16 | 0x00008000, 1578 FABS_s = FPDataProcessing1SourceFixed | 0x00008000, 1579 FABS_d = FPDataProcessing1SourceFixed | FP64 | 0x00008000, 1580 FABS = FABS_s, 1581 FNEG_h = FPDataProcessing1SourceFixed | FP16 | 0x00010000, 1582 FNEG_s = FPDataProcessing1SourceFixed | 0x00010000, 1583 FNEG_d = FPDataProcessing1SourceFixed | FP64 | 0x00010000, 1584 FNEG = FNEG_s, 1585 FSQRT_h = FPDataProcessing1SourceFixed | FP16 | 0x00018000, 1586 FSQRT_s = FPDataProcessing1SourceFixed | 0x00018000, 1587 FSQRT_d = FPDataProcessing1SourceFixed | FP64 | 0x00018000, 1588 FSQRT = FSQRT_s, 1589 FCVT_ds = FPDataProcessing1SourceFixed | 0x00028000, 1590 FCVT_sd = FPDataProcessing1SourceFixed | FP64 | 0x00020000, 1591 FCVT_hs = FPDataProcessing1SourceFixed | 0x00038000, 1592 FCVT_hd = FPDataProcessing1SourceFixed | FP64 | 0x00038000, 1593 FCVT_sh = FPDataProcessing1SourceFixed | 0x00C20000, 1594 FCVT_dh = FPDataProcessing1SourceFixed | 0x00C28000, 1595 FRINT32X_s = FPDataProcessing1SourceFixed | 0x00088000, 1596 FRINT32X_d = FPDataProcessing1SourceFixed | FP64 | 0x00088000, 1597 FRINT32X = FRINT32X_s, 1598 FRINT32Z_s = FPDataProcessing1SourceFixed | 0x00080000, 1599 FRINT32Z_d = FPDataProcessing1SourceFixed | FP64 | 0x00080000, 1600 FRINT32Z = FRINT32Z_s, 1601 FRINT64X_s = FPDataProcessing1SourceFixed | 0x00098000, 1602 FRINT64X_d = FPDataProcessing1SourceFixed | FP64 | 0x00098000, 1603 FRINT64X = FRINT64X_s, 1604 FRINT64Z_s = FPDataProcessing1SourceFixed | 0x00090000, 1605 FRINT64Z_d = FPDataProcessing1SourceFixed | FP64 | 0x00090000, 1606 FRINT64Z = FRINT64Z_s, 1607 FRINTN_h = FPDataProcessing1SourceFixed | FP16 | 0x00040000, 1608 FRINTN_s = FPDataProcessing1SourceFixed | 0x00040000, 1609 FRINTN_d = FPDataProcessing1SourceFixed | FP64 | 0x00040000, 1610 FRINTN = FRINTN_s, 1611 FRINTP_h = FPDataProcessing1SourceFixed | FP16 | 0x00048000, 1612 FRINTP_s = FPDataProcessing1SourceFixed | 0x00048000, 1613 FRINTP_d = FPDataProcessing1SourceFixed | FP64 | 0x00048000, 1614 FRINTP = FRINTP_s, 1615 FRINTM_h = FPDataProcessing1SourceFixed | FP16 | 0x00050000, 1616 FRINTM_s = FPDataProcessing1SourceFixed | 0x00050000, 1617 FRINTM_d = FPDataProcessing1SourceFixed | FP64 | 0x00050000, 1618 FRINTM = FRINTM_s, 1619 FRINTZ_h = FPDataProcessing1SourceFixed | FP16 | 0x00058000, 1620 FRINTZ_s = FPDataProcessing1SourceFixed | 0x00058000, 1621 FRINTZ_d = FPDataProcessing1SourceFixed | FP64 | 0x00058000, 1622 FRINTZ = FRINTZ_s, 1623 FRINTA_h = FPDataProcessing1SourceFixed | FP16 | 0x00060000, 1624 FRINTA_s = FPDataProcessing1SourceFixed | 0x00060000, 1625 FRINTA_d = FPDataProcessing1SourceFixed | FP64 | 0x00060000, 1626 FRINTA = FRINTA_s, 1627 FRINTX_h = FPDataProcessing1SourceFixed | FP16 | 0x00070000, 1628 FRINTX_s = FPDataProcessing1SourceFixed | 0x00070000, 1629 FRINTX_d = FPDataProcessing1SourceFixed | FP64 | 0x00070000, 1630 FRINTX = FRINTX_s, 1631 FRINTI_h = FPDataProcessing1SourceFixed | FP16 | 0x00078000, 1632 FRINTI_s = FPDataProcessing1SourceFixed | 0x00078000, 1633 FRINTI_d = FPDataProcessing1SourceFixed | FP64 | 0x00078000, 1634 FRINTI = FRINTI_s 1635}; 1636 1637// Floating point data processing 2 source. 1638enum FPDataProcessing2SourceOp { 1639 FPDataProcessing2SourceFixed = 0x1E200800, 1640 FPDataProcessing2SourceFMask = 0x5F200C00, 1641 FPDataProcessing2SourceMask = 0xFFE0FC00, 1642 FMUL = FPDataProcessing2SourceFixed | 0x00000000, 1643 FMUL_h = FMUL | FP16, 1644 FMUL_s = FMUL, 1645 FMUL_d = FMUL | FP64, 1646 FDIV = FPDataProcessing2SourceFixed | 0x00001000, 1647 FDIV_h = FDIV | FP16, 1648 FDIV_s = FDIV, 1649 FDIV_d = FDIV | FP64, 1650 FADD = FPDataProcessing2SourceFixed | 0x00002000, 1651 FADD_h = FADD | FP16, 1652 FADD_s = FADD, 1653 FADD_d = FADD | FP64, 1654 FSUB = FPDataProcessing2SourceFixed | 0x00003000, 1655 FSUB_h = FSUB | FP16, 1656 FSUB_s = FSUB, 1657 FSUB_d = FSUB | FP64, 1658 FMAX = FPDataProcessing2SourceFixed | 0x00004000, 1659 FMAX_h = FMAX | FP16, 1660 FMAX_s = FMAX, 1661 FMAX_d = FMAX | FP64, 1662 FMIN = FPDataProcessing2SourceFixed | 0x00005000, 1663 FMIN_h = FMIN | FP16, 1664 FMIN_s = FMIN, 1665 FMIN_d = FMIN | FP64, 1666 FMAXNM = FPDataProcessing2SourceFixed | 0x00006000, 1667 FMAXNM_h = FMAXNM | FP16, 1668 FMAXNM_s = FMAXNM, 1669 FMAXNM_d = FMAXNM | FP64, 1670 FMINNM = FPDataProcessing2SourceFixed | 0x00007000, 1671 FMINNM_h = FMINNM | FP16, 1672 FMINNM_s = FMINNM, 1673 FMINNM_d = FMINNM | FP64, 1674 FNMUL = FPDataProcessing2SourceFixed | 0x00008000, 1675 FNMUL_h = FNMUL | FP16, 1676 FNMUL_s = FNMUL, 1677 FNMUL_d = FNMUL | FP64 1678}; 1679 1680// Floating point data processing 3 source. 1681enum FPDataProcessing3SourceOp { 1682 FPDataProcessing3SourceFixed = 0x1F000000, 1683 FPDataProcessing3SourceFMask = 0x5F000000, 1684 FPDataProcessing3SourceMask = 0xFFE08000, 1685 FMADD_h = FPDataProcessing3SourceFixed | 0x00C00000, 1686 FMSUB_h = FPDataProcessing3SourceFixed | 0x00C08000, 1687 FNMADD_h = FPDataProcessing3SourceFixed | 0x00E00000, 1688 FNMSUB_h = FPDataProcessing3SourceFixed | 0x00E08000, 1689 FMADD_s = FPDataProcessing3SourceFixed | 0x00000000, 1690 FMSUB_s = FPDataProcessing3SourceFixed | 0x00008000, 1691 FNMADD_s = FPDataProcessing3SourceFixed | 0x00200000, 1692 FNMSUB_s = FPDataProcessing3SourceFixed | 0x00208000, 1693 FMADD_d = FPDataProcessing3SourceFixed | 0x00400000, 1694 FMSUB_d = FPDataProcessing3SourceFixed | 0x00408000, 1695 FNMADD_d = FPDataProcessing3SourceFixed | 0x00600000, 1696 FNMSUB_d = FPDataProcessing3SourceFixed | 0x00608000 1697}; 1698 1699// Conversion between floating point and integer. 1700enum FPIntegerConvertOp { 1701 FPIntegerConvertFixed = 0x1E200000, 1702 FPIntegerConvertFMask = 0x5F20FC00, 1703 FPIntegerConvertMask = 0xFFFFFC00, 1704 FCVTNS = FPIntegerConvertFixed | 0x00000000, 1705 FCVTNS_wh = FCVTNS | FP16, 1706 FCVTNS_xh = FCVTNS | SixtyFourBits | FP16, 1707 FCVTNS_ws = FCVTNS, 1708 FCVTNS_xs = FCVTNS | SixtyFourBits, 1709 FCVTNS_wd = FCVTNS | FP64, 1710 FCVTNS_xd = FCVTNS | SixtyFourBits | FP64, 1711 FCVTNU = FPIntegerConvertFixed | 0x00010000, 1712 FCVTNU_wh = FCVTNU | FP16, 1713 FCVTNU_xh = FCVTNU | SixtyFourBits | FP16, 1714 FCVTNU_ws = FCVTNU, 1715 FCVTNU_xs = FCVTNU | SixtyFourBits, 1716 FCVTNU_wd = FCVTNU | FP64, 1717 FCVTNU_xd = FCVTNU | SixtyFourBits | FP64, 1718 FCVTPS = FPIntegerConvertFixed | 0x00080000, 1719 FCVTPS_wh = FCVTPS | FP16, 1720 FCVTPS_xh = FCVTPS | SixtyFourBits | FP16, 1721 FCVTPS_ws = FCVTPS, 1722 FCVTPS_xs = FCVTPS | SixtyFourBits, 1723 FCVTPS_wd = FCVTPS | FP64, 1724 FCVTPS_xd = FCVTPS | SixtyFourBits | FP64, 1725 FCVTPU = FPIntegerConvertFixed | 0x00090000, 1726 FCVTPU_wh = FCVTPU | FP16, 1727 FCVTPU_xh = FCVTPU | SixtyFourBits | FP16, 1728 FCVTPU_ws = FCVTPU, 1729 FCVTPU_xs = FCVTPU | SixtyFourBits, 1730 FCVTPU_wd = FCVTPU | FP64, 1731 FCVTPU_xd = FCVTPU | SixtyFourBits | FP64, 1732 FCVTMS = FPIntegerConvertFixed | 0x00100000, 1733 FCVTMS_wh = FCVTMS | FP16, 1734 FCVTMS_xh = FCVTMS | SixtyFourBits | FP16, 1735 FCVTMS_ws = FCVTMS, 1736 FCVTMS_xs = FCVTMS | SixtyFourBits, 1737 FCVTMS_wd = FCVTMS | FP64, 1738 FCVTMS_xd = FCVTMS | SixtyFourBits | FP64, 1739 FCVTMU = FPIntegerConvertFixed | 0x00110000, 1740 FCVTMU_wh = FCVTMU | FP16, 1741 FCVTMU_xh = FCVTMU | SixtyFourBits | FP16, 1742 FCVTMU_ws = FCVTMU, 1743 FCVTMU_xs = FCVTMU | SixtyFourBits, 1744 FCVTMU_wd = FCVTMU | FP64, 1745 FCVTMU_xd = FCVTMU | SixtyFourBits | FP64, 1746 FCVTZS = FPIntegerConvertFixed | 0x00180000, 1747 FCVTZS_wh = FCVTZS | FP16, 1748 FCVTZS_xh = FCVTZS | SixtyFourBits | FP16, 1749 FCVTZS_ws = FCVTZS, 1750 FCVTZS_xs = FCVTZS | SixtyFourBits, 1751 FCVTZS_wd = FCVTZS | FP64, 1752 FCVTZS_xd = FCVTZS | SixtyFourBits | FP64, 1753 FCVTZU = FPIntegerConvertFixed | 0x00190000, 1754 FCVTZU_wh = FCVTZU | FP16, 1755 FCVTZU_xh = FCVTZU | SixtyFourBits | FP16, 1756 FCVTZU_ws = FCVTZU, 1757 FCVTZU_xs = FCVTZU | SixtyFourBits, 1758 FCVTZU_wd = FCVTZU | FP64, 1759 FCVTZU_xd = FCVTZU | SixtyFourBits | FP64, 1760 SCVTF = FPIntegerConvertFixed | 0x00020000, 1761 SCVTF_hw = SCVTF | FP16, 1762 SCVTF_hx = SCVTF | SixtyFourBits | FP16, 1763 SCVTF_sw = SCVTF, 1764 SCVTF_sx = SCVTF | SixtyFourBits, 1765 SCVTF_dw = SCVTF | FP64, 1766 SCVTF_dx = SCVTF | SixtyFourBits | FP64, 1767 UCVTF = FPIntegerConvertFixed | 0x00030000, 1768 UCVTF_hw = UCVTF | FP16, 1769 UCVTF_hx = UCVTF | SixtyFourBits | FP16, 1770 UCVTF_sw = UCVTF, 1771 UCVTF_sx = UCVTF | SixtyFourBits, 1772 UCVTF_dw = UCVTF | FP64, 1773 UCVTF_dx = UCVTF | SixtyFourBits | FP64, 1774 FCVTAS = FPIntegerConvertFixed | 0x00040000, 1775 FCVTAS_wh = FCVTAS | FP16, 1776 FCVTAS_xh = FCVTAS | SixtyFourBits | FP16, 1777 FCVTAS_ws = FCVTAS, 1778 FCVTAS_xs = FCVTAS | SixtyFourBits, 1779 FCVTAS_wd = FCVTAS | FP64, 1780 FCVTAS_xd = FCVTAS | SixtyFourBits | FP64, 1781 FCVTAU = FPIntegerConvertFixed | 0x00050000, 1782 FCVTAU_wh = FCVTAU | FP16, 1783 FCVTAU_xh = FCVTAU | SixtyFourBits | FP16, 1784 FCVTAU_ws = FCVTAU, 1785 FCVTAU_xs = FCVTAU | SixtyFourBits, 1786 FCVTAU_wd = FCVTAU | FP64, 1787 FCVTAU_xd = FCVTAU | SixtyFourBits | FP64, 1788 FMOV_wh = FPIntegerConvertFixed | 0x00060000 | FP16, 1789 FMOV_hw = FPIntegerConvertFixed | 0x00070000 | FP16, 1790 FMOV_xh = FMOV_wh | SixtyFourBits, 1791 FMOV_hx = FMOV_hw | SixtyFourBits, 1792 FMOV_ws = FPIntegerConvertFixed | 0x00060000, 1793 FMOV_sw = FPIntegerConvertFixed | 0x00070000, 1794 FMOV_xd = FMOV_ws | SixtyFourBits | FP64, 1795 FMOV_dx = FMOV_sw | SixtyFourBits | FP64, 1796 FMOV_d1_x = FPIntegerConvertFixed | SixtyFourBits | 0x008F0000, 1797 FMOV_x_d1 = FPIntegerConvertFixed | SixtyFourBits | 0x008E0000, 1798 FJCVTZS = FPIntegerConvertFixed | FP64 | 0x001E0000 1799}; 1800 1801// Conversion between fixed point and floating point. 1802enum FPFixedPointConvertOp { 1803 FPFixedPointConvertFixed = 0x1E000000, 1804 FPFixedPointConvertFMask = 0x5F200000, 1805 FPFixedPointConvertMask = 0xFFFF0000, 1806 FCVTZS_fixed = FPFixedPointConvertFixed | 0x00180000, 1807 FCVTZS_wh_fixed = FCVTZS_fixed | FP16, 1808 FCVTZS_xh_fixed = FCVTZS_fixed | SixtyFourBits | FP16, 1809 FCVTZS_ws_fixed = FCVTZS_fixed, 1810 FCVTZS_xs_fixed = FCVTZS_fixed | SixtyFourBits, 1811 FCVTZS_wd_fixed = FCVTZS_fixed | FP64, 1812 FCVTZS_xd_fixed = FCVTZS_fixed | SixtyFourBits | FP64, 1813 FCVTZU_fixed = FPFixedPointConvertFixed | 0x00190000, 1814 FCVTZU_wh_fixed = FCVTZU_fixed | FP16, 1815 FCVTZU_xh_fixed = FCVTZU_fixed | SixtyFourBits | FP16, 1816 FCVTZU_ws_fixed = FCVTZU_fixed, 1817 FCVTZU_xs_fixed = FCVTZU_fixed | SixtyFourBits, 1818 FCVTZU_wd_fixed = FCVTZU_fixed | FP64, 1819 FCVTZU_xd_fixed = FCVTZU_fixed | SixtyFourBits | FP64, 1820 SCVTF_fixed = FPFixedPointConvertFixed | 0x00020000, 1821 SCVTF_hw_fixed = SCVTF_fixed | FP16, 1822 SCVTF_hx_fixed = SCVTF_fixed | SixtyFourBits | FP16, 1823 SCVTF_sw_fixed = SCVTF_fixed, 1824 SCVTF_sx_fixed = SCVTF_fixed | SixtyFourBits, 1825 SCVTF_dw_fixed = SCVTF_fixed | FP64, 1826 SCVTF_dx_fixed = SCVTF_fixed | SixtyFourBits | FP64, 1827 UCVTF_fixed = FPFixedPointConvertFixed | 0x00030000, 1828 UCVTF_hw_fixed = UCVTF_fixed | FP16, 1829 UCVTF_hx_fixed = UCVTF_fixed | SixtyFourBits | FP16, 1830 UCVTF_sw_fixed = UCVTF_fixed, 1831 UCVTF_sx_fixed = UCVTF_fixed | SixtyFourBits, 1832 UCVTF_dw_fixed = UCVTF_fixed | FP64, 1833 UCVTF_dx_fixed = UCVTF_fixed | SixtyFourBits | FP64 1834}; 1835 1836// Crypto - two register SHA. 1837enum Crypto2RegSHAOp { 1838 Crypto2RegSHAFixed = 0x5E280800, 1839 Crypto2RegSHAFMask = 0xFF3E0C00 1840}; 1841 1842// Crypto - three register SHA. 1843enum Crypto3RegSHAOp { 1844 Crypto3RegSHAFixed = 0x5E000000, 1845 Crypto3RegSHAFMask = 0xFF208C00 1846}; 1847 1848// Crypto - AES. 1849enum CryptoAESOp { 1850 CryptoAESFixed = 0x4E280800, 1851 CryptoAESFMask = 0xFF3E0C00 1852}; 1853 1854// NEON instructions with two register operands. 1855enum NEON2RegMiscOp { 1856 NEON2RegMiscFixed = 0x0E200800, 1857 NEON2RegMiscFMask = 0x9F3E0C00, 1858 NEON2RegMiscMask = 0xBF3FFC00, 1859 NEON2RegMiscUBit = 0x20000000, 1860 NEON_REV64 = NEON2RegMiscFixed | 0x00000000, 1861 NEON_REV32 = NEON2RegMiscFixed | 0x20000000, 1862 NEON_REV16 = NEON2RegMiscFixed | 0x00001000, 1863 NEON_SADDLP = NEON2RegMiscFixed | 0x00002000, 1864 NEON_UADDLP = NEON_SADDLP | NEON2RegMiscUBit, 1865 NEON_SUQADD = NEON2RegMiscFixed | 0x00003000, 1866 NEON_USQADD = NEON_SUQADD | NEON2RegMiscUBit, 1867 NEON_CLS = NEON2RegMiscFixed | 0x00004000, 1868 NEON_CLZ = NEON2RegMiscFixed | 0x20004000, 1869 NEON_CNT = NEON2RegMiscFixed | 0x00005000, 1870 NEON_RBIT_NOT = NEON2RegMiscFixed | 0x20005000, 1871 NEON_SADALP = NEON2RegMiscFixed | 0x00006000, 1872 NEON_UADALP = NEON_SADALP | NEON2RegMiscUBit, 1873 NEON_SQABS = NEON2RegMiscFixed | 0x00007000, 1874 NEON_SQNEG = NEON2RegMiscFixed | 0x20007000, 1875 NEON_CMGT_zero = NEON2RegMiscFixed | 0x00008000, 1876 NEON_CMGE_zero = NEON2RegMiscFixed | 0x20008000, 1877 NEON_CMEQ_zero = NEON2RegMiscFixed | 0x00009000, 1878 NEON_CMLE_zero = NEON2RegMiscFixed | 0x20009000, 1879 NEON_CMLT_zero = NEON2RegMiscFixed | 0x0000A000, 1880 NEON_ABS = NEON2RegMiscFixed | 0x0000B000, 1881 NEON_NEG = NEON2RegMiscFixed | 0x2000B000, 1882 NEON_XTN = NEON2RegMiscFixed | 0x00012000, 1883 NEON_SQXTUN = NEON2RegMiscFixed | 0x20012000, 1884 NEON_SHLL = NEON2RegMiscFixed | 0x20013000, 1885 NEON_SQXTN = NEON2RegMiscFixed | 0x00014000, 1886 NEON_UQXTN = NEON_SQXTN | NEON2RegMiscUBit, 1887 1888 NEON2RegMiscOpcode = 0x0001F000, 1889 NEON_RBIT_NOT_opcode = NEON_RBIT_NOT & NEON2RegMiscOpcode, 1890 NEON_NEG_opcode = NEON_NEG & NEON2RegMiscOpcode, 1891 NEON_XTN_opcode = NEON_XTN & NEON2RegMiscOpcode, 1892 NEON_UQXTN_opcode = NEON_UQXTN & NEON2RegMiscOpcode, 1893 1894 // These instructions use only one bit of the size field. The other bit is 1895 // used to distinguish between instructions. 1896 NEON2RegMiscFPMask = NEON2RegMiscMask | 0x00800000, 1897 NEON_FABS = NEON2RegMiscFixed | 0x0080F000, 1898 NEON_FNEG = NEON2RegMiscFixed | 0x2080F000, 1899 NEON_FCVTN = NEON2RegMiscFixed | 0x00016000, 1900 NEON_FCVTXN = NEON2RegMiscFixed | 0x20016000, 1901 NEON_FCVTL = NEON2RegMiscFixed | 0x00017000, 1902 NEON_FRINT32X = NEON2RegMiscFixed | 0x2001E000, 1903 NEON_FRINT32Z = NEON2RegMiscFixed | 0x0001E000, 1904 NEON_FRINT64X = NEON2RegMiscFixed | 0x2001F000, 1905 NEON_FRINT64Z = NEON2RegMiscFixed | 0x0001F000, 1906 NEON_FRINTN = NEON2RegMiscFixed | 0x00018000, 1907 NEON_FRINTA = NEON2RegMiscFixed | 0x20018000, 1908 NEON_FRINTP = NEON2RegMiscFixed | 0x00818000, 1909 NEON_FRINTM = NEON2RegMiscFixed | 0x00019000, 1910 NEON_FRINTX = NEON2RegMiscFixed | 0x20019000, 1911 NEON_FRINTZ = NEON2RegMiscFixed | 0x00819000, 1912 NEON_FRINTI = NEON2RegMiscFixed | 0x20819000, 1913 NEON_FCVTNS = NEON2RegMiscFixed | 0x0001A000, 1914 NEON_FCVTNU = NEON_FCVTNS | NEON2RegMiscUBit, 1915 NEON_FCVTPS = NEON2RegMiscFixed | 0x0081A000, 1916 NEON_FCVTPU = NEON_FCVTPS | NEON2RegMiscUBit, 1917 NEON_FCVTMS = NEON2RegMiscFixed | 0x0001B000, 1918 NEON_FCVTMU = NEON_FCVTMS | NEON2RegMiscUBit, 1919 NEON_FCVTZS = NEON2RegMiscFixed | 0x0081B000, 1920 NEON_FCVTZU = NEON_FCVTZS | NEON2RegMiscUBit, 1921 NEON_FCVTAS = NEON2RegMiscFixed | 0x0001C000, 1922 NEON_FCVTAU = NEON_FCVTAS | NEON2RegMiscUBit, 1923 NEON_FSQRT = NEON2RegMiscFixed | 0x2081F000, 1924 NEON_SCVTF = NEON2RegMiscFixed | 0x0001D000, 1925 NEON_UCVTF = NEON_SCVTF | NEON2RegMiscUBit, 1926 NEON_URSQRTE = NEON2RegMiscFixed | 0x2081C000, 1927 NEON_URECPE = NEON2RegMiscFixed | 0x0081C000, 1928 NEON_FRSQRTE = NEON2RegMiscFixed | 0x2081D000, 1929 NEON_FRECPE = NEON2RegMiscFixed | 0x0081D000, 1930 NEON_FCMGT_zero = NEON2RegMiscFixed | 0x0080C000, 1931 NEON_FCMGE_zero = NEON2RegMiscFixed | 0x2080C000, 1932 NEON_FCMEQ_zero = NEON2RegMiscFixed | 0x0080D000, 1933 NEON_FCMLE_zero = NEON2RegMiscFixed | 0x2080D000, 1934 NEON_FCMLT_zero = NEON2RegMiscFixed | 0x0080E000, 1935 1936 NEON_FCVTL_opcode = NEON_FCVTL & NEON2RegMiscOpcode, 1937 NEON_FCVTN_opcode = NEON_FCVTN & NEON2RegMiscOpcode 1938}; 1939 1940// NEON instructions with two register operands (FP16). 1941enum NEON2RegMiscFP16Op { 1942 NEON2RegMiscFP16Fixed = 0x0E780800, 1943 NEON2RegMiscFP16FMask = 0x9F7E0C00, 1944 NEON2RegMiscFP16Mask = 0xBFFFFC00, 1945 NEON_FRINTN_H = NEON2RegMiscFP16Fixed | 0x00018000, 1946 NEON_FRINTM_H = NEON2RegMiscFP16Fixed | 0x00019000, 1947 NEON_FCVTNS_H = NEON2RegMiscFP16Fixed | 0x0001A000, 1948 NEON_FCVTMS_H = NEON2RegMiscFP16Fixed | 0x0001B000, 1949 NEON_FCVTAS_H = NEON2RegMiscFP16Fixed | 0x0001C000, 1950 NEON_SCVTF_H = NEON2RegMiscFP16Fixed | 0x0001D000, 1951 NEON_FCMGT_H_zero = NEON2RegMiscFP16Fixed | 0x0080C000, 1952 NEON_FCMEQ_H_zero = NEON2RegMiscFP16Fixed | 0x0080D000, 1953 NEON_FCMLT_H_zero = NEON2RegMiscFP16Fixed | 0x0080E000, 1954 NEON_FABS_H = NEON2RegMiscFP16Fixed | 0x0080F000, 1955 NEON_FRINTP_H = NEON2RegMiscFP16Fixed | 0x00818000, 1956 NEON_FRINTZ_H = NEON2RegMiscFP16Fixed | 0x00819000, 1957 NEON_FCVTPS_H = NEON2RegMiscFP16Fixed | 0x0081A000, 1958 NEON_FCVTZS_H = NEON2RegMiscFP16Fixed | 0x0081B000, 1959 NEON_FRECPE_H = NEON2RegMiscFP16Fixed | 0x0081D000, 1960 NEON_FRINTA_H = NEON2RegMiscFP16Fixed | 0x20018000, 1961 NEON_FRINTX_H = NEON2RegMiscFP16Fixed | 0x20019000, 1962 NEON_FCVTNU_H = NEON2RegMiscFP16Fixed | 0x2001A000, 1963 NEON_FCVTMU_H = NEON2RegMiscFP16Fixed | 0x2001B000, 1964 NEON_FCVTAU_H = NEON2RegMiscFP16Fixed | 0x2001C000, 1965 NEON_UCVTF_H = NEON2RegMiscFP16Fixed | 0x2001D000, 1966 NEON_FCMGE_H_zero = NEON2RegMiscFP16Fixed | 0x2080C000, 1967 NEON_FCMLE_H_zero = NEON2RegMiscFP16Fixed | 0x2080D000, 1968 NEON_FNEG_H = NEON2RegMiscFP16Fixed | 0x2080F000, 1969 NEON_FRINTI_H = NEON2RegMiscFP16Fixed | 0x20819000, 1970 NEON_FCVTPU_H = NEON2RegMiscFP16Fixed | 0x2081A000, 1971 NEON_FCVTZU_H = NEON2RegMiscFP16Fixed | 0x2081B000, 1972 NEON_FRSQRTE_H = NEON2RegMiscFP16Fixed | 0x2081D000, 1973 NEON_FSQRT_H = NEON2RegMiscFP16Fixed | 0x2081F000 1974}; 1975 1976// NEON instructions with three same-type operands. 1977enum NEON3SameOp { 1978 NEON3SameFixed = 0x0E200400, 1979 NEON3SameFMask = 0x9F200400, 1980 NEON3SameMask = 0xBF20FC00, 1981 NEON3SameUBit = 0x20000000, 1982 NEON_ADD = NEON3SameFixed | 0x00008000, 1983 NEON_ADDP = NEON3SameFixed | 0x0000B800, 1984 NEON_SHADD = NEON3SameFixed | 0x00000000, 1985 NEON_SHSUB = NEON3SameFixed | 0x00002000, 1986 NEON_SRHADD = NEON3SameFixed | 0x00001000, 1987 NEON_CMEQ = NEON3SameFixed | NEON3SameUBit | 0x00008800, 1988 NEON_CMGE = NEON3SameFixed | 0x00003800, 1989 NEON_CMGT = NEON3SameFixed | 0x00003000, 1990 NEON_CMHI = NEON3SameFixed | NEON3SameUBit | NEON_CMGT, 1991 NEON_CMHS = NEON3SameFixed | NEON3SameUBit | NEON_CMGE, 1992 NEON_CMTST = NEON3SameFixed | 0x00008800, 1993 NEON_MLA = NEON3SameFixed | 0x00009000, 1994 NEON_MLS = NEON3SameFixed | 0x20009000, 1995 NEON_MUL = NEON3SameFixed | 0x00009800, 1996 NEON_PMUL = NEON3SameFixed | 0x20009800, 1997 NEON_SRSHL = NEON3SameFixed | 0x00005000, 1998 NEON_SQSHL = NEON3SameFixed | 0x00004800, 1999 NEON_SQRSHL = NEON3SameFixed | 0x00005800, 2000 NEON_SSHL = NEON3SameFixed | 0x00004000, 2001 NEON_SMAX = NEON3SameFixed | 0x00006000, 2002 NEON_SMAXP = NEON3SameFixed | 0x0000A000, 2003 NEON_SMIN = NEON3SameFixed | 0x00006800, 2004 NEON_SMINP = NEON3SameFixed | 0x0000A800, 2005 NEON_SABD = NEON3SameFixed | 0x00007000, 2006 NEON_SABA = NEON3SameFixed | 0x00007800, 2007 NEON_UABD = NEON3SameFixed | NEON3SameUBit | NEON_SABD, 2008 NEON_UABA = NEON3SameFixed | NEON3SameUBit | NEON_SABA, 2009 NEON_SQADD = NEON3SameFixed | 0x00000800, 2010 NEON_SQSUB = NEON3SameFixed | 0x00002800, 2011 NEON_SUB = NEON3SameFixed | NEON3SameUBit | 0x00008000, 2012 NEON_UHADD = NEON3SameFixed | NEON3SameUBit | NEON_SHADD, 2013 NEON_UHSUB = NEON3SameFixed | NEON3SameUBit | NEON_SHSUB, 2014 NEON_URHADD = NEON3SameFixed | NEON3SameUBit | NEON_SRHADD, 2015 NEON_UMAX = NEON3SameFixed | NEON3SameUBit | NEON_SMAX, 2016 NEON_UMAXP = NEON3SameFixed | NEON3SameUBit | NEON_SMAXP, 2017 NEON_UMIN = NEON3SameFixed | NEON3SameUBit | NEON_SMIN, 2018 NEON_UMINP = NEON3SameFixed | NEON3SameUBit | NEON_SMINP, 2019 NEON_URSHL = NEON3SameFixed | NEON3SameUBit | NEON_SRSHL, 2020 NEON_UQADD = NEON3SameFixed | NEON3SameUBit | NEON_SQADD, 2021 NEON_UQRSHL = NEON3SameFixed | NEON3SameUBit | NEON_SQRSHL, 2022 NEON_UQSHL = NEON3SameFixed | NEON3SameUBit | NEON_SQSHL, 2023 NEON_UQSUB = NEON3SameFixed | NEON3SameUBit | NEON_SQSUB, 2024 NEON_USHL = NEON3SameFixed | NEON3SameUBit | NEON_SSHL, 2025 NEON_SQDMULH = NEON3SameFixed | 0x0000B000, 2026 NEON_SQRDMULH = NEON3SameFixed | 0x2000B000, 2027 2028 // NEON floating point instructions with three same-type operands. 2029 NEON3SameFPFixed = NEON3SameFixed | 0x0000C000, 2030 NEON3SameFPFMask = NEON3SameFMask | 0x0000C000, 2031 NEON3SameFPMask = NEON3SameMask | 0x00800000, 2032 NEON_FADD = NEON3SameFixed | 0x0000D000, 2033 NEON_FSUB = NEON3SameFixed | 0x0080D000, 2034 NEON_FMUL = NEON3SameFixed | 0x2000D800, 2035 NEON_FDIV = NEON3SameFixed | 0x2000F800, 2036 NEON_FMAX = NEON3SameFixed | 0x0000F000, 2037 NEON_FMAXNM = NEON3SameFixed | 0x0000C000, 2038 NEON_FMAXP = NEON3SameFixed | 0x2000F000, 2039 NEON_FMAXNMP = NEON3SameFixed | 0x2000C000, 2040 NEON_FMIN = NEON3SameFixed | 0x0080F000, 2041 NEON_FMINNM = NEON3SameFixed | 0x0080C000, 2042 NEON_FMINP = NEON3SameFixed | 0x2080F000, 2043 NEON_FMINNMP = NEON3SameFixed | 0x2080C000, 2044 NEON_FMLA = NEON3SameFixed | 0x0000C800, 2045 NEON_FMLS = NEON3SameFixed | 0x0080C800, 2046 NEON_FMULX = NEON3SameFixed | 0x0000D800, 2047 NEON_FRECPS = NEON3SameFixed | 0x0000F800, 2048 NEON_FRSQRTS = NEON3SameFixed | 0x0080F800, 2049 NEON_FABD = NEON3SameFixed | 0x2080D000, 2050 NEON_FADDP = NEON3SameFixed | 0x2000D000, 2051 NEON_FCMEQ = NEON3SameFixed | 0x0000E000, 2052 NEON_FCMGE = NEON3SameFixed | 0x2000E000, 2053 NEON_FCMGT = NEON3SameFixed | 0x2080E000, 2054 NEON_FACGE = NEON3SameFixed | 0x2000E800, 2055 NEON_FACGT = NEON3SameFixed | 0x2080E800, 2056 2057 // NEON logical instructions with three same-type operands. 2058 NEON3SameLogicalFixed = NEON3SameFixed | 0x00001800, 2059 NEON3SameLogicalFMask = NEON3SameFMask | 0x0000F800, 2060 NEON3SameLogicalMask = 0xBFE0FC00, 2061 NEON3SameLogicalFormatMask = NEON_Q, 2062 NEON_AND = NEON3SameLogicalFixed | 0x00000000, 2063 NEON_ORR = NEON3SameLogicalFixed | 0x00A00000, 2064 NEON_ORN = NEON3SameLogicalFixed | 0x00C00000, 2065 NEON_EOR = NEON3SameLogicalFixed | 0x20000000, 2066 NEON_BIC = NEON3SameLogicalFixed | 0x00400000, 2067 NEON_BIF = NEON3SameLogicalFixed | 0x20C00000, 2068 NEON_BIT = NEON3SameLogicalFixed | 0x20800000, 2069 NEON_BSL = NEON3SameLogicalFixed | 0x20400000, 2070 2071 // FHM (FMLAL-like) instructions have an oddball encoding scheme under 3Same. 2072 NEON3SameFHMMask = 0xBFE0FC00, // U size opcode 2073 NEON_FMLAL = NEON3SameFixed | 0x0000E800, // 0 00 11101 2074 NEON_FMLAL2 = NEON3SameFixed | 0x2000C800, // 1 00 11001 2075 NEON_FMLSL = NEON3SameFixed | 0x0080E800, // 0 10 11101 2076 NEON_FMLSL2 = NEON3SameFixed | 0x2080C800 // 1 10 11001 2077}; 2078 2079 2080enum NEON3SameFP16 { 2081 NEON3SameFP16Fixed = 0x0E400400, 2082 NEON3SameFP16FMask = 0x9F60C400, 2083 NEON3SameFP16Mask = 0xBFE0FC00, 2084 NEON_FMAXNM_H = NEON3SameFP16Fixed | 0x00000000, 2085 NEON_FMLA_H = NEON3SameFP16Fixed | 0x00000800, 2086 NEON_FADD_H = NEON3SameFP16Fixed | 0x00001000, 2087 NEON_FMULX_H = NEON3SameFP16Fixed | 0x00001800, 2088 NEON_FCMEQ_H = NEON3SameFP16Fixed | 0x00002000, 2089 NEON_FMAX_H = NEON3SameFP16Fixed | 0x00003000, 2090 NEON_FRECPS_H = NEON3SameFP16Fixed | 0x00003800, 2091 NEON_FMINNM_H = NEON3SameFP16Fixed | 0x00800000, 2092 NEON_FMLS_H = NEON3SameFP16Fixed | 0x00800800, 2093 NEON_FSUB_H = NEON3SameFP16Fixed | 0x00801000, 2094 NEON_FMIN_H = NEON3SameFP16Fixed | 0x00803000, 2095 NEON_FRSQRTS_H = NEON3SameFP16Fixed | 0x00803800, 2096 NEON_FMAXNMP_H = NEON3SameFP16Fixed | 0x20000000, 2097 NEON_FADDP_H = NEON3SameFP16Fixed | 0x20001000, 2098 NEON_FMUL_H = NEON3SameFP16Fixed | 0x20001800, 2099 NEON_FCMGE_H = NEON3SameFP16Fixed | 0x20002000, 2100 NEON_FACGE_H = NEON3SameFP16Fixed | 0x20002800, 2101 NEON_FMAXP_H = NEON3SameFP16Fixed | 0x20003000, 2102 NEON_FDIV_H = NEON3SameFP16Fixed | 0x20003800, 2103 NEON_FMINNMP_H = NEON3SameFP16Fixed | 0x20800000, 2104 NEON_FABD_H = NEON3SameFP16Fixed | 0x20801000, 2105 NEON_FCMGT_H = NEON3SameFP16Fixed | 0x20802000, 2106 NEON_FACGT_H = NEON3SameFP16Fixed | 0x20802800, 2107 NEON_FMINP_H = NEON3SameFP16Fixed | 0x20803000 2108}; 2109 2110 2111// 'Extra' NEON instructions with three same-type operands. 2112enum NEON3SameExtraOp { 2113 NEON3SameExtraFixed = 0x0E008400, 2114 NEON3SameExtraUBit = 0x20000000, 2115 NEON3SameExtraFMask = 0x9E208400, 2116 NEON3SameExtraMask = 0xBE20FC00, 2117 NEON_SQRDMLAH = NEON3SameExtraFixed | NEON3SameExtraUBit, 2118 NEON_SQRDMLSH = NEON3SameExtraFixed | NEON3SameExtraUBit | 0x00000800, 2119 NEON_SDOT = NEON3SameExtraFixed | 0x00001000, 2120 NEON_UDOT = NEON3SameExtraFixed | NEON3SameExtraUBit | 0x00001000, 2121 2122 /* v8.3 Complex Numbers */ 2123 NEON3SameExtraFCFixed = 0x2E00C400, 2124 NEON3SameExtraFCFMask = 0xBF20C400, 2125 // FCMLA fixes opcode<3:2>, and uses opcode<1:0> to encode <rotate>. 2126 NEON3SameExtraFCMLAMask = NEON3SameExtraFCFMask | 0x00006000, 2127 NEON_FCMLA = NEON3SameExtraFCFixed, 2128 // FCADD fixes opcode<3:2, 0>, and uses opcode<1> to encode <rotate>. 2129 NEON3SameExtraFCADDMask = NEON3SameExtraFCFMask | 0x00006800, 2130 NEON_FCADD = NEON3SameExtraFCFixed | 0x00002000 2131 // Other encodings under NEON3SameExtraFCFMask are UNALLOCATED. 2132}; 2133 2134// NEON instructions with three different-type operands. 2135enum NEON3DifferentOp { 2136 NEON3DifferentFixed = 0x0E200000, 2137 NEON3DifferentFMask = 0x9F200C00, 2138 NEON3DifferentMask = 0xFF20FC00, 2139 NEON_ADDHN = NEON3DifferentFixed | 0x00004000, 2140 NEON_ADDHN2 = NEON_ADDHN | NEON_Q, 2141 NEON_PMULL = NEON3DifferentFixed | 0x0000E000, 2142 NEON_PMULL2 = NEON_PMULL | NEON_Q, 2143 NEON_RADDHN = NEON3DifferentFixed | 0x20004000, 2144 NEON_RADDHN2 = NEON_RADDHN | NEON_Q, 2145 NEON_RSUBHN = NEON3DifferentFixed | 0x20006000, 2146 NEON_RSUBHN2 = NEON_RSUBHN | NEON_Q, 2147 NEON_SABAL = NEON3DifferentFixed | 0x00005000, 2148 NEON_SABAL2 = NEON_SABAL | NEON_Q, 2149 NEON_SABDL = NEON3DifferentFixed | 0x00007000, 2150 NEON_SABDL2 = NEON_SABDL | NEON_Q, 2151 NEON_SADDL = NEON3DifferentFixed | 0x00000000, 2152 NEON_SADDL2 = NEON_SADDL | NEON_Q, 2153 NEON_SADDW = NEON3DifferentFixed | 0x00001000, 2154 NEON_SADDW2 = NEON_SADDW | NEON_Q, 2155 NEON_SMLAL = NEON3DifferentFixed | 0x00008000, 2156 NEON_SMLAL2 = NEON_SMLAL | NEON_Q, 2157 NEON_SMLSL = NEON3DifferentFixed | 0x0000A000, 2158 NEON_SMLSL2 = NEON_SMLSL | NEON_Q, 2159 NEON_SMULL = NEON3DifferentFixed | 0x0000C000, 2160 NEON_SMULL2 = NEON_SMULL | NEON_Q, 2161 NEON_SSUBL = NEON3DifferentFixed | 0x00002000, 2162 NEON_SSUBL2 = NEON_SSUBL | NEON_Q, 2163 NEON_SSUBW = NEON3DifferentFixed | 0x00003000, 2164 NEON_SSUBW2 = NEON_SSUBW | NEON_Q, 2165 NEON_SQDMLAL = NEON3DifferentFixed | 0x00009000, 2166 NEON_SQDMLAL2 = NEON_SQDMLAL | NEON_Q, 2167 NEON_SQDMLSL = NEON3DifferentFixed | 0x0000B000, 2168 NEON_SQDMLSL2 = NEON_SQDMLSL | NEON_Q, 2169 NEON_SQDMULL = NEON3DifferentFixed | 0x0000D000, 2170 NEON_SQDMULL2 = NEON_SQDMULL | NEON_Q, 2171 NEON_SUBHN = NEON3DifferentFixed | 0x00006000, 2172 NEON_SUBHN2 = NEON_SUBHN | NEON_Q, 2173 NEON_UABAL = NEON_SABAL | NEON3SameUBit, 2174 NEON_UABAL2 = NEON_UABAL | NEON_Q, 2175 NEON_UABDL = NEON_SABDL | NEON3SameUBit, 2176 NEON_UABDL2 = NEON_UABDL | NEON_Q, 2177 NEON_UADDL = NEON_SADDL | NEON3SameUBit, 2178 NEON_UADDL2 = NEON_UADDL | NEON_Q, 2179 NEON_UADDW = NEON_SADDW | NEON3SameUBit, 2180 NEON_UADDW2 = NEON_UADDW | NEON_Q, 2181 NEON_UMLAL = NEON_SMLAL | NEON3SameUBit, 2182 NEON_UMLAL2 = NEON_UMLAL | NEON_Q, 2183 NEON_UMLSL = NEON_SMLSL | NEON3SameUBit, 2184 NEON_UMLSL2 = NEON_UMLSL | NEON_Q, 2185 NEON_UMULL = NEON_SMULL | NEON3SameUBit, 2186 NEON_UMULL2 = NEON_UMULL | NEON_Q, 2187 NEON_USUBL = NEON_SSUBL | NEON3SameUBit, 2188 NEON_USUBL2 = NEON_USUBL | NEON_Q, 2189 NEON_USUBW = NEON_SSUBW | NEON3SameUBit, 2190 NEON_USUBW2 = NEON_USUBW | NEON_Q 2191}; 2192 2193// NEON instructions operating across vectors. 2194enum NEONAcrossLanesOp { 2195 NEONAcrossLanesFixed = 0x0E300800, 2196 NEONAcrossLanesFMask = 0x9F3E0C00, 2197 NEONAcrossLanesMask = 0xBF3FFC00, 2198 NEON_ADDV = NEONAcrossLanesFixed | 0x0001B000, 2199 NEON_SADDLV = NEONAcrossLanesFixed | 0x00003000, 2200 NEON_UADDLV = NEONAcrossLanesFixed | 0x20003000, 2201 NEON_SMAXV = NEONAcrossLanesFixed | 0x0000A000, 2202 NEON_SMINV = NEONAcrossLanesFixed | 0x0001A000, 2203 NEON_UMAXV = NEONAcrossLanesFixed | 0x2000A000, 2204 NEON_UMINV = NEONAcrossLanesFixed | 0x2001A000, 2205 2206 NEONAcrossLanesFP16Fixed = NEONAcrossLanesFixed | 0x0000C000, 2207 NEONAcrossLanesFP16FMask = NEONAcrossLanesFMask | 0x2000C000, 2208 NEONAcrossLanesFP16Mask = NEONAcrossLanesMask | 0x20800000, 2209 NEON_FMAXNMV_H = NEONAcrossLanesFP16Fixed | 0x00000000, 2210 NEON_FMAXV_H = NEONAcrossLanesFP16Fixed | 0x00003000, 2211 NEON_FMINNMV_H = NEONAcrossLanesFP16Fixed | 0x00800000, 2212 NEON_FMINV_H = NEONAcrossLanesFP16Fixed | 0x00803000, 2213 2214 // NEON floating point across instructions. 2215 NEONAcrossLanesFPFixed = NEONAcrossLanesFixed | 0x2000C000, 2216 NEONAcrossLanesFPFMask = NEONAcrossLanesFMask | 0x2000C000, 2217 NEONAcrossLanesFPMask = NEONAcrossLanesMask | 0x20800000, 2218 2219 NEON_FMAXV = NEONAcrossLanesFPFixed | 0x2000F000, 2220 NEON_FMINV = NEONAcrossLanesFPFixed | 0x2080F000, 2221 NEON_FMAXNMV = NEONAcrossLanesFPFixed | 0x2000C000, 2222 NEON_FMINNMV = NEONAcrossLanesFPFixed | 0x2080C000 2223}; 2224 2225// NEON instructions with indexed element operand. 2226enum NEONByIndexedElementOp { 2227 NEONByIndexedElementFixed = 0x0F000000, 2228 NEONByIndexedElementFMask = 0x9F000400, 2229 NEONByIndexedElementMask = 0xBF00F400, 2230 NEON_MUL_byelement = NEONByIndexedElementFixed | 0x00008000, 2231 NEON_MLA_byelement = NEONByIndexedElementFixed | 0x20000000, 2232 NEON_MLS_byelement = NEONByIndexedElementFixed | 0x20004000, 2233 NEON_SMULL_byelement = NEONByIndexedElementFixed | 0x0000A000, 2234 NEON_SMLAL_byelement = NEONByIndexedElementFixed | 0x00002000, 2235 NEON_SMLSL_byelement = NEONByIndexedElementFixed | 0x00006000, 2236 NEON_UMULL_byelement = NEONByIndexedElementFixed | 0x2000A000, 2237 NEON_UMLAL_byelement = NEONByIndexedElementFixed | 0x20002000, 2238 NEON_UMLSL_byelement = NEONByIndexedElementFixed | 0x20006000, 2239 NEON_SQDMULL_byelement = NEONByIndexedElementFixed | 0x0000B000, 2240 NEON_SQDMLAL_byelement = NEONByIndexedElementFixed | 0x00003000, 2241 NEON_SQDMLSL_byelement = NEONByIndexedElementFixed | 0x00007000, 2242 NEON_SQDMULH_byelement = NEONByIndexedElementFixed | 0x0000C000, 2243 NEON_SQRDMULH_byelement = NEONByIndexedElementFixed | 0x0000D000, 2244 NEON_SDOT_byelement = NEONByIndexedElementFixed | 0x0000E000, 2245 NEON_SQRDMLAH_byelement = NEONByIndexedElementFixed | 0x2000D000, 2246 NEON_UDOT_byelement = NEONByIndexedElementFixed | 0x2000E000, 2247 NEON_SQRDMLSH_byelement = NEONByIndexedElementFixed | 0x2000F000, 2248 2249 NEON_FMLA_H_byelement = NEONByIndexedElementFixed | 0x00001000, 2250 NEON_FMLS_H_byelement = NEONByIndexedElementFixed | 0x00005000, 2251 NEON_FMUL_H_byelement = NEONByIndexedElementFixed | 0x00009000, 2252 NEON_FMULX_H_byelement = NEONByIndexedElementFixed | 0x20009000, 2253 2254 // Floating point instructions. 2255 NEONByIndexedElementFPFixed = NEONByIndexedElementFixed | 0x00800000, 2256 NEONByIndexedElementFPMask = NEONByIndexedElementMask | 0x00800000, 2257 NEON_FMLA_byelement = NEONByIndexedElementFPFixed | 0x00001000, 2258 NEON_FMLS_byelement = NEONByIndexedElementFPFixed | 0x00005000, 2259 NEON_FMUL_byelement = NEONByIndexedElementFPFixed | 0x00009000, 2260 NEON_FMULX_byelement = NEONByIndexedElementFPFixed | 0x20009000, 2261 2262 // FMLAL-like instructions. 2263 // For all cases: U = x, size = 10, opcode = xx00 2264 NEONByIndexedElementFPLongFixed = NEONByIndexedElementFixed | 0x00800000, 2265 NEONByIndexedElementFPLongFMask = NEONByIndexedElementFMask | 0x00C03000, 2266 NEONByIndexedElementFPLongMask = 0xBFC0F400, 2267 NEON_FMLAL_H_byelement = NEONByIndexedElementFixed | 0x00800000, 2268 NEON_FMLAL2_H_byelement = NEONByIndexedElementFixed | 0x20808000, 2269 NEON_FMLSL_H_byelement = NEONByIndexedElementFixed | 0x00804000, 2270 NEON_FMLSL2_H_byelement = NEONByIndexedElementFixed | 0x2080C000, 2271 2272 // Complex instruction(s). 2273 // This is necessary because the 'rot' encoding moves into the 2274 // NEONByIndex..Mask space. 2275 NEONByIndexedElementFPComplexMask = 0xBF009400, 2276 NEON_FCMLA_byelement = NEONByIndexedElementFixed | 0x20001000 2277}; 2278 2279// NEON register copy. 2280enum NEONCopyOp { 2281 NEONCopyFixed = 0x0E000400, 2282 NEONCopyFMask = 0x9FE08400, 2283 NEONCopyMask = 0x3FE08400, 2284 NEONCopyInsElementMask = NEONCopyMask | 0x40000000, 2285 NEONCopyInsGeneralMask = NEONCopyMask | 0x40007800, 2286 NEONCopyDupElementMask = NEONCopyMask | 0x20007800, 2287 NEONCopyDupGeneralMask = NEONCopyDupElementMask, 2288 NEONCopyUmovMask = NEONCopyMask | 0x20007800, 2289 NEONCopySmovMask = NEONCopyMask | 0x20007800, 2290 NEON_INS_ELEMENT = NEONCopyFixed | 0x60000000, 2291 NEON_INS_GENERAL = NEONCopyFixed | 0x40001800, 2292 NEON_DUP_ELEMENT = NEONCopyFixed | 0x00000000, 2293 NEON_DUP_GENERAL = NEONCopyFixed | 0x00000800, 2294 NEON_SMOV = NEONCopyFixed | 0x00002800, 2295 NEON_UMOV = NEONCopyFixed | 0x00003800 2296}; 2297 2298// NEON extract. 2299enum NEONExtractOp { 2300 NEONExtractFixed = 0x2E000000, 2301 NEONExtractFMask = 0xBF208400, 2302 NEONExtractMask = 0xBFE08400, 2303 NEON_EXT = NEONExtractFixed | 0x00000000 2304}; 2305 2306enum NEONLoadStoreMultiOp { 2307 NEONLoadStoreMultiL = 0x00400000, 2308 NEONLoadStoreMulti1_1v = 0x00007000, 2309 NEONLoadStoreMulti1_2v = 0x0000A000, 2310 NEONLoadStoreMulti1_3v = 0x00006000, 2311 NEONLoadStoreMulti1_4v = 0x00002000, 2312 NEONLoadStoreMulti2 = 0x00008000, 2313 NEONLoadStoreMulti3 = 0x00004000, 2314 NEONLoadStoreMulti4 = 0x00000000 2315}; 2316 2317// NEON load/store multiple structures. 2318enum NEONLoadStoreMultiStructOp { 2319 NEONLoadStoreMultiStructFixed = 0x0C000000, 2320 NEONLoadStoreMultiStructFMask = 0xBFBF0000, 2321 NEONLoadStoreMultiStructMask = 0xBFFFF000, 2322 NEONLoadStoreMultiStructStore = NEONLoadStoreMultiStructFixed, 2323 NEONLoadStoreMultiStructLoad = NEONLoadStoreMultiStructFixed | 2324 NEONLoadStoreMultiL, 2325 NEON_LD1_1v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_1v, 2326 NEON_LD1_2v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_2v, 2327 NEON_LD1_3v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_3v, 2328 NEON_LD1_4v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_4v, 2329 NEON_LD2 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti2, 2330 NEON_LD3 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti3, 2331 NEON_LD4 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti4, 2332 NEON_ST1_1v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_1v, 2333 NEON_ST1_2v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_2v, 2334 NEON_ST1_3v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_3v, 2335 NEON_ST1_4v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_4v, 2336 NEON_ST2 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti2, 2337 NEON_ST3 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti3, 2338 NEON_ST4 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti4 2339}; 2340 2341// NEON load/store multiple structures with post-index addressing. 2342enum NEONLoadStoreMultiStructPostIndexOp { 2343 NEONLoadStoreMultiStructPostIndexFixed = 0x0C800000, 2344 NEONLoadStoreMultiStructPostIndexFMask = 0xBFA00000, 2345 NEONLoadStoreMultiStructPostIndexMask = 0xBFE0F000, 2346 NEONLoadStoreMultiStructPostIndex = 0x00800000, 2347 NEON_LD1_1v_post = NEON_LD1_1v | NEONLoadStoreMultiStructPostIndex, 2348 NEON_LD1_2v_post = NEON_LD1_2v | NEONLoadStoreMultiStructPostIndex, 2349 NEON_LD1_3v_post = NEON_LD1_3v | NEONLoadStoreMultiStructPostIndex, 2350 NEON_LD1_4v_post = NEON_LD1_4v | NEONLoadStoreMultiStructPostIndex, 2351 NEON_LD2_post = NEON_LD2 | NEONLoadStoreMultiStructPostIndex, 2352 NEON_LD3_post = NEON_LD3 | NEONLoadStoreMultiStructPostIndex, 2353 NEON_LD4_post = NEON_LD4 | NEONLoadStoreMultiStructPostIndex, 2354 NEON_ST1_1v_post = NEON_ST1_1v | NEONLoadStoreMultiStructPostIndex, 2355 NEON_ST1_2v_post = NEON_ST1_2v | NEONLoadStoreMultiStructPostIndex, 2356 NEON_ST1_3v_post = NEON_ST1_3v | NEONLoadStoreMultiStructPostIndex, 2357 NEON_ST1_4v_post = NEON_ST1_4v | NEONLoadStoreMultiStructPostIndex, 2358 NEON_ST2_post = NEON_ST2 | NEONLoadStoreMultiStructPostIndex, 2359 NEON_ST3_post = NEON_ST3 | NEONLoadStoreMultiStructPostIndex, 2360 NEON_ST4_post = NEON_ST4 | NEONLoadStoreMultiStructPostIndex 2361}; 2362 2363enum NEONLoadStoreSingleOp { 2364 NEONLoadStoreSingle1 = 0x00000000, 2365 NEONLoadStoreSingle2 = 0x00200000, 2366 NEONLoadStoreSingle3 = 0x00002000, 2367 NEONLoadStoreSingle4 = 0x00202000, 2368 NEONLoadStoreSingleL = 0x00400000, 2369 NEONLoadStoreSingle_b = 0x00000000, 2370 NEONLoadStoreSingle_h = 0x00004000, 2371 NEONLoadStoreSingle_s = 0x00008000, 2372 NEONLoadStoreSingle_d = 0x00008400, 2373 NEONLoadStoreSingleAllLanes = 0x0000C000, 2374 NEONLoadStoreSingleLenMask = 0x00202000 2375}; 2376 2377// NEON load/store single structure. 2378enum NEONLoadStoreSingleStructOp { 2379 NEONLoadStoreSingleStructFixed = 0x0D000000, 2380 NEONLoadStoreSingleStructFMask = 0xBF9F0000, 2381 NEONLoadStoreSingleStructMask = 0xBFFFE000, 2382 NEONLoadStoreSingleStructStore = NEONLoadStoreSingleStructFixed, 2383 NEONLoadStoreSingleStructLoad = NEONLoadStoreSingleStructFixed | 2384 NEONLoadStoreSingleL, 2385 NEONLoadStoreSingleStructLoad1 = NEONLoadStoreSingle1 | 2386 NEONLoadStoreSingleStructLoad, 2387 NEONLoadStoreSingleStructLoad2 = NEONLoadStoreSingle2 | 2388 NEONLoadStoreSingleStructLoad, 2389 NEONLoadStoreSingleStructLoad3 = NEONLoadStoreSingle3 | 2390 NEONLoadStoreSingleStructLoad, 2391 NEONLoadStoreSingleStructLoad4 = NEONLoadStoreSingle4 | 2392 NEONLoadStoreSingleStructLoad, 2393 NEONLoadStoreSingleStructStore1 = NEONLoadStoreSingle1 | 2394 NEONLoadStoreSingleStructFixed, 2395 NEONLoadStoreSingleStructStore2 = NEONLoadStoreSingle2 | 2396 NEONLoadStoreSingleStructFixed, 2397 NEONLoadStoreSingleStructStore3 = NEONLoadStoreSingle3 | 2398 NEONLoadStoreSingleStructFixed, 2399 NEONLoadStoreSingleStructStore4 = NEONLoadStoreSingle4 | 2400 NEONLoadStoreSingleStructFixed, 2401 NEON_LD1_b = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_b, 2402 NEON_LD1_h = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_h, 2403 NEON_LD1_s = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_s, 2404 NEON_LD1_d = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_d, 2405 NEON_LD1R = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingleAllLanes, 2406 NEON_ST1_b = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_b, 2407 NEON_ST1_h = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_h, 2408 NEON_ST1_s = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_s, 2409 NEON_ST1_d = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_d, 2410 2411 NEON_LD2_b = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_b, 2412 NEON_LD2_h = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_h, 2413 NEON_LD2_s = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_s, 2414 NEON_LD2_d = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_d, 2415 NEON_LD2R = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingleAllLanes, 2416 NEON_ST2_b = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_b, 2417 NEON_ST2_h = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_h, 2418 NEON_ST2_s = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_s, 2419 NEON_ST2_d = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_d, 2420 2421 NEON_LD3_b = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_b, 2422 NEON_LD3_h = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_h, 2423 NEON_LD3_s = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_s, 2424 NEON_LD3_d = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_d, 2425 NEON_LD3R = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingleAllLanes, 2426 NEON_ST3_b = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_b, 2427 NEON_ST3_h = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_h, 2428 NEON_ST3_s = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_s, 2429 NEON_ST3_d = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_d, 2430 2431 NEON_LD4_b = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_b, 2432 NEON_LD4_h = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_h, 2433 NEON_LD4_s = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_s, 2434 NEON_LD4_d = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_d, 2435 NEON_LD4R = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingleAllLanes, 2436 NEON_ST4_b = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_b, 2437 NEON_ST4_h = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_h, 2438 NEON_ST4_s = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_s, 2439 NEON_ST4_d = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_d 2440}; 2441 2442// NEON load/store single structure with post-index addressing. 2443enum NEONLoadStoreSingleStructPostIndexOp { 2444 NEONLoadStoreSingleStructPostIndexFixed = 0x0D800000, 2445 NEONLoadStoreSingleStructPostIndexFMask = 0xBF800000, 2446 NEONLoadStoreSingleStructPostIndexMask = 0xBFE0E000, 2447 NEONLoadStoreSingleStructPostIndex = 0x00800000, 2448 NEON_LD1_b_post = NEON_LD1_b | NEONLoadStoreSingleStructPostIndex, 2449 NEON_LD1_h_post = NEON_LD1_h | NEONLoadStoreSingleStructPostIndex, 2450 NEON_LD1_s_post = NEON_LD1_s | NEONLoadStoreSingleStructPostIndex, 2451 NEON_LD1_d_post = NEON_LD1_d | NEONLoadStoreSingleStructPostIndex, 2452 NEON_LD1R_post = NEON_LD1R | NEONLoadStoreSingleStructPostIndex, 2453 NEON_ST1_b_post = NEON_ST1_b | NEONLoadStoreSingleStructPostIndex, 2454 NEON_ST1_h_post = NEON_ST1_h | NEONLoadStoreSingleStructPostIndex, 2455 NEON_ST1_s_post = NEON_ST1_s | NEONLoadStoreSingleStructPostIndex, 2456 NEON_ST1_d_post = NEON_ST1_d | NEONLoadStoreSingleStructPostIndex, 2457 2458 NEON_LD2_b_post = NEON_LD2_b | NEONLoadStoreSingleStructPostIndex, 2459 NEON_LD2_h_post = NEON_LD2_h | NEONLoadStoreSingleStructPostIndex, 2460 NEON_LD2_s_post = NEON_LD2_s | NEONLoadStoreSingleStructPostIndex, 2461 NEON_LD2_d_post = NEON_LD2_d | NEONLoadStoreSingleStructPostIndex, 2462 NEON_LD2R_post = NEON_LD2R | NEONLoadStoreSingleStructPostIndex, 2463 NEON_ST2_b_post = NEON_ST2_b | NEONLoadStoreSingleStructPostIndex, 2464 NEON_ST2_h_post = NEON_ST2_h | NEONLoadStoreSingleStructPostIndex, 2465 NEON_ST2_s_post = NEON_ST2_s | NEONLoadStoreSingleStructPostIndex, 2466 NEON_ST2_d_post = NEON_ST2_d | NEONLoadStoreSingleStructPostIndex, 2467 2468 NEON_LD3_b_post = NEON_LD3_b | NEONLoadStoreSingleStructPostIndex, 2469 NEON_LD3_h_post = NEON_LD3_h | NEONLoadStoreSingleStructPostIndex, 2470 NEON_LD3_s_post = NEON_LD3_s | NEONLoadStoreSingleStructPostIndex, 2471 NEON_LD3_d_post = NEON_LD3_d | NEONLoadStoreSingleStructPostIndex, 2472 NEON_LD3R_post = NEON_LD3R | NEONLoadStoreSingleStructPostIndex, 2473 NEON_ST3_b_post = NEON_ST3_b | NEONLoadStoreSingleStructPostIndex, 2474 NEON_ST3_h_post = NEON_ST3_h | NEONLoadStoreSingleStructPostIndex, 2475 NEON_ST3_s_post = NEON_ST3_s | NEONLoadStoreSingleStructPostIndex, 2476 NEON_ST3_d_post = NEON_ST3_d | NEONLoadStoreSingleStructPostIndex, 2477 2478 NEON_LD4_b_post = NEON_LD4_b | NEONLoadStoreSingleStructPostIndex, 2479 NEON_LD4_h_post = NEON_LD4_h | NEONLoadStoreSingleStructPostIndex, 2480 NEON_LD4_s_post = NEON_LD4_s | NEONLoadStoreSingleStructPostIndex, 2481 NEON_LD4_d_post = NEON_LD4_d | NEONLoadStoreSingleStructPostIndex, 2482 NEON_LD4R_post = NEON_LD4R | NEONLoadStoreSingleStructPostIndex, 2483 NEON_ST4_b_post = NEON_ST4_b | NEONLoadStoreSingleStructPostIndex, 2484 NEON_ST4_h_post = NEON_ST4_h | NEONLoadStoreSingleStructPostIndex, 2485 NEON_ST4_s_post = NEON_ST4_s | NEONLoadStoreSingleStructPostIndex, 2486 NEON_ST4_d_post = NEON_ST4_d | NEONLoadStoreSingleStructPostIndex 2487}; 2488 2489// NEON modified immediate. 2490enum NEONModifiedImmediateOp { 2491 NEONModifiedImmediateFixed = 0x0F000400, 2492 NEONModifiedImmediateFMask = 0x9FF80400, 2493 NEONModifiedImmediateOpBit = 0x20000000, 2494 NEONModifiedImmediate_FMOV = NEONModifiedImmediateFixed | 0x00000800, 2495 NEONModifiedImmediate_MOVI = NEONModifiedImmediateFixed | 0x00000000, 2496 NEONModifiedImmediate_MVNI = NEONModifiedImmediateFixed | 0x20000000, 2497 NEONModifiedImmediate_ORR = NEONModifiedImmediateFixed | 0x00001000, 2498 NEONModifiedImmediate_BIC = NEONModifiedImmediateFixed | 0x20001000 2499}; 2500 2501// NEON shift immediate. 2502enum NEONShiftImmediateOp { 2503 NEONShiftImmediateFixed = 0x0F000400, 2504 NEONShiftImmediateFMask = 0x9F800400, 2505 NEONShiftImmediateMask = 0xBF80FC00, 2506 NEONShiftImmediateUBit = 0x20000000, 2507 NEON_SHL = NEONShiftImmediateFixed | 0x00005000, 2508 NEON_SSHLL = NEONShiftImmediateFixed | 0x0000A000, 2509 NEON_USHLL = NEONShiftImmediateFixed | 0x2000A000, 2510 NEON_SLI = NEONShiftImmediateFixed | 0x20005000, 2511 NEON_SRI = NEONShiftImmediateFixed | 0x20004000, 2512 NEON_SHRN = NEONShiftImmediateFixed | 0x00008000, 2513 NEON_RSHRN = NEONShiftImmediateFixed | 0x00008800, 2514 NEON_UQSHRN = NEONShiftImmediateFixed | 0x20009000, 2515 NEON_UQRSHRN = NEONShiftImmediateFixed | 0x20009800, 2516 NEON_SQSHRN = NEONShiftImmediateFixed | 0x00009000, 2517 NEON_SQRSHRN = NEONShiftImmediateFixed | 0x00009800, 2518 NEON_SQSHRUN = NEONShiftImmediateFixed | 0x20008000, 2519 NEON_SQRSHRUN = NEONShiftImmediateFixed | 0x20008800, 2520 NEON_SSHR = NEONShiftImmediateFixed | 0x00000000, 2521 NEON_SRSHR = NEONShiftImmediateFixed | 0x00002000, 2522 NEON_USHR = NEONShiftImmediateFixed | 0x20000000, 2523 NEON_URSHR = NEONShiftImmediateFixed | 0x20002000, 2524 NEON_SSRA = NEONShiftImmediateFixed | 0x00001000, 2525 NEON_SRSRA = NEONShiftImmediateFixed | 0x00003000, 2526 NEON_USRA = NEONShiftImmediateFixed | 0x20001000, 2527 NEON_URSRA = NEONShiftImmediateFixed | 0x20003000, 2528 NEON_SQSHLU = NEONShiftImmediateFixed | 0x20006000, 2529 NEON_SCVTF_imm = NEONShiftImmediateFixed | 0x0000E000, 2530 NEON_UCVTF_imm = NEONShiftImmediateFixed | 0x2000E000, 2531 NEON_FCVTZS_imm = NEONShiftImmediateFixed | 0x0000F800, 2532 NEON_FCVTZU_imm = NEONShiftImmediateFixed | 0x2000F800, 2533 NEON_SQSHL_imm = NEONShiftImmediateFixed | 0x00007000, 2534 NEON_UQSHL_imm = NEONShiftImmediateFixed | 0x20007000 2535}; 2536 2537// NEON table. 2538enum NEONTableOp { 2539 NEONTableFixed = 0x0E000000, 2540 NEONTableFMask = 0xBF208C00, 2541 NEONTableExt = 0x00001000, 2542 NEONTableMask = 0xBF20FC00, 2543 NEON_TBL_1v = NEONTableFixed | 0x00000000, 2544 NEON_TBL_2v = NEONTableFixed | 0x00002000, 2545 NEON_TBL_3v = NEONTableFixed | 0x00004000, 2546 NEON_TBL_4v = NEONTableFixed | 0x00006000, 2547 NEON_TBX_1v = NEON_TBL_1v | NEONTableExt, 2548 NEON_TBX_2v = NEON_TBL_2v | NEONTableExt, 2549 NEON_TBX_3v = NEON_TBL_3v | NEONTableExt, 2550 NEON_TBX_4v = NEON_TBL_4v | NEONTableExt 2551}; 2552 2553// NEON perm. 2554enum NEONPermOp { 2555 NEONPermFixed = 0x0E000800, 2556 NEONPermFMask = 0xBF208C00, 2557 NEONPermMask = 0x3F20FC00, 2558 NEON_UZP1 = NEONPermFixed | 0x00001000, 2559 NEON_TRN1 = NEONPermFixed | 0x00002000, 2560 NEON_ZIP1 = NEONPermFixed | 0x00003000, 2561 NEON_UZP2 = NEONPermFixed | 0x00005000, 2562 NEON_TRN2 = NEONPermFixed | 0x00006000, 2563 NEON_ZIP2 = NEONPermFixed | 0x00007000 2564}; 2565 2566// NEON scalar instructions with two register operands. 2567enum NEONScalar2RegMiscOp { 2568 NEONScalar2RegMiscFixed = 0x5E200800, 2569 NEONScalar2RegMiscFMask = 0xDF3E0C00, 2570 NEONScalar2RegMiscMask = NEON_Q | NEONScalar | NEON2RegMiscMask, 2571 NEON_CMGT_zero_scalar = NEON_Q | NEONScalar | NEON_CMGT_zero, 2572 NEON_CMEQ_zero_scalar = NEON_Q | NEONScalar | NEON_CMEQ_zero, 2573 NEON_CMLT_zero_scalar = NEON_Q | NEONScalar | NEON_CMLT_zero, 2574 NEON_CMGE_zero_scalar = NEON_Q | NEONScalar | NEON_CMGE_zero, 2575 NEON_CMLE_zero_scalar = NEON_Q | NEONScalar | NEON_CMLE_zero, 2576 NEON_ABS_scalar = NEON_Q | NEONScalar | NEON_ABS, 2577 NEON_SQABS_scalar = NEON_Q | NEONScalar | NEON_SQABS, 2578 NEON_NEG_scalar = NEON_Q | NEONScalar | NEON_NEG, 2579 NEON_SQNEG_scalar = NEON_Q | NEONScalar | NEON_SQNEG, 2580 NEON_SQXTN_scalar = NEON_Q | NEONScalar | NEON_SQXTN, 2581 NEON_UQXTN_scalar = NEON_Q | NEONScalar | NEON_UQXTN, 2582 NEON_SQXTUN_scalar = NEON_Q | NEONScalar | NEON_SQXTUN, 2583 NEON_SUQADD_scalar = NEON_Q | NEONScalar | NEON_SUQADD, 2584 NEON_USQADD_scalar = NEON_Q | NEONScalar | NEON_USQADD, 2585 2586 NEONScalar2RegMiscOpcode = NEON2RegMiscOpcode, 2587 NEON_NEG_scalar_opcode = NEON_NEG_scalar & NEONScalar2RegMiscOpcode, 2588 2589 NEONScalar2RegMiscFPMask = NEONScalar2RegMiscMask | 0x00800000, 2590 NEON_FRSQRTE_scalar = NEON_Q | NEONScalar | NEON_FRSQRTE, 2591 NEON_FRECPE_scalar = NEON_Q | NEONScalar | NEON_FRECPE, 2592 NEON_SCVTF_scalar = NEON_Q | NEONScalar | NEON_SCVTF, 2593 NEON_UCVTF_scalar = NEON_Q | NEONScalar | NEON_UCVTF, 2594 NEON_FCMGT_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGT_zero, 2595 NEON_FCMEQ_zero_scalar = NEON_Q | NEONScalar | NEON_FCMEQ_zero, 2596 NEON_FCMLT_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLT_zero, 2597 NEON_FCMGE_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGE_zero, 2598 NEON_FCMLE_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLE_zero, 2599 NEON_FRECPX_scalar = NEONScalar2RegMiscFixed | 0x0081F000, 2600 NEON_FCVTNS_scalar = NEON_Q | NEONScalar | NEON_FCVTNS, 2601 NEON_FCVTNU_scalar = NEON_Q | NEONScalar | NEON_FCVTNU, 2602 NEON_FCVTPS_scalar = NEON_Q | NEONScalar | NEON_FCVTPS, 2603 NEON_FCVTPU_scalar = NEON_Q | NEONScalar | NEON_FCVTPU, 2604 NEON_FCVTMS_scalar = NEON_Q | NEONScalar | NEON_FCVTMS, 2605 NEON_FCVTMU_scalar = NEON_Q | NEONScalar | NEON_FCVTMU, 2606 NEON_FCVTZS_scalar = NEON_Q | NEONScalar | NEON_FCVTZS, 2607 NEON_FCVTZU_scalar = NEON_Q | NEONScalar | NEON_FCVTZU, 2608 NEON_FCVTAS_scalar = NEON_Q | NEONScalar | NEON_FCVTAS, 2609 NEON_FCVTAU_scalar = NEON_Q | NEONScalar | NEON_FCVTAU, 2610 NEON_FCVTXN_scalar = NEON_Q | NEONScalar | NEON_FCVTXN 2611}; 2612 2613// NEON instructions with two register operands (FP16). 2614enum NEONScalar2RegMiscFP16Op { 2615 NEONScalar2RegMiscFP16Fixed = 0x5E780800, 2616 NEONScalar2RegMiscFP16FMask = 0xDF7E0C00, 2617 NEONScalar2RegMiscFP16Mask = 0xFFFFFC00, 2618 NEON_FCVTNS_H_scalar = NEON_Q | NEONScalar | NEON_FCVTNS_H, 2619 NEON_FCVTMS_H_scalar = NEON_Q | NEONScalar | NEON_FCVTMS_H, 2620 NEON_FCVTAS_H_scalar = NEON_Q | NEONScalar | NEON_FCVTAS_H, 2621 NEON_SCVTF_H_scalar = NEON_Q | NEONScalar | NEON_SCVTF_H, 2622 NEON_FCMGT_H_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGT_H_zero, 2623 NEON_FCMEQ_H_zero_scalar = NEON_Q | NEONScalar | NEON_FCMEQ_H_zero, 2624 NEON_FCMLT_H_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLT_H_zero, 2625 NEON_FCVTPS_H_scalar = NEON_Q | NEONScalar | NEON_FCVTPS_H, 2626 NEON_FCVTZS_H_scalar = NEON_Q | NEONScalar | NEON_FCVTZS_H, 2627 NEON_FRECPE_H_scalar = NEON_Q | NEONScalar | NEON_FRECPE_H, 2628 NEON_FRECPX_H_scalar = NEONScalar2RegMiscFP16Fixed | 0x0081F000, 2629 NEON_FCVTNU_H_scalar = NEON_Q | NEONScalar | NEON_FCVTNU_H, 2630 NEON_FCVTMU_H_scalar = NEON_Q | NEONScalar | NEON_FCVTMU_H, 2631 NEON_FCVTAU_H_scalar = NEON_Q | NEONScalar | NEON_FCVTAU_H, 2632 NEON_UCVTF_H_scalar = NEON_Q | NEONScalar | NEON_UCVTF_H, 2633 NEON_FCMGE_H_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGE_H_zero, 2634 NEON_FCMLE_H_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLE_H_zero, 2635 NEON_FCVTPU_H_scalar = NEON_Q | NEONScalar | NEON_FCVTPU_H, 2636 NEON_FCVTZU_H_scalar = NEON_Q | NEONScalar | NEON_FCVTZU_H, 2637 NEON_FRSQRTE_H_scalar = NEON_Q | NEONScalar | NEON_FRSQRTE_H 2638}; 2639 2640// NEON scalar instructions with three same-type operands. 2641enum NEONScalar3SameOp { 2642 NEONScalar3SameFixed = 0x5E200400, 2643 NEONScalar3SameFMask = 0xDF200400, 2644 NEONScalar3SameMask = 0xFF20FC00, 2645 NEON_ADD_scalar = NEON_Q | NEONScalar | NEON_ADD, 2646 NEON_CMEQ_scalar = NEON_Q | NEONScalar | NEON_CMEQ, 2647 NEON_CMGE_scalar = NEON_Q | NEONScalar | NEON_CMGE, 2648 NEON_CMGT_scalar = NEON_Q | NEONScalar | NEON_CMGT, 2649 NEON_CMHI_scalar = NEON_Q | NEONScalar | NEON_CMHI, 2650 NEON_CMHS_scalar = NEON_Q | NEONScalar | NEON_CMHS, 2651 NEON_CMTST_scalar = NEON_Q | NEONScalar | NEON_CMTST, 2652 NEON_SUB_scalar = NEON_Q | NEONScalar | NEON_SUB, 2653 NEON_UQADD_scalar = NEON_Q | NEONScalar | NEON_UQADD, 2654 NEON_SQADD_scalar = NEON_Q | NEONScalar | NEON_SQADD, 2655 NEON_UQSUB_scalar = NEON_Q | NEONScalar | NEON_UQSUB, 2656 NEON_SQSUB_scalar = NEON_Q | NEONScalar | NEON_SQSUB, 2657 NEON_USHL_scalar = NEON_Q | NEONScalar | NEON_USHL, 2658 NEON_SSHL_scalar = NEON_Q | NEONScalar | NEON_SSHL, 2659 NEON_UQSHL_scalar = NEON_Q | NEONScalar | NEON_UQSHL, 2660 NEON_SQSHL_scalar = NEON_Q | NEONScalar | NEON_SQSHL, 2661 NEON_URSHL_scalar = NEON_Q | NEONScalar | NEON_URSHL, 2662 NEON_SRSHL_scalar = NEON_Q | NEONScalar | NEON_SRSHL, 2663 NEON_UQRSHL_scalar = NEON_Q | NEONScalar | NEON_UQRSHL, 2664 NEON_SQRSHL_scalar = NEON_Q | NEONScalar | NEON_SQRSHL, 2665 NEON_SQDMULH_scalar = NEON_Q | NEONScalar | NEON_SQDMULH, 2666 NEON_SQRDMULH_scalar = NEON_Q | NEONScalar | NEON_SQRDMULH, 2667 2668 // NEON floating point scalar instructions with three same-type operands. 2669 NEONScalar3SameFPFixed = NEONScalar3SameFixed | 0x0000C000, 2670 NEONScalar3SameFPFMask = NEONScalar3SameFMask | 0x0000C000, 2671 NEONScalar3SameFPMask = NEONScalar3SameMask | 0x00800000, 2672 NEON_FACGE_scalar = NEON_Q | NEONScalar | NEON_FACGE, 2673 NEON_FACGT_scalar = NEON_Q | NEONScalar | NEON_FACGT, 2674 NEON_FCMEQ_scalar = NEON_Q | NEONScalar | NEON_FCMEQ, 2675 NEON_FCMGE_scalar = NEON_Q | NEONScalar | NEON_FCMGE, 2676 NEON_FCMGT_scalar = NEON_Q | NEONScalar | NEON_FCMGT, 2677 NEON_FMULX_scalar = NEON_Q | NEONScalar | NEON_FMULX, 2678 NEON_FRECPS_scalar = NEON_Q | NEONScalar | NEON_FRECPS, 2679 NEON_FRSQRTS_scalar = NEON_Q | NEONScalar | NEON_FRSQRTS, 2680 NEON_FABD_scalar = NEON_Q | NEONScalar | NEON_FABD 2681}; 2682 2683// NEON scalar FP16 instructions with three same-type operands. 2684enum NEONScalar3SameFP16Op { 2685 NEONScalar3SameFP16Fixed = 0x5E400400, 2686 NEONScalar3SameFP16FMask = 0xDF60C400, 2687 NEONScalar3SameFP16Mask = 0xFFE0FC00, 2688 NEON_FABD_H_scalar = NEON_Q | NEONScalar | NEON_FABD_H, 2689 NEON_FMULX_H_scalar = NEON_Q | NEONScalar | NEON_FMULX_H, 2690 NEON_FCMEQ_H_scalar = NEON_Q | NEONScalar | NEON_FCMEQ_H, 2691 NEON_FCMGE_H_scalar = NEON_Q | NEONScalar | NEON_FCMGE_H, 2692 NEON_FCMGT_H_scalar = NEON_Q | NEONScalar | NEON_FCMGT_H, 2693 NEON_FACGE_H_scalar = NEON_Q | NEONScalar | NEON_FACGE_H, 2694 NEON_FACGT_H_scalar = NEON_Q | NEONScalar | NEON_FACGT_H, 2695 NEON_FRECPS_H_scalar = NEON_Q | NEONScalar | NEON_FRECPS_H, 2696 NEON_FRSQRTS_H_scalar = NEON_Q | NEONScalar | NEON_FRSQRTS_H 2697}; 2698 2699// 'Extra' NEON scalar instructions with three same-type operands. 2700enum NEONScalar3SameExtraOp { 2701 NEONScalar3SameExtraFixed = 0x5E008400, 2702 NEONScalar3SameExtraFMask = 0xDF208400, 2703 NEONScalar3SameExtraMask = 0xFF20FC00, 2704 NEON_SQRDMLAH_scalar = NEON_Q | NEONScalar | NEON_SQRDMLAH, 2705 NEON_SQRDMLSH_scalar = NEON_Q | NEONScalar | NEON_SQRDMLSH 2706}; 2707 2708// NEON scalar instructions with three different-type operands. 2709enum NEONScalar3DiffOp { 2710 NEONScalar3DiffFixed = 0x5E200000, 2711 NEONScalar3DiffFMask = 0xDF200C00, 2712 NEONScalar3DiffMask = NEON_Q | NEONScalar | NEON3DifferentMask, 2713 NEON_SQDMLAL_scalar = NEON_Q | NEONScalar | NEON_SQDMLAL, 2714 NEON_SQDMLSL_scalar = NEON_Q | NEONScalar | NEON_SQDMLSL, 2715 NEON_SQDMULL_scalar = NEON_Q | NEONScalar | NEON_SQDMULL 2716}; 2717 2718// NEON scalar instructions with indexed element operand. 2719enum NEONScalarByIndexedElementOp { 2720 NEONScalarByIndexedElementFixed = 0x5F000000, 2721 NEONScalarByIndexedElementFMask = 0xDF000400, 2722 NEONScalarByIndexedElementMask = 0xFF00F400, 2723 NEON_SQDMLAL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMLAL_byelement, 2724 NEON_SQDMLSL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMLSL_byelement, 2725 NEON_SQDMULL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMULL_byelement, 2726 NEON_SQDMULH_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMULH_byelement, 2727 NEON_SQRDMULH_byelement_scalar 2728 = NEON_Q | NEONScalar | NEON_SQRDMULH_byelement, 2729 NEON_SQRDMLAH_byelement_scalar 2730 = NEON_Q | NEONScalar | NEON_SQRDMLAH_byelement, 2731 NEON_SQRDMLSH_byelement_scalar 2732 = NEON_Q | NEONScalar | NEON_SQRDMLSH_byelement, 2733 NEON_FMLA_H_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLA_H_byelement, 2734 NEON_FMLS_H_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLS_H_byelement, 2735 NEON_FMUL_H_byelement_scalar = NEON_Q | NEONScalar | NEON_FMUL_H_byelement, 2736 NEON_FMULX_H_byelement_scalar = NEON_Q | NEONScalar | NEON_FMULX_H_byelement, 2737 2738 // Floating point instructions. 2739 NEONScalarByIndexedElementFPFixed 2740 = NEONScalarByIndexedElementFixed | 0x00800000, 2741 NEONScalarByIndexedElementFPMask 2742 = NEONScalarByIndexedElementMask | 0x00800000, 2743 NEON_FMLA_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLA_byelement, 2744 NEON_FMLS_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLS_byelement, 2745 NEON_FMUL_byelement_scalar = NEON_Q | NEONScalar | NEON_FMUL_byelement, 2746 NEON_FMULX_byelement_scalar = NEON_Q | NEONScalar | NEON_FMULX_byelement 2747}; 2748 2749// NEON scalar register copy. 2750enum NEONScalarCopyOp { 2751 NEONScalarCopyFixed = 0x5E000400, 2752 NEONScalarCopyFMask = 0xDFE08400, 2753 NEONScalarCopyMask = 0xFFE0FC00, 2754 NEON_DUP_ELEMENT_scalar = NEON_Q | NEONScalar | NEON_DUP_ELEMENT 2755}; 2756 2757// NEON scalar pairwise instructions. 2758enum NEONScalarPairwiseOp { 2759 NEONScalarPairwiseFixed = 0x5E300800, 2760 NEONScalarPairwiseFMask = 0xDF3E0C00, 2761 NEONScalarPairwiseMask = 0xFFB1F800, 2762 NEON_ADDP_scalar = NEONScalarPairwiseFixed | 0x0081B000, 2763 NEON_FMAXNMP_h_scalar = NEONScalarPairwiseFixed | 0x0000C000, 2764 NEON_FADDP_h_scalar = NEONScalarPairwiseFixed | 0x0000D000, 2765 NEON_FMAXP_h_scalar = NEONScalarPairwiseFixed | 0x0000F000, 2766 NEON_FMINNMP_h_scalar = NEONScalarPairwiseFixed | 0x0080C000, 2767 NEON_FMINP_h_scalar = NEONScalarPairwiseFixed | 0x0080F000, 2768 NEON_FMAXNMP_scalar = NEONScalarPairwiseFixed | 0x2000C000, 2769 NEON_FMINNMP_scalar = NEONScalarPairwiseFixed | 0x2080C000, 2770 NEON_FADDP_scalar = NEONScalarPairwiseFixed | 0x2000D000, 2771 NEON_FMAXP_scalar = NEONScalarPairwiseFixed | 0x2000F000, 2772 NEON_FMINP_scalar = NEONScalarPairwiseFixed | 0x2080F000 2773}; 2774 2775// NEON scalar shift immediate. 2776enum NEONScalarShiftImmediateOp { 2777 NEONScalarShiftImmediateFixed = 0x5F000400, 2778 NEONScalarShiftImmediateFMask = 0xDF800400, 2779 NEONScalarShiftImmediateMask = 0xFF80FC00, 2780 NEON_SHL_scalar = NEON_Q | NEONScalar | NEON_SHL, 2781 NEON_SLI_scalar = NEON_Q | NEONScalar | NEON_SLI, 2782 NEON_SRI_scalar = NEON_Q | NEONScalar | NEON_SRI, 2783 NEON_SSHR_scalar = NEON_Q | NEONScalar | NEON_SSHR, 2784 NEON_USHR_scalar = NEON_Q | NEONScalar | NEON_USHR, 2785 NEON_SRSHR_scalar = NEON_Q | NEONScalar | NEON_SRSHR, 2786 NEON_URSHR_scalar = NEON_Q | NEONScalar | NEON_URSHR, 2787 NEON_SSRA_scalar = NEON_Q | NEONScalar | NEON_SSRA, 2788 NEON_USRA_scalar = NEON_Q | NEONScalar | NEON_USRA, 2789 NEON_SRSRA_scalar = NEON_Q | NEONScalar | NEON_SRSRA, 2790 NEON_URSRA_scalar = NEON_Q | NEONScalar | NEON_URSRA, 2791 NEON_UQSHRN_scalar = NEON_Q | NEONScalar | NEON_UQSHRN, 2792 NEON_UQRSHRN_scalar = NEON_Q | NEONScalar | NEON_UQRSHRN, 2793 NEON_SQSHRN_scalar = NEON_Q | NEONScalar | NEON_SQSHRN, 2794 NEON_SQRSHRN_scalar = NEON_Q | NEONScalar | NEON_SQRSHRN, 2795 NEON_SQSHRUN_scalar = NEON_Q | NEONScalar | NEON_SQSHRUN, 2796 NEON_SQRSHRUN_scalar = NEON_Q | NEONScalar | NEON_SQRSHRUN, 2797 NEON_SQSHLU_scalar = NEON_Q | NEONScalar | NEON_SQSHLU, 2798 NEON_SQSHL_imm_scalar = NEON_Q | NEONScalar | NEON_SQSHL_imm, 2799 NEON_UQSHL_imm_scalar = NEON_Q | NEONScalar | NEON_UQSHL_imm, 2800 NEON_SCVTF_imm_scalar = NEON_Q | NEONScalar | NEON_SCVTF_imm, 2801 NEON_UCVTF_imm_scalar = NEON_Q | NEONScalar | NEON_UCVTF_imm, 2802 NEON_FCVTZS_imm_scalar = NEON_Q | NEONScalar | NEON_FCVTZS_imm, 2803 NEON_FCVTZU_imm_scalar = NEON_Q | NEONScalar | NEON_FCVTZU_imm 2804}; 2805 2806enum SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsOp { 2807 SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFixed = 0x84A00000, 2808 SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFMask = 0xFFA08000, 2809 SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsMask = 0xFFA0E000, 2810 LD1SH_z_p_bz_s_x32_scaled = SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFixed, 2811 LDFF1SH_z_p_bz_s_x32_scaled = SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFixed | 0x00002000, 2812 LD1H_z_p_bz_s_x32_scaled = SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFixed | 0x00004000, 2813 LDFF1H_z_p_bz_s_x32_scaled = SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFixed | 0x00006000 2814}; 2815 2816enum SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsOp { 2817 SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsFixed = 0x85200000, 2818 SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsFMask = 0xFFA08000, 2819 SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsMask = 0xFFA0E000, 2820 LD1W_z_p_bz_s_x32_scaled = SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsFixed | 0x00004000, 2821 LDFF1W_z_p_bz_s_x32_scaled = SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsFixed | 0x00006000 2822}; 2823 2824enum SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsOp { 2825 SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed = 0x84000000, 2826 SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFMask = 0xFE208000, 2827 SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsMask = 0xFFA0E000, 2828 LD1SB_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed, 2829 LDFF1SB_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00002000, 2830 LD1B_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00004000, 2831 LDFF1B_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00006000, 2832 LD1SH_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00800000, 2833 LDFF1SH_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00802000, 2834 LD1H_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00804000, 2835 LDFF1H_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00806000, 2836 LD1W_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x01004000, 2837 LDFF1W_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x01006000 2838}; 2839 2840enum SVE32BitGatherLoad_VectorPlusImmOp { 2841 SVE32BitGatherLoad_VectorPlusImmFixed = 0x84208000, 2842 SVE32BitGatherLoad_VectorPlusImmFMask = 0xFE608000, 2843 SVE32BitGatherLoad_VectorPlusImmMask = 0xFFE0E000, 2844 LD1SB_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed, 2845 LDFF1SB_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00002000, 2846 LD1B_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00004000, 2847 LDFF1B_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00006000, 2848 LD1SH_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00800000, 2849 LDFF1SH_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00802000, 2850 LD1H_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00804000, 2851 LDFF1H_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00806000, 2852 LD1W_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x01004000, 2853 LDFF1W_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x01006000 2854}; 2855 2856enum SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsOp { 2857 SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFixed = 0x84200000, 2858 SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFMask = 0xFFA08010, 2859 SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsMask = 0xFFA0E010, 2860 PRFB_i_p_bz_s_x32_scaled = SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFixed, 2861 PRFH_i_p_bz_s_x32_scaled = SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFixed | 0x00002000, 2862 PRFW_i_p_bz_s_x32_scaled = SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFixed | 0x00004000, 2863 PRFD_i_p_bz_s_x32_scaled = SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFixed | 0x00006000 2864}; 2865 2866enum SVE32BitGatherPrefetch_VectorPlusImmOp { 2867 SVE32BitGatherPrefetch_VectorPlusImmFixed = 0x8400E000, 2868 SVE32BitGatherPrefetch_VectorPlusImmFMask = 0xFE60E010, 2869 SVE32BitGatherPrefetch_VectorPlusImmMask = 0xFFE0E010, 2870 PRFB_i_p_ai_s = SVE32BitGatherPrefetch_VectorPlusImmFixed, 2871 PRFH_i_p_ai_s = SVE32BitGatherPrefetch_VectorPlusImmFixed | 0x00800000, 2872 PRFW_i_p_ai_s = SVE32BitGatherPrefetch_VectorPlusImmFixed | 0x01000000, 2873 PRFD_i_p_ai_s = SVE32BitGatherPrefetch_VectorPlusImmFixed | 0x01800000 2874}; 2875 2876enum SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsOp { 2877 SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsFixed = 0xE4608000, 2878 SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsFMask = 0xFE60A000, 2879 SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsMask = 0xFFE0A000, 2880 ST1H_z_p_bz_s_x32_scaled = SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsFixed | 0x00800000, 2881 ST1W_z_p_bz_s_x32_scaled = SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsFixed | 0x01000000 2882}; 2883 2884enum SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsOp { 2885 SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsFixed = 0xE4408000, 2886 SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsFMask = 0xFE60A000, 2887 SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsMask = 0xFFE0A000, 2888 ST1B_z_p_bz_s_x32_unscaled = SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsFixed, 2889 ST1H_z_p_bz_s_x32_unscaled = SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsFixed | 0x00800000, 2890 ST1W_z_p_bz_s_x32_unscaled = SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsFixed | 0x01000000 2891}; 2892 2893enum SVE32BitScatterStore_VectorPlusImmOp { 2894 SVE32BitScatterStore_VectorPlusImmFixed = 0xE460A000, 2895 SVE32BitScatterStore_VectorPlusImmFMask = 0xFE60E000, 2896 SVE32BitScatterStore_VectorPlusImmMask = 0xFFE0E000, 2897 ST1B_z_p_ai_s = SVE32BitScatterStore_VectorPlusImmFixed, 2898 ST1H_z_p_ai_s = SVE32BitScatterStore_VectorPlusImmFixed | 0x00800000, 2899 ST1W_z_p_ai_s = SVE32BitScatterStore_VectorPlusImmFixed | 0x01000000 2900}; 2901 2902enum SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsOp { 2903 SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed = 0xC4200000, 2904 SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFMask = 0xFE208000, 2905 SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsMask = 0xFFA0E000, 2906 LD1SH_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x00800000, 2907 LDFF1SH_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x00802000, 2908 LD1H_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x00804000, 2909 LDFF1H_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x00806000, 2910 LD1SW_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01000000, 2911 LDFF1SW_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01002000, 2912 LD1W_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01004000, 2913 LDFF1W_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01006000, 2914 LD1D_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01804000, 2915 LDFF1D_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01806000 2916}; 2917 2918enum SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsOp { 2919 SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed = 0xC4608000, 2920 SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFMask = 0xFE608000, 2921 SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsMask = 0xFFE0E000, 2922 LD1SH_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x00800000, 2923 LDFF1SH_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x00802000, 2924 LD1H_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x00804000, 2925 LDFF1H_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x00806000, 2926 LD1SW_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01000000, 2927 LDFF1SW_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01002000, 2928 LD1W_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01004000, 2929 LDFF1W_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01006000, 2930 LD1D_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01804000, 2931 LDFF1D_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01806000 2932}; 2933 2934enum SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsOp { 2935 SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed = 0xC4408000, 2936 SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFMask = 0xFE608000, 2937 SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsMask = 0xFFE0E000, 2938 LD1SB_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed, 2939 LDFF1SB_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00002000, 2940 LD1B_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00004000, 2941 LDFF1B_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00006000, 2942 LD1SH_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00800000, 2943 LDFF1SH_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00802000, 2944 LD1H_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00804000, 2945 LDFF1H_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00806000, 2946 LD1SW_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01000000, 2947 LDFF1SW_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01002000, 2948 LD1W_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01004000, 2949 LDFF1W_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01006000, 2950 LD1D_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01804000, 2951 LDFF1D_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01806000 2952}; 2953 2954enum SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsOp { 2955 SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed = 0xC4000000, 2956 SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFMask = 0xFE208000, 2957 SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsMask = 0xFFA0E000, 2958 LD1SB_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed, 2959 LDFF1SB_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00002000, 2960 LD1B_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00004000, 2961 LDFF1B_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00006000, 2962 LD1SH_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00800000, 2963 LDFF1SH_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00802000, 2964 LD1H_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00804000, 2965 LDFF1H_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00806000, 2966 LD1SW_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01000000, 2967 LDFF1SW_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01002000, 2968 LD1W_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01004000, 2969 LDFF1W_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01006000, 2970 LD1D_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01804000, 2971 LDFF1D_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01806000 2972}; 2973 2974enum SVE64BitGatherLoad_VectorPlusImmOp { 2975 SVE64BitGatherLoad_VectorPlusImmFixed = 0xC4208000, 2976 SVE64BitGatherLoad_VectorPlusImmFMask = 0xFE608000, 2977 SVE64BitGatherLoad_VectorPlusImmMask = 0xFFE0E000, 2978 LD1SB_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed, 2979 LDFF1SB_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00002000, 2980 LD1B_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00004000, 2981 LDFF1B_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00006000, 2982 LD1SH_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00800000, 2983 LDFF1SH_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00802000, 2984 LD1H_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00804000, 2985 LDFF1H_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00806000, 2986 LD1SW_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01000000, 2987 LDFF1SW_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01002000, 2988 LD1W_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01004000, 2989 LDFF1W_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01006000, 2990 LD1D_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01804000, 2991 LDFF1D_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01806000 2992}; 2993 2994enum SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsOp { 2995 SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFixed = 0xC4608000, 2996 SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFMask = 0xFFE08010, 2997 SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsMask = 0xFFE0E010, 2998 PRFB_i_p_bz_d_64_scaled = SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFixed, 2999 PRFH_i_p_bz_d_64_scaled = SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFixed | 0x00002000, 3000 PRFW_i_p_bz_d_64_scaled = SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFixed | 0x00004000, 3001 PRFD_i_p_bz_d_64_scaled = SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFixed | 0x00006000 3002}; 3003 3004enum SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsOp { 3005 SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFixed = 0xC4200000, 3006 SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFMask = 0xFFA08010, 3007 SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsMask = 0xFFA0E010, 3008 PRFB_i_p_bz_d_x32_scaled = SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFixed, 3009 PRFH_i_p_bz_d_x32_scaled = SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x00002000, 3010 PRFW_i_p_bz_d_x32_scaled = SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x00004000, 3011 PRFD_i_p_bz_d_x32_scaled = SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x00006000 3012}; 3013 3014enum SVE64BitGatherPrefetch_VectorPlusImmOp { 3015 SVE64BitGatherPrefetch_VectorPlusImmFixed = 0xC400E000, 3016 SVE64BitGatherPrefetch_VectorPlusImmFMask = 0xFE60E010, 3017 SVE64BitGatherPrefetch_VectorPlusImmMask = 0xFFE0E010, 3018 PRFB_i_p_ai_d = SVE64BitGatherPrefetch_VectorPlusImmFixed, 3019 PRFH_i_p_ai_d = SVE64BitGatherPrefetch_VectorPlusImmFixed | 0x00800000, 3020 PRFW_i_p_ai_d = SVE64BitGatherPrefetch_VectorPlusImmFixed | 0x01000000, 3021 PRFD_i_p_ai_d = SVE64BitGatherPrefetch_VectorPlusImmFixed | 0x01800000 3022}; 3023 3024enum SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsOp { 3025 SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsFixed = 0xE420A000, 3026 SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsFMask = 0xFE60E000, 3027 SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsMask = 0xFFE0E000, 3028 ST1H_z_p_bz_d_64_scaled = SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsFixed | 0x00800000, 3029 ST1W_z_p_bz_d_64_scaled = SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsFixed | 0x01000000, 3030 ST1D_z_p_bz_d_64_scaled = SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsFixed | 0x01800000 3031}; 3032 3033enum SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsOp { 3034 SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFixed = 0xE400A000, 3035 SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFMask = 0xFE60E000, 3036 SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsMask = 0xFFE0E000, 3037 ST1B_z_p_bz_d_64_unscaled = SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFixed, 3038 ST1H_z_p_bz_d_64_unscaled = SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFixed | 0x00800000, 3039 ST1W_z_p_bz_d_64_unscaled = SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFixed | 0x01000000, 3040 ST1D_z_p_bz_d_64_unscaled = SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFixed | 0x01800000 3041}; 3042 3043enum SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsOp { 3044 SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsFixed = 0xE4208000, 3045 SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsFMask = 0xFE60A000, 3046 SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsMask = 0xFFE0A000, 3047 ST1H_z_p_bz_d_x32_scaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x00800000, 3048 ST1W_z_p_bz_d_x32_scaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x01000000, 3049 ST1D_z_p_bz_d_x32_scaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x01800000 3050}; 3051 3052enum SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsOp { 3053 SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFixed = 0xE4008000, 3054 SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFMask = 0xFE60A000, 3055 SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsMask = 0xFFE0A000, 3056 ST1B_z_p_bz_d_x32_unscaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFixed, 3057 ST1H_z_p_bz_d_x32_unscaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00800000, 3058 ST1W_z_p_bz_d_x32_unscaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01000000, 3059 ST1D_z_p_bz_d_x32_unscaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01800000 3060}; 3061 3062enum SVE64BitScatterStore_VectorPlusImmOp { 3063 SVE64BitScatterStore_VectorPlusImmFixed = 0xE440A000, 3064 SVE64BitScatterStore_VectorPlusImmFMask = 0xFE60E000, 3065 SVE64BitScatterStore_VectorPlusImmMask = 0xFFE0E000, 3066 ST1B_z_p_ai_d = SVE64BitScatterStore_VectorPlusImmFixed, 3067 ST1H_z_p_ai_d = SVE64BitScatterStore_VectorPlusImmFixed | 0x00800000, 3068 ST1W_z_p_ai_d = SVE64BitScatterStore_VectorPlusImmFixed | 0x01000000, 3069 ST1D_z_p_ai_d = SVE64BitScatterStore_VectorPlusImmFixed | 0x01800000 3070}; 3071 3072enum SVEAddressGenerationOp { 3073 SVEAddressGenerationFixed = 0x0420A000, 3074 SVEAddressGenerationFMask = 0xFF20F000, 3075 SVEAddressGenerationMask = 0xFFE0F000, 3076 ADR_z_az_d_s32_scaled = SVEAddressGenerationFixed, 3077 ADR_z_az_d_u32_scaled = SVEAddressGenerationFixed | 0x00400000, 3078 ADR_z_az_s_same_scaled = SVEAddressGenerationFixed | 0x00800000, 3079 ADR_z_az_d_same_scaled = SVEAddressGenerationFixed | 0x00C00000 3080}; 3081 3082enum SVEBitwiseLogicalUnpredicatedOp { 3083 SVEBitwiseLogicalUnpredicatedFixed = 0x04202000, 3084 SVEBitwiseLogicalUnpredicatedFMask = 0xFF20E000, 3085 SVEBitwiseLogicalUnpredicatedMask = 0xFFE0FC00, 3086 AND_z_zz = SVEBitwiseLogicalUnpredicatedFixed | 0x00001000, 3087 ORR_z_zz = SVEBitwiseLogicalUnpredicatedFixed | 0x00401000, 3088 EOR_z_zz = SVEBitwiseLogicalUnpredicatedFixed | 0x00801000, 3089 BIC_z_zz = SVEBitwiseLogicalUnpredicatedFixed | 0x00C01000 3090}; 3091 3092enum SVEBitwiseLogicalWithImm_UnpredicatedOp { 3093 SVEBitwiseLogicalWithImm_UnpredicatedFixed = 0x05000000, 3094 SVEBitwiseLogicalWithImm_UnpredicatedFMask = 0xFF3C0000, 3095 SVEBitwiseLogicalWithImm_UnpredicatedMask = 0xFFFC0000, 3096 ORR_z_zi = SVEBitwiseLogicalWithImm_UnpredicatedFixed, 3097 EOR_z_zi = SVEBitwiseLogicalWithImm_UnpredicatedFixed | 0x00400000, 3098 AND_z_zi = SVEBitwiseLogicalWithImm_UnpredicatedFixed | 0x00800000 3099}; 3100 3101enum SVEBitwiseLogical_PredicatedOp { 3102 SVEBitwiseLogical_PredicatedFixed = 0x04180000, 3103 SVEBitwiseLogical_PredicatedFMask = 0xFF38E000, 3104 SVEBitwiseLogical_PredicatedMask = 0xFF3FE000, 3105 ORR_z_p_zz = SVEBitwiseLogical_PredicatedFixed, 3106 EOR_z_p_zz = SVEBitwiseLogical_PredicatedFixed | 0x00010000, 3107 AND_z_p_zz = SVEBitwiseLogical_PredicatedFixed | 0x00020000, 3108 BIC_z_p_zz = SVEBitwiseLogical_PredicatedFixed | 0x00030000 3109}; 3110 3111enum SVEBitwiseShiftByImm_PredicatedOp { 3112 SVEBitwiseShiftByImm_PredicatedFixed = 0x04008000, 3113 SVEBitwiseShiftByImm_PredicatedFMask = 0xFF30E000, 3114 SVEBitwiseShiftByImm_PredicatedMask = 0xFF3FE000, 3115 ASR_z_p_zi = SVEBitwiseShiftByImm_PredicatedFixed, 3116 LSR_z_p_zi = SVEBitwiseShiftByImm_PredicatedFixed | 0x00010000, 3117 LSL_z_p_zi = SVEBitwiseShiftByImm_PredicatedFixed | 0x00030000, 3118 ASRD_z_p_zi = SVEBitwiseShiftByImm_PredicatedFixed | 0x00040000 3119}; 3120 3121enum SVEBitwiseShiftByVector_PredicatedOp { 3122 SVEBitwiseShiftByVector_PredicatedFixed = 0x04108000, 3123 SVEBitwiseShiftByVector_PredicatedFMask = 0xFF38E000, 3124 SVEBitwiseShiftByVector_PredicatedMask = 0xFF3FE000, 3125 ASR_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed, 3126 LSR_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed | 0x00010000, 3127 LSL_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed | 0x00030000, 3128 ASRR_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed | 0x00040000, 3129 LSRR_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed | 0x00050000, 3130 LSLR_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed | 0x00070000 3131}; 3132 3133enum SVEBitwiseShiftByWideElements_PredicatedOp { 3134 SVEBitwiseShiftByWideElements_PredicatedFixed = 0x04188000, 3135 SVEBitwiseShiftByWideElements_PredicatedFMask = 0xFF38E000, 3136 SVEBitwiseShiftByWideElements_PredicatedMask = 0xFF3FE000, 3137 ASR_z_p_zw = SVEBitwiseShiftByWideElements_PredicatedFixed, 3138 LSR_z_p_zw = SVEBitwiseShiftByWideElements_PredicatedFixed | 0x00010000, 3139 LSL_z_p_zw = SVEBitwiseShiftByWideElements_PredicatedFixed | 0x00030000 3140}; 3141 3142enum SVEBitwiseShiftUnpredicatedOp { 3143 SVEBitwiseShiftUnpredicatedFixed = 0x04208000, 3144 SVEBitwiseShiftUnpredicatedFMask = 0xFF20E000, 3145 SVEBitwiseShiftUnpredicatedMask = 0xFF20FC00, 3146 ASR_z_zw = SVEBitwiseShiftUnpredicatedFixed, 3147 LSR_z_zw = SVEBitwiseShiftUnpredicatedFixed | 0x00000400, 3148 LSL_z_zw = SVEBitwiseShiftUnpredicatedFixed | 0x00000C00, 3149 ASR_z_zi = SVEBitwiseShiftUnpredicatedFixed | 0x00001000, 3150 LSR_z_zi = SVEBitwiseShiftUnpredicatedFixed | 0x00001400, 3151 LSL_z_zi = SVEBitwiseShiftUnpredicatedFixed | 0x00001C00 3152}; 3153 3154enum SVEBroadcastBitmaskImmOp { 3155 SVEBroadcastBitmaskImmFixed = 0x05C00000, 3156 SVEBroadcastBitmaskImmFMask = 0xFFFC0000, 3157 SVEBroadcastBitmaskImmMask = 0xFFFC0000, 3158 DUPM_z_i = SVEBroadcastBitmaskImmFixed 3159}; 3160 3161enum SVEBroadcastFPImm_UnpredicatedOp { 3162 SVEBroadcastFPImm_UnpredicatedFixed = 0x2539C000, 3163 SVEBroadcastFPImm_UnpredicatedFMask = 0xFF39C000, 3164 SVEBroadcastFPImm_UnpredicatedMask = 0xFF3FE000, 3165 FDUP_z_i = SVEBroadcastFPImm_UnpredicatedFixed 3166}; 3167 3168enum SVEBroadcastGeneralRegisterOp { 3169 SVEBroadcastGeneralRegisterFixed = 0x05203800, 3170 SVEBroadcastGeneralRegisterFMask = 0xFF3FFC00, 3171 SVEBroadcastGeneralRegisterMask = 0xFF3FFC00, 3172 DUP_z_r = SVEBroadcastGeneralRegisterFixed 3173}; 3174 3175enum SVEBroadcastIndexElementOp { 3176 SVEBroadcastIndexElementFixed = 0x05202000, 3177 SVEBroadcastIndexElementFMask = 0xFF20FC00, 3178 SVEBroadcastIndexElementMask = 0xFF20FC00, 3179 DUP_z_zi = SVEBroadcastIndexElementFixed 3180}; 3181 3182enum SVEBroadcastIntImm_UnpredicatedOp { 3183 SVEBroadcastIntImm_UnpredicatedFixed = 0x2538C000, 3184 SVEBroadcastIntImm_UnpredicatedFMask = 0xFF39C000, 3185 SVEBroadcastIntImm_UnpredicatedMask = 0xFF3FC000, 3186 DUP_z_i = SVEBroadcastIntImm_UnpredicatedFixed 3187}; 3188 3189enum SVECompressActiveElementsOp { 3190 SVECompressActiveElementsFixed = 0x05A18000, 3191 SVECompressActiveElementsFMask = 0xFFBFE000, 3192 SVECompressActiveElementsMask = 0xFFBFE000, 3193 COMPACT_z_p_z = SVECompressActiveElementsFixed 3194}; 3195 3196enum SVEConditionallyBroadcastElementToVectorOp { 3197 SVEConditionallyBroadcastElementToVectorFixed = 0x05288000, 3198 SVEConditionallyBroadcastElementToVectorFMask = 0xFF3EE000, 3199 SVEConditionallyBroadcastElementToVectorMask = 0xFF3FE000, 3200 CLASTA_z_p_zz = SVEConditionallyBroadcastElementToVectorFixed, 3201 CLASTB_z_p_zz = SVEConditionallyBroadcastElementToVectorFixed | 0x00010000 3202}; 3203 3204enum SVEConditionallyExtractElementToGeneralRegisterOp { 3205 SVEConditionallyExtractElementToGeneralRegisterFixed = 0x0530A000, 3206 SVEConditionallyExtractElementToGeneralRegisterFMask = 0xFF3EE000, 3207 SVEConditionallyExtractElementToGeneralRegisterMask = 0xFF3FE000, 3208 CLASTA_r_p_z = SVEConditionallyExtractElementToGeneralRegisterFixed, 3209 CLASTB_r_p_z = SVEConditionallyExtractElementToGeneralRegisterFixed | 0x00010000 3210}; 3211 3212enum SVEConditionallyExtractElementToSIMDFPScalarOp { 3213 SVEConditionallyExtractElementToSIMDFPScalarFixed = 0x052A8000, 3214 SVEConditionallyExtractElementToSIMDFPScalarFMask = 0xFF3EE000, 3215 SVEConditionallyExtractElementToSIMDFPScalarMask = 0xFF3FE000, 3216 CLASTA_v_p_z = SVEConditionallyExtractElementToSIMDFPScalarFixed, 3217 CLASTB_v_p_z = SVEConditionallyExtractElementToSIMDFPScalarFixed | 0x00010000 3218}; 3219 3220enum SVEConditionallyTerminateScalarsOp { 3221 SVEConditionallyTerminateScalarsFixed = 0x25202000, 3222 SVEConditionallyTerminateScalarsFMask = 0xFF20FC0F, 3223 SVEConditionallyTerminateScalarsMask = 0xFFA0FC1F, 3224 CTERMEQ_rr = SVEConditionallyTerminateScalarsFixed | 0x00800000, 3225 CTERMNE_rr = SVEConditionallyTerminateScalarsFixed | 0x00800010 3226}; 3227 3228enum SVEConstructivePrefix_UnpredicatedOp { 3229 SVEConstructivePrefix_UnpredicatedFixed = 0x0420BC00, 3230 SVEConstructivePrefix_UnpredicatedFMask = 0xFF20FC00, 3231 SVEConstructivePrefix_UnpredicatedMask = 0xFFFFFC00, 3232 MOVPRFX_z_z = SVEConstructivePrefix_UnpredicatedFixed 3233}; 3234 3235enum SVEContiguousFirstFaultLoad_ScalarPlusScalarOp { 3236 SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed = 0xA4006000, 3237 SVEContiguousFirstFaultLoad_ScalarPlusScalarFMask = 0xFE00E000, 3238 SVEContiguousFirstFaultLoad_ScalarPlusScalarMask = 0xFFE0E000, 3239 LDFF1B_z_p_br_u8 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed, 3240 LDFF1B_z_p_br_u16 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00200000, 3241 LDFF1B_z_p_br_u32 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00400000, 3242 LDFF1B_z_p_br_u64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00600000, 3243 LDFF1SW_z_p_br_s64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00800000, 3244 LDFF1H_z_p_br_u16 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00A00000, 3245 LDFF1H_z_p_br_u32 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00C00000, 3246 LDFF1H_z_p_br_u64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00E00000, 3247 LDFF1SH_z_p_br_s64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01000000, 3248 LDFF1SH_z_p_br_s32 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01200000, 3249 LDFF1W_z_p_br_u32 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01400000, 3250 LDFF1W_z_p_br_u64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01600000, 3251 LDFF1SB_z_p_br_s64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01800000, 3252 LDFF1SB_z_p_br_s32 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01A00000, 3253 LDFF1SB_z_p_br_s16 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01C00000, 3254 LDFF1D_z_p_br_u64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01E00000 3255}; 3256 3257enum SVEContiguousLoad_ScalarPlusImmOp { 3258 SVEContiguousLoad_ScalarPlusImmFixed = 0xA400A000, 3259 SVEContiguousLoad_ScalarPlusImmFMask = 0xFE10E000, 3260 SVEContiguousLoad_ScalarPlusImmMask = 0xFFF0E000, 3261 LD1B_z_p_bi_u8 = SVEContiguousLoad_ScalarPlusImmFixed, 3262 LD1B_z_p_bi_u16 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00200000, 3263 LD1B_z_p_bi_u32 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00400000, 3264 LD1B_z_p_bi_u64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00600000, 3265 LD1SW_z_p_bi_s64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00800000, 3266 LD1H_z_p_bi_u16 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00A00000, 3267 LD1H_z_p_bi_u32 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00C00000, 3268 LD1H_z_p_bi_u64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00E00000, 3269 LD1SH_z_p_bi_s64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01000000, 3270 LD1SH_z_p_bi_s32 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01200000, 3271 LD1W_z_p_bi_u32 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01400000, 3272 LD1W_z_p_bi_u64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01600000, 3273 LD1SB_z_p_bi_s64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01800000, 3274 LD1SB_z_p_bi_s32 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01A00000, 3275 LD1SB_z_p_bi_s16 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01C00000, 3276 LD1D_z_p_bi_u64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01E00000 3277}; 3278 3279enum SVEContiguousLoad_ScalarPlusScalarOp { 3280 SVEContiguousLoad_ScalarPlusScalarFixed = 0xA4004000, 3281 SVEContiguousLoad_ScalarPlusScalarFMask = 0xFE00E000, 3282 SVEContiguousLoad_ScalarPlusScalarMask = 0xFFE0E000, 3283 LD1B_z_p_br_u8 = SVEContiguousLoad_ScalarPlusScalarFixed, 3284 LD1B_z_p_br_u16 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00200000, 3285 LD1B_z_p_br_u32 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00400000, 3286 LD1B_z_p_br_u64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00600000, 3287 LD1SW_z_p_br_s64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00800000, 3288 LD1H_z_p_br_u16 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00A00000, 3289 LD1H_z_p_br_u32 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00C00000, 3290 LD1H_z_p_br_u64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00E00000, 3291 LD1SH_z_p_br_s64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01000000, 3292 LD1SH_z_p_br_s32 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01200000, 3293 LD1W_z_p_br_u32 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01400000, 3294 LD1W_z_p_br_u64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01600000, 3295 LD1SB_z_p_br_s64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01800000, 3296 LD1SB_z_p_br_s32 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01A00000, 3297 LD1SB_z_p_br_s16 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01C00000, 3298 LD1D_z_p_br_u64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01E00000 3299}; 3300 3301enum SVEContiguousNonFaultLoad_ScalarPlusImmOp { 3302 SVEContiguousNonFaultLoad_ScalarPlusImmFixed = 0xA410A000, 3303 SVEContiguousNonFaultLoad_ScalarPlusImmFMask = 0xFE10E000, 3304 SVEContiguousNonFaultLoad_ScalarPlusImmMask = 0xFFF0E000, 3305 LDNF1B_z_p_bi_u8 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed, 3306 LDNF1B_z_p_bi_u16 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00200000, 3307 LDNF1B_z_p_bi_u32 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00400000, 3308 LDNF1B_z_p_bi_u64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00600000, 3309 LDNF1SW_z_p_bi_s64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00800000, 3310 LDNF1H_z_p_bi_u16 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00A00000, 3311 LDNF1H_z_p_bi_u32 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00C00000, 3312 LDNF1H_z_p_bi_u64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00E00000, 3313 LDNF1SH_z_p_bi_s64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01000000, 3314 LDNF1SH_z_p_bi_s32 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01200000, 3315 LDNF1W_z_p_bi_u32 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01400000, 3316 LDNF1W_z_p_bi_u64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01600000, 3317 LDNF1SB_z_p_bi_s64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01800000, 3318 LDNF1SB_z_p_bi_s32 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01A00000, 3319 LDNF1SB_z_p_bi_s16 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01C00000, 3320 LDNF1D_z_p_bi_u64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01E00000 3321}; 3322 3323enum SVEContiguousNonTemporalLoad_ScalarPlusImmOp { 3324 SVEContiguousNonTemporalLoad_ScalarPlusImmFixed = 0xA400E000, 3325 SVEContiguousNonTemporalLoad_ScalarPlusImmFMask = 0xFE70E000, 3326 SVEContiguousNonTemporalLoad_ScalarPlusImmMask = 0xFFF0E000, 3327 LDNT1B_z_p_bi_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusImmFixed, 3328 LDNT1H_z_p_bi_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusImmFixed | 0x00800000, 3329 LDNT1W_z_p_bi_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusImmFixed | 0x01000000, 3330 LDNT1D_z_p_bi_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusImmFixed | 0x01800000 3331}; 3332 3333enum SVEContiguousNonTemporalLoad_ScalarPlusScalarOp { 3334 SVEContiguousNonTemporalLoad_ScalarPlusScalarFixed = 0xA400C000, 3335 SVEContiguousNonTemporalLoad_ScalarPlusScalarFMask = 0xFE60E000, 3336 SVEContiguousNonTemporalLoad_ScalarPlusScalarMask = 0xFFE0E000, 3337 LDNT1B_z_p_br_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusScalarFixed, 3338 LDNT1H_z_p_br_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusScalarFixed | 0x00800000, 3339 LDNT1W_z_p_br_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusScalarFixed | 0x01000000, 3340 LDNT1D_z_p_br_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusScalarFixed | 0x01800000 3341}; 3342 3343enum SVEContiguousNonTemporalStore_ScalarPlusImmOp { 3344 SVEContiguousNonTemporalStore_ScalarPlusImmFixed = 0xE410E000, 3345 SVEContiguousNonTemporalStore_ScalarPlusImmFMask = 0xFE70E000, 3346 SVEContiguousNonTemporalStore_ScalarPlusImmMask = 0xFFF0E000, 3347 STNT1B_z_p_bi_contiguous = SVEContiguousNonTemporalStore_ScalarPlusImmFixed, 3348 STNT1H_z_p_bi_contiguous = SVEContiguousNonTemporalStore_ScalarPlusImmFixed | 0x00800000, 3349 STNT1W_z_p_bi_contiguous = SVEContiguousNonTemporalStore_ScalarPlusImmFixed | 0x01000000, 3350 STNT1D_z_p_bi_contiguous = SVEContiguousNonTemporalStore_ScalarPlusImmFixed | 0x01800000 3351}; 3352 3353enum SVEContiguousNonTemporalStore_ScalarPlusScalarOp { 3354 SVEContiguousNonTemporalStore_ScalarPlusScalarFixed = 0xE4006000, 3355 SVEContiguousNonTemporalStore_ScalarPlusScalarFMask = 0xFE60E000, 3356 SVEContiguousNonTemporalStore_ScalarPlusScalarMask = 0xFFE0E000, 3357 STNT1B_z_p_br_contiguous = SVEContiguousNonTemporalStore_ScalarPlusScalarFixed, 3358 STNT1H_z_p_br_contiguous = SVEContiguousNonTemporalStore_ScalarPlusScalarFixed | 0x00800000, 3359 STNT1W_z_p_br_contiguous = SVEContiguousNonTemporalStore_ScalarPlusScalarFixed | 0x01000000, 3360 STNT1D_z_p_br_contiguous = SVEContiguousNonTemporalStore_ScalarPlusScalarFixed | 0x01800000 3361}; 3362 3363enum SVEContiguousPrefetch_ScalarPlusImmOp { 3364 SVEContiguousPrefetch_ScalarPlusImmFixed = 0x85C00000, 3365 SVEContiguousPrefetch_ScalarPlusImmFMask = 0xFFC08010, 3366 SVEContiguousPrefetch_ScalarPlusImmMask = 0xFFC0E010, 3367 PRFB_i_p_bi_s = SVEContiguousPrefetch_ScalarPlusImmFixed, 3368 PRFH_i_p_bi_s = SVEContiguousPrefetch_ScalarPlusImmFixed | 0x00002000, 3369 PRFW_i_p_bi_s = SVEContiguousPrefetch_ScalarPlusImmFixed | 0x00004000, 3370 PRFD_i_p_bi_s = SVEContiguousPrefetch_ScalarPlusImmFixed | 0x00006000 3371}; 3372 3373enum SVEContiguousPrefetch_ScalarPlusScalarOp { 3374 SVEContiguousPrefetch_ScalarPlusScalarFixed = 0x8400C000, 3375 SVEContiguousPrefetch_ScalarPlusScalarFMask = 0xFE60E010, 3376 SVEContiguousPrefetch_ScalarPlusScalarMask = 0xFFE0E010, 3377 PRFB_i_p_br_s = SVEContiguousPrefetch_ScalarPlusScalarFixed, 3378 PRFH_i_p_br_s = SVEContiguousPrefetch_ScalarPlusScalarFixed | 0x00800000, 3379 PRFW_i_p_br_s = SVEContiguousPrefetch_ScalarPlusScalarFixed | 0x01000000, 3380 PRFD_i_p_br_s = SVEContiguousPrefetch_ScalarPlusScalarFixed | 0x01800000 3381}; 3382 3383enum SVEContiguousStore_ScalarPlusImmOp { 3384 SVEContiguousStore_ScalarPlusImmFixed = 0xE400E000, 3385 SVEContiguousStore_ScalarPlusImmFMask = 0xFE10E000, 3386 SVEContiguousStore_ScalarPlusImmMask = 0xFF90E000, 3387 ST1B_z_p_bi = SVEContiguousStore_ScalarPlusImmFixed, 3388 ST1H_z_p_bi = SVEContiguousStore_ScalarPlusImmFixed | 0x00800000, 3389 ST1W_z_p_bi = SVEContiguousStore_ScalarPlusImmFixed | 0x01000000, 3390 ST1D_z_p_bi = SVEContiguousStore_ScalarPlusImmFixed | 0x01800000 3391}; 3392 3393enum SVEContiguousStore_ScalarPlusScalarOp { 3394 SVEContiguousStore_ScalarPlusScalarFixed = 0xE4004000, 3395 SVEContiguousStore_ScalarPlusScalarFMask = 0xFE00E000, 3396 SVEContiguousStore_ScalarPlusScalarMask = 0xFF80E000, 3397 ST1B_z_p_br = SVEContiguousStore_ScalarPlusScalarFixed, 3398 ST1H_z_p_br = SVEContiguousStore_ScalarPlusScalarFixed | 0x00800000, 3399 ST1W_z_p_br = SVEContiguousStore_ScalarPlusScalarFixed | 0x01000000, 3400 ST1D_z_p_br = SVEContiguousStore_ScalarPlusScalarFixed | 0x01800000 3401}; 3402 3403enum SVECopyFPImm_PredicatedOp { 3404 SVECopyFPImm_PredicatedFixed = 0x0510C000, 3405 SVECopyFPImm_PredicatedFMask = 0xFF30E000, 3406 SVECopyFPImm_PredicatedMask = 0xFF30E000, 3407 FCPY_z_p_i = SVECopyFPImm_PredicatedFixed 3408}; 3409 3410enum SVECopyGeneralRegisterToVector_PredicatedOp { 3411 SVECopyGeneralRegisterToVector_PredicatedFixed = 0x0528A000, 3412 SVECopyGeneralRegisterToVector_PredicatedFMask = 0xFF3FE000, 3413 SVECopyGeneralRegisterToVector_PredicatedMask = 0xFF3FE000, 3414 CPY_z_p_r = SVECopyGeneralRegisterToVector_PredicatedFixed 3415}; 3416 3417enum SVECopyIntImm_PredicatedOp { 3418 SVECopyIntImm_PredicatedFixed = 0x05100000, 3419 SVECopyIntImm_PredicatedFMask = 0xFF308000, 3420 SVECopyIntImm_PredicatedMask = 0xFF308000, 3421 CPY_z_p_i = SVECopyIntImm_PredicatedFixed 3422}; 3423 3424enum SVECopySIMDFPScalarRegisterToVector_PredicatedOp { 3425 SVECopySIMDFPScalarRegisterToVector_PredicatedFixed = 0x05208000, 3426 SVECopySIMDFPScalarRegisterToVector_PredicatedFMask = 0xFF3FE000, 3427 SVECopySIMDFPScalarRegisterToVector_PredicatedMask = 0xFF3FE000, 3428 CPY_z_p_v = SVECopySIMDFPScalarRegisterToVector_PredicatedFixed 3429}; 3430 3431enum SVEElementCountOp { 3432 SVEElementCountFixed = 0x0420E000, 3433 SVEElementCountFMask = 0xFF30F800, 3434 SVEElementCountMask = 0xFFF0FC00, 3435 CNTB_r_s = SVEElementCountFixed, 3436 CNTH_r_s = SVEElementCountFixed | 0x00400000, 3437 CNTW_r_s = SVEElementCountFixed | 0x00800000, 3438 CNTD_r_s = SVEElementCountFixed | 0x00C00000 3439}; 3440 3441enum SVEExtractElementToGeneralRegisterOp { 3442 SVEExtractElementToGeneralRegisterFixed = 0x0520A000, 3443 SVEExtractElementToGeneralRegisterFMask = 0xFF3EE000, 3444 SVEExtractElementToGeneralRegisterMask = 0xFF3FE000, 3445 LASTA_r_p_z = SVEExtractElementToGeneralRegisterFixed, 3446 LASTB_r_p_z = SVEExtractElementToGeneralRegisterFixed | 0x00010000 3447}; 3448 3449enum SVEExtractElementToSIMDFPScalarRegisterOp { 3450 SVEExtractElementToSIMDFPScalarRegisterFixed = 0x05228000, 3451 SVEExtractElementToSIMDFPScalarRegisterFMask = 0xFF3EE000, 3452 SVEExtractElementToSIMDFPScalarRegisterMask = 0xFF3FE000, 3453 LASTA_v_p_z = SVEExtractElementToSIMDFPScalarRegisterFixed, 3454 LASTB_v_p_z = SVEExtractElementToSIMDFPScalarRegisterFixed | 0x00010000 3455}; 3456 3457enum SVEFFRInitialiseOp { 3458 SVEFFRInitialiseFixed = 0x252C9000, 3459 SVEFFRInitialiseFMask = 0xFF3FFFFF, 3460 SVEFFRInitialiseMask = 0xFFFFFFFF, 3461 SETFFR_f = SVEFFRInitialiseFixed 3462}; 3463 3464enum SVEFFRWriteFromPredicateOp { 3465 SVEFFRWriteFromPredicateFixed = 0x25289000, 3466 SVEFFRWriteFromPredicateFMask = 0xFF3FFE1F, 3467 SVEFFRWriteFromPredicateMask = 0xFFFFFE1F, 3468 WRFFR_f_p = SVEFFRWriteFromPredicateFixed 3469}; 3470 3471enum SVEFPAccumulatingReductionOp { 3472 SVEFPAccumulatingReductionFixed = 0x65182000, 3473 SVEFPAccumulatingReductionFMask = 0xFF38E000, 3474 SVEFPAccumulatingReductionMask = 0xFF3FE000, 3475 FADDA_v_p_z = SVEFPAccumulatingReductionFixed 3476}; 3477 3478enum SVEFPArithmeticUnpredicatedOp { 3479 SVEFPArithmeticUnpredicatedFixed = 0x65000000, 3480 SVEFPArithmeticUnpredicatedFMask = 0xFF20E000, 3481 SVEFPArithmeticUnpredicatedMask = 0xFF20FC00, 3482 FADD_z_zz = SVEFPArithmeticUnpredicatedFixed, 3483 FSUB_z_zz = SVEFPArithmeticUnpredicatedFixed | 0x00000400, 3484 FMUL_z_zz = SVEFPArithmeticUnpredicatedFixed | 0x00000800, 3485 FTSMUL_z_zz = SVEFPArithmeticUnpredicatedFixed | 0x00000C00, 3486 FRECPS_z_zz = SVEFPArithmeticUnpredicatedFixed | 0x00001800, 3487 FRSQRTS_z_zz = SVEFPArithmeticUnpredicatedFixed | 0x00001C00 3488}; 3489 3490enum SVEFPArithmeticWithImm_PredicatedOp { 3491 SVEFPArithmeticWithImm_PredicatedFixed = 0x65188000, 3492 SVEFPArithmeticWithImm_PredicatedFMask = 0xFF38E3C0, 3493 SVEFPArithmeticWithImm_PredicatedMask = 0xFF3FE3C0, 3494 FADD_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed, 3495 FSUB_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00010000, 3496 FMUL_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00020000, 3497 FSUBR_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00030000, 3498 FMAXNM_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00040000, 3499 FMINNM_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00050000, 3500 FMAX_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00060000, 3501 FMIN_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00070000 3502}; 3503 3504enum SVEFPArithmetic_PredicatedOp { 3505 SVEFPArithmetic_PredicatedFixed = 0x65008000, 3506 SVEFPArithmetic_PredicatedFMask = 0xFF30E000, 3507 SVEFPArithmetic_PredicatedMask = 0xFF3FE000, 3508 FADD_z_p_zz = SVEFPArithmetic_PredicatedFixed, 3509 FSUB_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00010000, 3510 FMUL_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00020000, 3511 FSUBR_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00030000, 3512 FMAXNM_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00040000, 3513 FMINNM_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00050000, 3514 FMAX_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00060000, 3515 FMIN_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00070000, 3516 FABD_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00080000, 3517 FSCALE_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00090000, 3518 FMULX_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x000A0000, 3519 FDIVR_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x000C0000, 3520 FDIV_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x000D0000 3521}; 3522 3523enum SVEFPCompareVectorsOp { 3524 SVEFPCompareVectorsFixed = 0x65004000, 3525 SVEFPCompareVectorsFMask = 0xFF204000, 3526 SVEFPCompareVectorsMask = 0xFF20E010, 3527 FCMGE_p_p_zz = SVEFPCompareVectorsFixed, 3528 FCMGT_p_p_zz = SVEFPCompareVectorsFixed | 0x00000010, 3529 FCMEQ_p_p_zz = SVEFPCompareVectorsFixed | 0x00002000, 3530 FCMNE_p_p_zz = SVEFPCompareVectorsFixed | 0x00002010, 3531 FCMUO_p_p_zz = SVEFPCompareVectorsFixed | 0x00008000, 3532 FACGE_p_p_zz = SVEFPCompareVectorsFixed | 0x00008010, 3533 FACGT_p_p_zz = SVEFPCompareVectorsFixed | 0x0000A010 3534}; 3535 3536enum SVEFPCompareWithZeroOp { 3537 SVEFPCompareWithZeroFixed = 0x65102000, 3538 SVEFPCompareWithZeroFMask = 0xFF38E000, 3539 SVEFPCompareWithZeroMask = 0xFF3FE010, 3540 FCMGE_p_p_z0 = SVEFPCompareWithZeroFixed, 3541 FCMGT_p_p_z0 = SVEFPCompareWithZeroFixed | 0x00000010, 3542 FCMLT_p_p_z0 = SVEFPCompareWithZeroFixed | 0x00010000, 3543 FCMLE_p_p_z0 = SVEFPCompareWithZeroFixed | 0x00010010, 3544 FCMEQ_p_p_z0 = SVEFPCompareWithZeroFixed | 0x00020000, 3545 FCMNE_p_p_z0 = SVEFPCompareWithZeroFixed | 0x00030000 3546}; 3547 3548enum SVEFPComplexAdditionOp { 3549 SVEFPComplexAdditionFixed = 0x64008000, 3550 SVEFPComplexAdditionFMask = 0xFF3EE000, 3551 SVEFPComplexAdditionMask = 0xFF3EE000, 3552 FCADD_z_p_zz = SVEFPComplexAdditionFixed 3553}; 3554 3555enum SVEFPComplexMulAddOp { 3556 SVEFPComplexMulAddFixed = 0x64000000, 3557 SVEFPComplexMulAddFMask = 0xFF208000, 3558 SVEFPComplexMulAddMask = 0xFF208000, 3559 FCMLA_z_p_zzz = SVEFPComplexMulAddFixed 3560}; 3561 3562enum SVEFPComplexMulAddIndexOp { 3563 SVEFPComplexMulAddIndexFixed = 0x64201000, 3564 SVEFPComplexMulAddIndexFMask = 0xFF20F000, 3565 SVEFPComplexMulAddIndexMask = 0xFFE0F000, 3566 FCMLA_z_zzzi_h = SVEFPComplexMulAddIndexFixed | 0x00800000, 3567 FCMLA_z_zzzi_s = SVEFPComplexMulAddIndexFixed | 0x00C00000 3568}; 3569 3570enum SVEFPConvertPrecisionOp { 3571 SVEFPConvertPrecisionFixed = 0x6508A000, 3572 SVEFPConvertPrecisionFMask = 0xFF3CE000, 3573 SVEFPConvertPrecisionMask = 0xFFFFE000, 3574 FCVT_z_p_z_s2h = SVEFPConvertPrecisionFixed | 0x00800000, 3575 FCVT_z_p_z_h2s = SVEFPConvertPrecisionFixed | 0x00810000, 3576 FCVT_z_p_z_d2h = SVEFPConvertPrecisionFixed | 0x00C00000, 3577 FCVT_z_p_z_h2d = SVEFPConvertPrecisionFixed | 0x00C10000, 3578 FCVT_z_p_z_d2s = SVEFPConvertPrecisionFixed | 0x00C20000, 3579 FCVT_z_p_z_s2d = SVEFPConvertPrecisionFixed | 0x00C30000 3580}; 3581 3582enum SVEFPConvertToIntOp { 3583 SVEFPConvertToIntFixed = 0x6518A000, 3584 SVEFPConvertToIntFMask = 0xFF38E000, 3585 SVEFPConvertToIntMask = 0xFFFFE000, 3586 FCVTZS_z_p_z_fp162h = SVEFPConvertToIntFixed | 0x00420000, 3587 FCVTZU_z_p_z_fp162h = SVEFPConvertToIntFixed | 0x00430000, 3588 FCVTZS_z_p_z_fp162w = SVEFPConvertToIntFixed | 0x00440000, 3589 FCVTZU_z_p_z_fp162w = SVEFPConvertToIntFixed | 0x00450000, 3590 FCVTZS_z_p_z_fp162x = SVEFPConvertToIntFixed | 0x00460000, 3591 FCVTZU_z_p_z_fp162x = SVEFPConvertToIntFixed | 0x00470000, 3592 FCVTZS_z_p_z_s2w = SVEFPConvertToIntFixed | 0x00840000, 3593 FCVTZU_z_p_z_s2w = SVEFPConvertToIntFixed | 0x00850000, 3594 FCVTZS_z_p_z_d2w = SVEFPConvertToIntFixed | 0x00C00000, 3595 FCVTZU_z_p_z_d2w = SVEFPConvertToIntFixed | 0x00C10000, 3596 FCVTZS_z_p_z_s2x = SVEFPConvertToIntFixed | 0x00C40000, 3597 FCVTZU_z_p_z_s2x = SVEFPConvertToIntFixed | 0x00C50000, 3598 FCVTZS_z_p_z_d2x = SVEFPConvertToIntFixed | 0x00C60000, 3599 FCVTZU_z_p_z_d2x = SVEFPConvertToIntFixed | 0x00C70000 3600}; 3601 3602enum SVEFPExponentialAcceleratorOp { 3603 SVEFPExponentialAcceleratorFixed = 0x0420B800, 3604 SVEFPExponentialAcceleratorFMask = 0xFF20FC00, 3605 SVEFPExponentialAcceleratorMask = 0xFF3FFC00, 3606 FEXPA_z_z = SVEFPExponentialAcceleratorFixed 3607}; 3608 3609enum SVEFPFastReductionOp { 3610 SVEFPFastReductionFixed = 0x65002000, 3611 SVEFPFastReductionFMask = 0xFF38E000, 3612 SVEFPFastReductionMask = 0xFF3FE000, 3613 FADDV_v_p_z = SVEFPFastReductionFixed, 3614 FMAXNMV_v_p_z = SVEFPFastReductionFixed | 0x00040000, 3615 FMINNMV_v_p_z = SVEFPFastReductionFixed | 0x00050000, 3616 FMAXV_v_p_z = SVEFPFastReductionFixed | 0x00060000, 3617 FMINV_v_p_z = SVEFPFastReductionFixed | 0x00070000 3618}; 3619 3620enum SVEFPMulAddOp { 3621 SVEFPMulAddFixed = 0x65200000, 3622 SVEFPMulAddFMask = 0xFF200000, 3623 SVEFPMulAddMask = 0xFF20E000, 3624 FMLA_z_p_zzz = SVEFPMulAddFixed, 3625 FMLS_z_p_zzz = SVEFPMulAddFixed | 0x00002000, 3626 FNMLA_z_p_zzz = SVEFPMulAddFixed | 0x00004000, 3627 FNMLS_z_p_zzz = SVEFPMulAddFixed | 0x00006000, 3628 FMAD_z_p_zzz = SVEFPMulAddFixed | 0x00008000, 3629 FMSB_z_p_zzz = SVEFPMulAddFixed | 0x0000A000, 3630 FNMAD_z_p_zzz = SVEFPMulAddFixed | 0x0000C000, 3631 FNMSB_z_p_zzz = SVEFPMulAddFixed | 0x0000E000 3632}; 3633 3634enum SVEFPMulAddIndexOp { 3635 SVEFPMulAddIndexFixed = 0x64200000, 3636 SVEFPMulAddIndexFMask = 0xFF20F800, 3637 SVEFPMulAddIndexMask = 0xFFE0FC00, 3638 FMLA_z_zzzi_h = SVEFPMulAddIndexFixed, 3639 FMLA_z_zzzi_h_i3h = FMLA_z_zzzi_h | 0x00400000, 3640 FMLS_z_zzzi_h = SVEFPMulAddIndexFixed | 0x00000400, 3641 FMLS_z_zzzi_h_i3h = FMLS_z_zzzi_h | 0x00400000, 3642 FMLA_z_zzzi_s = SVEFPMulAddIndexFixed | 0x00800000, 3643 FMLS_z_zzzi_s = SVEFPMulAddIndexFixed | 0x00800400, 3644 FMLA_z_zzzi_d = SVEFPMulAddIndexFixed | 0x00C00000, 3645 FMLS_z_zzzi_d = SVEFPMulAddIndexFixed | 0x00C00400 3646}; 3647 3648enum SVEFPMulIndexOp { 3649 SVEFPMulIndexFixed = 0x64202000, 3650 SVEFPMulIndexFMask = 0xFF20FC00, 3651 SVEFPMulIndexMask = 0xFFE0FC00, 3652 FMUL_z_zzi_h = SVEFPMulIndexFixed, 3653 FMUL_z_zzi_h_i3h = FMUL_z_zzi_h | 0x00400000, 3654 FMUL_z_zzi_s = SVEFPMulIndexFixed | 0x00800000, 3655 FMUL_z_zzi_d = SVEFPMulIndexFixed | 0x00C00000 3656}; 3657 3658enum SVEFPRoundToIntegralValueOp { 3659 SVEFPRoundToIntegralValueFixed = 0x6500A000, 3660 SVEFPRoundToIntegralValueFMask = 0xFF38E000, 3661 SVEFPRoundToIntegralValueMask = 0xFF3FE000, 3662 FRINTN_z_p_z = SVEFPRoundToIntegralValueFixed, 3663 FRINTP_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00010000, 3664 FRINTM_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00020000, 3665 FRINTZ_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00030000, 3666 FRINTA_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00040000, 3667 FRINTX_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00060000, 3668 FRINTI_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00070000 3669}; 3670 3671enum SVEFPTrigMulAddCoefficientOp { 3672 SVEFPTrigMulAddCoefficientFixed = 0x65108000, 3673 SVEFPTrigMulAddCoefficientFMask = 0xFF38FC00, 3674 SVEFPTrigMulAddCoefficientMask = 0xFF38FC00, 3675 FTMAD_z_zzi = SVEFPTrigMulAddCoefficientFixed 3676}; 3677 3678enum SVEFPTrigSelectCoefficientOp { 3679 SVEFPTrigSelectCoefficientFixed = 0x0420B000, 3680 SVEFPTrigSelectCoefficientFMask = 0xFF20F800, 3681 SVEFPTrigSelectCoefficientMask = 0xFF20FC00, 3682 FTSSEL_z_zz = SVEFPTrigSelectCoefficientFixed 3683}; 3684 3685enum SVEFPUnaryOpOp { 3686 SVEFPUnaryOpFixed = 0x650CA000, 3687 SVEFPUnaryOpFMask = 0xFF3CE000, 3688 SVEFPUnaryOpMask = 0xFF3FE000, 3689 FRECPX_z_p_z = SVEFPUnaryOpFixed, 3690 FSQRT_z_p_z = SVEFPUnaryOpFixed | 0x00010000 3691}; 3692 3693enum SVEFPUnaryOpUnpredicatedOp { 3694 SVEFPUnaryOpUnpredicatedFixed = 0x65083000, 3695 SVEFPUnaryOpUnpredicatedFMask = 0xFF38F000, 3696 SVEFPUnaryOpUnpredicatedMask = 0xFF3FFC00, 3697 FRECPE_z_z = SVEFPUnaryOpUnpredicatedFixed | 0x00060000, 3698 FRSQRTE_z_z = SVEFPUnaryOpUnpredicatedFixed | 0x00070000 3699}; 3700 3701enum SVEIncDecByPredicateCountOp { 3702 SVEIncDecByPredicateCountFixed = 0x25288000, 3703 SVEIncDecByPredicateCountFMask = 0xFF38F000, 3704 SVEIncDecByPredicateCountMask = 0xFF3FFE00, 3705 SQINCP_z_p_z = SVEIncDecByPredicateCountFixed, 3706 SQINCP_r_p_r_sx = SVEIncDecByPredicateCountFixed | 0x00000800, 3707 SQINCP_r_p_r_x = SVEIncDecByPredicateCountFixed | 0x00000C00, 3708 UQINCP_z_p_z = SVEIncDecByPredicateCountFixed | 0x00010000, 3709 UQINCP_r_p_r_uw = SVEIncDecByPredicateCountFixed | 0x00010800, 3710 UQINCP_r_p_r_x = SVEIncDecByPredicateCountFixed | 0x00010C00, 3711 SQDECP_z_p_z = SVEIncDecByPredicateCountFixed | 0x00020000, 3712 SQDECP_r_p_r_sx = SVEIncDecByPredicateCountFixed | 0x00020800, 3713 SQDECP_r_p_r_x = SVEIncDecByPredicateCountFixed | 0x00020C00, 3714 UQDECP_z_p_z = SVEIncDecByPredicateCountFixed | 0x00030000, 3715 UQDECP_r_p_r_uw = SVEIncDecByPredicateCountFixed | 0x00030800, 3716 UQDECP_r_p_r_x = SVEIncDecByPredicateCountFixed | 0x00030C00, 3717 INCP_z_p_z = SVEIncDecByPredicateCountFixed | 0x00040000, 3718 INCP_r_p_r = SVEIncDecByPredicateCountFixed | 0x00040800, 3719 DECP_z_p_z = SVEIncDecByPredicateCountFixed | 0x00050000, 3720 DECP_r_p_r = SVEIncDecByPredicateCountFixed | 0x00050800 3721}; 3722 3723enum SVEIncDecRegisterByElementCountOp { 3724 SVEIncDecRegisterByElementCountFixed = 0x0430E000, 3725 SVEIncDecRegisterByElementCountFMask = 0xFF30F800, 3726 SVEIncDecRegisterByElementCountMask = 0xFFF0FC00, 3727 INCB_r_rs = SVEIncDecRegisterByElementCountFixed, 3728 DECB_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00000400, 3729 INCH_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00400000, 3730 DECH_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00400400, 3731 INCW_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00800000, 3732 DECW_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00800400, 3733 INCD_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00C00000, 3734 DECD_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00C00400 3735}; 3736 3737enum SVEIncDecVectorByElementCountOp { 3738 SVEIncDecVectorByElementCountFixed = 0x0430C000, 3739 SVEIncDecVectorByElementCountFMask = 0xFF30F800, 3740 SVEIncDecVectorByElementCountMask = 0xFFF0FC00, 3741 INCH_z_zs = SVEIncDecVectorByElementCountFixed | 0x00400000, 3742 DECH_z_zs = SVEIncDecVectorByElementCountFixed | 0x00400400, 3743 INCW_z_zs = SVEIncDecVectorByElementCountFixed | 0x00800000, 3744 DECW_z_zs = SVEIncDecVectorByElementCountFixed | 0x00800400, 3745 INCD_z_zs = SVEIncDecVectorByElementCountFixed | 0x00C00000, 3746 DECD_z_zs = SVEIncDecVectorByElementCountFixed | 0x00C00400 3747}; 3748 3749enum SVEIndexGenerationOp { 3750 SVEIndexGenerationFixed = 0x04204000, 3751 SVEIndexGenerationFMask = 0xFF20F000, 3752 SVEIndexGenerationMask = 0xFF20FC00, 3753 INDEX_z_ii = SVEIndexGenerationFixed, 3754 INDEX_z_ri = SVEIndexGenerationFixed | 0x00000400, 3755 INDEX_z_ir = SVEIndexGenerationFixed | 0x00000800, 3756 INDEX_z_rr = SVEIndexGenerationFixed | 0x00000C00 3757}; 3758 3759enum SVEInsertGeneralRegisterOp { 3760 SVEInsertGeneralRegisterFixed = 0x05243800, 3761 SVEInsertGeneralRegisterFMask = 0xFF3FFC00, 3762 SVEInsertGeneralRegisterMask = 0xFF3FFC00, 3763 INSR_z_r = SVEInsertGeneralRegisterFixed 3764}; 3765 3766enum SVEInsertSIMDFPScalarRegisterOp { 3767 SVEInsertSIMDFPScalarRegisterFixed = 0x05343800, 3768 SVEInsertSIMDFPScalarRegisterFMask = 0xFF3FFC00, 3769 SVEInsertSIMDFPScalarRegisterMask = 0xFF3FFC00, 3770 INSR_z_v = SVEInsertSIMDFPScalarRegisterFixed 3771}; 3772 3773enum SVEIntAddSubtractImm_UnpredicatedOp { 3774 SVEIntAddSubtractImm_UnpredicatedFixed = 0x2520C000, 3775 SVEIntAddSubtractImm_UnpredicatedFMask = 0xFF38C000, 3776 SVEIntAddSubtractImm_UnpredicatedMask = 0xFF3FC000, 3777 ADD_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed, 3778 SUB_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00010000, 3779 SUBR_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00030000, 3780 SQADD_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00040000, 3781 UQADD_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00050000, 3782 SQSUB_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00060000, 3783 UQSUB_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00070000 3784}; 3785 3786enum SVEIntAddSubtractVectors_PredicatedOp { 3787 SVEIntAddSubtractVectors_PredicatedFixed = 0x04000000, 3788 SVEIntAddSubtractVectors_PredicatedFMask = 0xFF38E000, 3789 SVEIntAddSubtractVectors_PredicatedMask = 0xFF3FE000, 3790 ADD_z_p_zz = SVEIntAddSubtractVectors_PredicatedFixed, 3791 SUB_z_p_zz = SVEIntAddSubtractVectors_PredicatedFixed | 0x00010000, 3792 SUBR_z_p_zz = SVEIntAddSubtractVectors_PredicatedFixed | 0x00030000 3793}; 3794 3795enum SVEIntArithmeticUnpredicatedOp { 3796 SVEIntArithmeticUnpredicatedFixed = 0x04200000, 3797 SVEIntArithmeticUnpredicatedFMask = 0xFF20E000, 3798 SVEIntArithmeticUnpredicatedMask = 0xFF20FC00, 3799 ADD_z_zz = SVEIntArithmeticUnpredicatedFixed, 3800 SUB_z_zz = SVEIntArithmeticUnpredicatedFixed | 0x00000400, 3801 SQADD_z_zz = SVEIntArithmeticUnpredicatedFixed | 0x00001000, 3802 UQADD_z_zz = SVEIntArithmeticUnpredicatedFixed | 0x00001400, 3803 SQSUB_z_zz = SVEIntArithmeticUnpredicatedFixed | 0x00001800, 3804 UQSUB_z_zz = SVEIntArithmeticUnpredicatedFixed | 0x00001C00 3805}; 3806 3807enum SVEIntCompareScalarCountAndLimitOp { 3808 SVEIntCompareScalarCountAndLimitFixed = 0x25200000, 3809 SVEIntCompareScalarCountAndLimitFMask = 0xFF20E000, 3810 SVEIntCompareScalarCountAndLimitMask = 0xFF20EC10, 3811 WHILELT_p_p_rr = SVEIntCompareScalarCountAndLimitFixed | 0x00000400, 3812 WHILELE_p_p_rr = SVEIntCompareScalarCountAndLimitFixed | 0x00000410, 3813 WHILELO_p_p_rr = SVEIntCompareScalarCountAndLimitFixed | 0x00000C00, 3814 WHILELS_p_p_rr = SVEIntCompareScalarCountAndLimitFixed | 0x00000C10 3815}; 3816 3817enum SVEIntCompareSignedImmOp { 3818 SVEIntCompareSignedImmFixed = 0x25000000, 3819 SVEIntCompareSignedImmFMask = 0xFF204000, 3820 SVEIntCompareSignedImmMask = 0xFF20E010, 3821 CMPGE_p_p_zi = SVEIntCompareSignedImmFixed, 3822 CMPGT_p_p_zi = SVEIntCompareSignedImmFixed | 0x00000010, 3823 CMPLT_p_p_zi = SVEIntCompareSignedImmFixed | 0x00002000, 3824 CMPLE_p_p_zi = SVEIntCompareSignedImmFixed | 0x00002010, 3825 CMPEQ_p_p_zi = SVEIntCompareSignedImmFixed | 0x00008000, 3826 CMPNE_p_p_zi = SVEIntCompareSignedImmFixed | 0x00008010 3827}; 3828 3829enum SVEIntCompareUnsignedImmOp { 3830 SVEIntCompareUnsignedImmFixed = 0x24200000, 3831 SVEIntCompareUnsignedImmFMask = 0xFF200000, 3832 SVEIntCompareUnsignedImmMask = 0xFF202010, 3833 CMPHS_p_p_zi = SVEIntCompareUnsignedImmFixed, 3834 CMPHI_p_p_zi = SVEIntCompareUnsignedImmFixed | 0x00000010, 3835 CMPLO_p_p_zi = SVEIntCompareUnsignedImmFixed | 0x00002000, 3836 CMPLS_p_p_zi = SVEIntCompareUnsignedImmFixed | 0x00002010 3837}; 3838 3839enum SVEIntCompareVectorsOp { 3840 SVEIntCompareVectorsFixed = 0x24000000, 3841 SVEIntCompareVectorsFMask = 0xFF200000, 3842 SVEIntCompareVectorsMask = 0xFF20E010, 3843 CMPHS_p_p_zz = SVEIntCompareVectorsFixed, 3844 CMPHI_p_p_zz = SVEIntCompareVectorsFixed | 0x00000010, 3845 CMPEQ_p_p_zw = SVEIntCompareVectorsFixed | 0x00002000, 3846 CMPNE_p_p_zw = SVEIntCompareVectorsFixed | 0x00002010, 3847 CMPGE_p_p_zw = SVEIntCompareVectorsFixed | 0x00004000, 3848 CMPGT_p_p_zw = SVEIntCompareVectorsFixed | 0x00004010, 3849 CMPLT_p_p_zw = SVEIntCompareVectorsFixed | 0x00006000, 3850 CMPLE_p_p_zw = SVEIntCompareVectorsFixed | 0x00006010, 3851 CMPGE_p_p_zz = SVEIntCompareVectorsFixed | 0x00008000, 3852 CMPGT_p_p_zz = SVEIntCompareVectorsFixed | 0x00008010, 3853 CMPEQ_p_p_zz = SVEIntCompareVectorsFixed | 0x0000A000, 3854 CMPNE_p_p_zz = SVEIntCompareVectorsFixed | 0x0000A010, 3855 CMPHS_p_p_zw = SVEIntCompareVectorsFixed | 0x0000C000, 3856 CMPHI_p_p_zw = SVEIntCompareVectorsFixed | 0x0000C010, 3857 CMPLO_p_p_zw = SVEIntCompareVectorsFixed | 0x0000E000, 3858 CMPLS_p_p_zw = SVEIntCompareVectorsFixed | 0x0000E010 3859}; 3860 3861enum SVEIntConvertToFPOp { 3862 SVEIntConvertToFPFixed = 0x6510A000, 3863 SVEIntConvertToFPFMask = 0xFF38E000, 3864 SVEIntConvertToFPMask = 0xFFFFE000, 3865 SCVTF_z_p_z_h2fp16 = SVEIntConvertToFPFixed | 0x00420000, 3866 UCVTF_z_p_z_h2fp16 = SVEIntConvertToFPFixed | 0x00430000, 3867 SCVTF_z_p_z_w2fp16 = SVEIntConvertToFPFixed | 0x00440000, 3868 UCVTF_z_p_z_w2fp16 = SVEIntConvertToFPFixed | 0x00450000, 3869 SCVTF_z_p_z_x2fp16 = SVEIntConvertToFPFixed | 0x00460000, 3870 UCVTF_z_p_z_x2fp16 = SVEIntConvertToFPFixed | 0x00470000, 3871 SCVTF_z_p_z_w2s = SVEIntConvertToFPFixed | 0x00840000, 3872 UCVTF_z_p_z_w2s = SVEIntConvertToFPFixed | 0x00850000, 3873 SCVTF_z_p_z_w2d = SVEIntConvertToFPFixed | 0x00C00000, 3874 UCVTF_z_p_z_w2d = SVEIntConvertToFPFixed | 0x00C10000, 3875 SCVTF_z_p_z_x2s = SVEIntConvertToFPFixed | 0x00C40000, 3876 UCVTF_z_p_z_x2s = SVEIntConvertToFPFixed | 0x00C50000, 3877 SCVTF_z_p_z_x2d = SVEIntConvertToFPFixed | 0x00C60000, 3878 UCVTF_z_p_z_x2d = SVEIntConvertToFPFixed | 0x00C70000 3879}; 3880 3881enum SVEIntDivideVectors_PredicatedOp { 3882 SVEIntDivideVectors_PredicatedFixed = 0x04140000, 3883 SVEIntDivideVectors_PredicatedFMask = 0xFF3CE000, 3884 SVEIntDivideVectors_PredicatedMask = 0xFF3FE000, 3885 SDIV_z_p_zz = SVEIntDivideVectors_PredicatedFixed, 3886 UDIV_z_p_zz = SVEIntDivideVectors_PredicatedFixed | 0x00010000, 3887 SDIVR_z_p_zz = SVEIntDivideVectors_PredicatedFixed | 0x00020000, 3888 UDIVR_z_p_zz = SVEIntDivideVectors_PredicatedFixed | 0x00030000 3889}; 3890 3891enum SVEIntMinMaxDifference_PredicatedOp { 3892 SVEIntMinMaxDifference_PredicatedFixed = 0x04080000, 3893 SVEIntMinMaxDifference_PredicatedFMask = 0xFF38E000, 3894 SVEIntMinMaxDifference_PredicatedMask = 0xFF3FE000, 3895 SMAX_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed, 3896 UMAX_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed | 0x00010000, 3897 SMIN_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed | 0x00020000, 3898 UMIN_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed | 0x00030000, 3899 SABD_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed | 0x00040000, 3900 UABD_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed | 0x00050000 3901}; 3902 3903enum SVEIntMinMaxImm_UnpredicatedOp { 3904 SVEIntMinMaxImm_UnpredicatedFixed = 0x2528C000, 3905 SVEIntMinMaxImm_UnpredicatedFMask = 0xFF38C000, 3906 SVEIntMinMaxImm_UnpredicatedMask = 0xFF3FE000, 3907 SMAX_z_zi = SVEIntMinMaxImm_UnpredicatedFixed, 3908 UMAX_z_zi = SVEIntMinMaxImm_UnpredicatedFixed | 0x00010000, 3909 SMIN_z_zi = SVEIntMinMaxImm_UnpredicatedFixed | 0x00020000, 3910 UMIN_z_zi = SVEIntMinMaxImm_UnpredicatedFixed | 0x00030000 3911}; 3912 3913enum SVEIntMulAddPredicatedOp { 3914 SVEIntMulAddPredicatedFixed = 0x04004000, 3915 SVEIntMulAddPredicatedFMask = 0xFF204000, 3916 SVEIntMulAddPredicatedMask = 0xFF20E000, 3917 MLA_z_p_zzz = SVEIntMulAddPredicatedFixed, 3918 MLS_z_p_zzz = SVEIntMulAddPredicatedFixed | 0x00002000, 3919 MAD_z_p_zzz = SVEIntMulAddPredicatedFixed | 0x00008000, 3920 MSB_z_p_zzz = SVEIntMulAddPredicatedFixed | 0x0000A000 3921}; 3922 3923enum SVEIntMulAddUnpredicatedOp { 3924 SVEIntMulAddUnpredicatedFixed = 0x44000000, 3925 SVEIntMulAddUnpredicatedFMask = 0xFF208000, 3926 SVEIntMulAddUnpredicatedMask = 0xFF20FC00, 3927 SDOT_z_zzz = SVEIntMulAddUnpredicatedFixed, 3928 UDOT_z_zzz = SVEIntMulAddUnpredicatedFixed | 0x00000400 3929}; 3930 3931enum SVEIntMulImm_UnpredicatedOp { 3932 SVEIntMulImm_UnpredicatedFixed = 0x2530C000, 3933 SVEIntMulImm_UnpredicatedFMask = 0xFF38C000, 3934 SVEIntMulImm_UnpredicatedMask = 0xFF3FE000, 3935 MUL_z_zi = SVEIntMulImm_UnpredicatedFixed 3936}; 3937 3938enum SVEIntMulVectors_PredicatedOp { 3939 SVEIntMulVectors_PredicatedFixed = 0x04100000, 3940 SVEIntMulVectors_PredicatedFMask = 0xFF3CE000, 3941 SVEIntMulVectors_PredicatedMask = 0xFF3FE000, 3942 MUL_z_p_zz = SVEIntMulVectors_PredicatedFixed, 3943 SMULH_z_p_zz = SVEIntMulVectors_PredicatedFixed | 0x00020000, 3944 UMULH_z_p_zz = SVEIntMulVectors_PredicatedFixed | 0x00030000 3945}; 3946 3947enum SVEMovprfxOp { 3948 SVEMovprfxFixed = 0x04002000, 3949 SVEMovprfxFMask = 0xFF20E000, 3950 SVEMovprfxMask = 0xFF3EE000, 3951 MOVPRFX_z_p_z = SVEMovprfxFixed | 0x00100000 3952}; 3953 3954enum SVEIntReductionOp { 3955 SVEIntReductionFixed = 0x04002000, 3956 SVEIntReductionFMask = 0xFF20E000, 3957 SVEIntReductionMask = 0xFF3FE000, 3958 SADDV_r_p_z = SVEIntReductionFixed, 3959 UADDV_r_p_z = SVEIntReductionFixed | 0x00010000, 3960 SMAXV_r_p_z = SVEIntReductionFixed | 0x00080000, 3961 UMAXV_r_p_z = SVEIntReductionFixed | 0x00090000, 3962 SMINV_r_p_z = SVEIntReductionFixed | 0x000A0000, 3963 UMINV_r_p_z = SVEIntReductionFixed | 0x000B0000 3964}; 3965 3966enum SVEIntReductionLogicalOp { 3967 SVEIntReductionLogicalFixed = 0x04182000, 3968 SVEIntReductionLogicalFMask = 0xFF38E000, 3969 SVEIntReductionLogicalMask = 0xFF3FE000, 3970 ORV_r_p_z = SVEIntReductionLogicalFixed | 0x00180000, 3971 EORV_r_p_z = SVEIntReductionLogicalFixed | 0x00190000, 3972 ANDV_r_p_z = SVEIntReductionLogicalFixed | 0x001A0000 3973}; 3974 3975enum SVEIntUnaryArithmeticPredicatedOp { 3976 SVEIntUnaryArithmeticPredicatedFixed = 0x0400A000, 3977 SVEIntUnaryArithmeticPredicatedFMask = 0xFF20E000, 3978 SVEIntUnaryArithmeticPredicatedMask = 0xFF3FE000, 3979 SXTB_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00100000, 3980 UXTB_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00110000, 3981 SXTH_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00120000, 3982 UXTH_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00130000, 3983 SXTW_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00140000, 3984 UXTW_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00150000, 3985 ABS_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00160000, 3986 NEG_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00170000, 3987 CLS_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00180000, 3988 CLZ_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00190000, 3989 CNT_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x001A0000, 3990 CNOT_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x001B0000, 3991 FABS_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x001C0000, 3992 FNEG_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x001D0000, 3993 NOT_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x001E0000 3994}; 3995 3996enum SVELoadAndBroadcastElementOp { 3997 SVELoadAndBroadcastElementFixed = 0x84408000, 3998 SVELoadAndBroadcastElementFMask = 0xFE408000, 3999 SVELoadAndBroadcastElementMask = 0xFFC0E000, 4000 LD1RB_z_p_bi_u8 = SVELoadAndBroadcastElementFixed, 4001 LD1RB_z_p_bi_u16 = SVELoadAndBroadcastElementFixed | 0x00002000, 4002 LD1RB_z_p_bi_u32 = SVELoadAndBroadcastElementFixed | 0x00004000, 4003 LD1RB_z_p_bi_u64 = SVELoadAndBroadcastElementFixed | 0x00006000, 4004 LD1RSW_z_p_bi_s64 = SVELoadAndBroadcastElementFixed | 0x00800000, 4005 LD1RH_z_p_bi_u16 = SVELoadAndBroadcastElementFixed | 0x00802000, 4006 LD1RH_z_p_bi_u32 = SVELoadAndBroadcastElementFixed | 0x00804000, 4007 LD1RH_z_p_bi_u64 = SVELoadAndBroadcastElementFixed | 0x00806000, 4008 LD1RSH_z_p_bi_s64 = SVELoadAndBroadcastElementFixed | 0x01000000, 4009 LD1RSH_z_p_bi_s32 = SVELoadAndBroadcastElementFixed | 0x01002000, 4010 LD1RW_z_p_bi_u32 = SVELoadAndBroadcastElementFixed | 0x01004000, 4011 LD1RW_z_p_bi_u64 = SVELoadAndBroadcastElementFixed | 0x01006000, 4012 LD1RSB_z_p_bi_s64 = SVELoadAndBroadcastElementFixed | 0x01800000, 4013 LD1RSB_z_p_bi_s32 = SVELoadAndBroadcastElementFixed | 0x01802000, 4014 LD1RSB_z_p_bi_s16 = SVELoadAndBroadcastElementFixed | 0x01804000, 4015 LD1RD_z_p_bi_u64 = SVELoadAndBroadcastElementFixed | 0x01806000 4016}; 4017 4018enum SVELoadAndBroadcastQuadword_ScalarPlusImmOp { 4019 SVELoadAndBroadcastQuadword_ScalarPlusImmFixed = 0xA4002000, 4020 SVELoadAndBroadcastQuadword_ScalarPlusImmFMask = 0xFE10E000, 4021 SVELoadAndBroadcastQuadword_ScalarPlusImmMask = 0xFFF0E000, 4022 LD1RQB_z_p_bi_u8 = SVELoadAndBroadcastQuadword_ScalarPlusImmFixed, 4023 LD1RQH_z_p_bi_u16 = SVELoadAndBroadcastQuadword_ScalarPlusImmFixed | 0x00800000, 4024 LD1RQW_z_p_bi_u32 = SVELoadAndBroadcastQuadword_ScalarPlusImmFixed | 0x01000000, 4025 LD1RQD_z_p_bi_u64 = SVELoadAndBroadcastQuadword_ScalarPlusImmFixed | 0x01800000 4026}; 4027 4028enum SVELoadAndBroadcastQuadword_ScalarPlusScalarOp { 4029 SVELoadAndBroadcastQuadword_ScalarPlusScalarFixed = 0xA4000000, 4030 SVELoadAndBroadcastQuadword_ScalarPlusScalarFMask = 0xFE00E000, 4031 SVELoadAndBroadcastQuadword_ScalarPlusScalarMask = 0xFFE0E000, 4032 LD1RQB_z_p_br_contiguous = SVELoadAndBroadcastQuadword_ScalarPlusScalarFixed, 4033 LD1RQH_z_p_br_contiguous = SVELoadAndBroadcastQuadword_ScalarPlusScalarFixed | 0x00800000, 4034 LD1RQW_z_p_br_contiguous = SVELoadAndBroadcastQuadword_ScalarPlusScalarFixed | 0x01000000, 4035 LD1RQD_z_p_br_contiguous = SVELoadAndBroadcastQuadword_ScalarPlusScalarFixed | 0x01800000 4036}; 4037 4038enum SVELoadMultipleStructures_ScalarPlusImmOp { 4039 SVELoadMultipleStructures_ScalarPlusImmFixed = 0xA400E000, 4040 SVELoadMultipleStructures_ScalarPlusImmFMask = 0xFE10E000, 4041 SVELoadMultipleStructures_ScalarPlusImmMask = 0xFFF0E000, 4042 LD2B_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00200000, 4043 LD3B_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00400000, 4044 LD4B_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00600000, 4045 LD2H_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00A00000, 4046 LD3H_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00C00000, 4047 LD4H_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00E00000, 4048 LD2W_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01200000, 4049 LD3W_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01400000, 4050 LD4W_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01600000, 4051 LD2D_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01A00000, 4052 LD3D_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01C00000, 4053 LD4D_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01E00000 4054}; 4055 4056enum SVELoadMultipleStructures_ScalarPlusScalarOp { 4057 SVELoadMultipleStructures_ScalarPlusScalarFixed = 0xA400C000, 4058 SVELoadMultipleStructures_ScalarPlusScalarFMask = 0xFE00E000, 4059 SVELoadMultipleStructures_ScalarPlusScalarMask = 0xFFE0E000, 4060 LD2B_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00200000, 4061 LD3B_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00400000, 4062 LD4B_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00600000, 4063 LD2H_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00A00000, 4064 LD3H_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00C00000, 4065 LD4H_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00E00000, 4066 LD2W_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01200000, 4067 LD3W_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01400000, 4068 LD4W_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01600000, 4069 LD2D_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01A00000, 4070 LD3D_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01C00000, 4071 LD4D_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01E00000 4072}; 4073 4074enum SVELoadPredicateRegisterOp { 4075 SVELoadPredicateRegisterFixed = 0x85800000, 4076 SVELoadPredicateRegisterFMask = 0xFFC0E010, 4077 SVELoadPredicateRegisterMask = 0xFFC0E010, 4078 LDR_p_bi = SVELoadPredicateRegisterFixed 4079}; 4080 4081enum SVELoadVectorRegisterOp { 4082 SVELoadVectorRegisterFixed = 0x85804000, 4083 SVELoadVectorRegisterFMask = 0xFFC0E000, 4084 SVELoadVectorRegisterMask = 0xFFC0E000, 4085 LDR_z_bi = SVELoadVectorRegisterFixed 4086}; 4087 4088enum SVEMulIndexOp { 4089 SVEMulIndexFixed = 0x44200000, 4090 SVEMulIndexFMask = 0xFF200000, 4091 SVEMulIndexMask = 0xFFE0FC00, 4092 SDOT_z_zzzi_s = SVEMulIndexFixed | 0x00800000, 4093 UDOT_z_zzzi_s = SVEMulIndexFixed | 0x00800400, 4094 SDOT_z_zzzi_d = SVEMulIndexFixed | 0x00C00000, 4095 UDOT_z_zzzi_d = SVEMulIndexFixed | 0x00C00400 4096}; 4097 4098enum SVEPartitionBreakConditionOp { 4099 SVEPartitionBreakConditionFixed = 0x25104000, 4100 SVEPartitionBreakConditionFMask = 0xFF3FC200, 4101 SVEPartitionBreakConditionMask = 0xFFFFC200, 4102 BRKA_p_p_p = SVEPartitionBreakConditionFixed, 4103 BRKAS_p_p_p_z = SVEPartitionBreakConditionFixed | 0x00400000, 4104 BRKB_p_p_p = SVEPartitionBreakConditionFixed | 0x00800000, 4105 BRKBS_p_p_p_z = SVEPartitionBreakConditionFixed | 0x00C00000 4106}; 4107 4108enum SVEPermutePredicateElementsOp { 4109 SVEPermutePredicateElementsFixed = 0x05204000, 4110 SVEPermutePredicateElementsFMask = 0xFF30E210, 4111 SVEPermutePredicateElementsMask = 0xFF30FE10, 4112 ZIP1_p_pp = SVEPermutePredicateElementsFixed, 4113 ZIP2_p_pp = SVEPermutePredicateElementsFixed | 0x00000400, 4114 UZP1_p_pp = SVEPermutePredicateElementsFixed | 0x00000800, 4115 UZP2_p_pp = SVEPermutePredicateElementsFixed | 0x00000C00, 4116 TRN1_p_pp = SVEPermutePredicateElementsFixed | 0x00001000, 4117 TRN2_p_pp = SVEPermutePredicateElementsFixed | 0x00001400 4118}; 4119 4120enum SVEPermuteVectorExtractOp { 4121 SVEPermuteVectorExtractFixed = 0x05200000, 4122 SVEPermuteVectorExtractFMask = 0xFF20E000, 4123 SVEPermuteVectorExtractMask = 0xFFE0E000, 4124 EXT_z_zi_des = SVEPermuteVectorExtractFixed 4125}; 4126 4127enum SVEPermuteVectorInterleavingOp { 4128 SVEPermuteVectorInterleavingFixed = 0x05206000, 4129 SVEPermuteVectorInterleavingFMask = 0xFF20E000, 4130 SVEPermuteVectorInterleavingMask = 0xFF20FC00, 4131 ZIP1_z_zz = SVEPermuteVectorInterleavingFixed, 4132 ZIP2_z_zz = SVEPermuteVectorInterleavingFixed | 0x00000400, 4133 UZP1_z_zz = SVEPermuteVectorInterleavingFixed | 0x00000800, 4134 UZP2_z_zz = SVEPermuteVectorInterleavingFixed | 0x00000C00, 4135 TRN1_z_zz = SVEPermuteVectorInterleavingFixed | 0x00001000, 4136 TRN2_z_zz = SVEPermuteVectorInterleavingFixed | 0x00001400 4137}; 4138 4139enum SVEPredicateCountOp { 4140 SVEPredicateCountFixed = 0x25208000, 4141 SVEPredicateCountFMask = 0xFF38C000, 4142 SVEPredicateCountMask = 0xFF3FC200, 4143 CNTP_r_p_p = SVEPredicateCountFixed 4144}; 4145 4146enum SVEPredicateFirstActiveOp { 4147 SVEPredicateFirstActiveFixed = 0x2518C000, 4148 SVEPredicateFirstActiveFMask = 0xFF3FFE10, 4149 SVEPredicateFirstActiveMask = 0xFFFFFE10, 4150 PFIRST_p_p_p = SVEPredicateFirstActiveFixed | 0x00400000 4151}; 4152 4153enum SVEPredicateInitializeOp { 4154 SVEPredicateInitializeFixed = 0x2518E000, 4155 SVEPredicateInitializeFMask = 0xFF3EFC10, 4156 SVEPredicateInitializeMask = 0xFF3FFC10, 4157 SVEPredicateInitializeSetFlagsBit = 0x00010000, 4158 PTRUE_p_s = SVEPredicateInitializeFixed | 0x00000000, 4159 PTRUES_p_s = SVEPredicateInitializeFixed | SVEPredicateInitializeSetFlagsBit 4160}; 4161 4162enum SVEPredicateLogicalOp { 4163 SVEPredicateLogicalFixed = 0x25004000, 4164 SVEPredicateLogicalFMask = 0xFF30C000, 4165 SVEPredicateLogicalMask = 0xFFF0C210, 4166 SVEPredicateLogicalSetFlagsBit = 0x00400000, 4167 AND_p_p_pp_z = SVEPredicateLogicalFixed, 4168 ANDS_p_p_pp_z = AND_p_p_pp_z | SVEPredicateLogicalSetFlagsBit, 4169 BIC_p_p_pp_z = SVEPredicateLogicalFixed | 0x00000010, 4170 BICS_p_p_pp_z = BIC_p_p_pp_z | SVEPredicateLogicalSetFlagsBit, 4171 EOR_p_p_pp_z = SVEPredicateLogicalFixed | 0x00000200, 4172 EORS_p_p_pp_z = EOR_p_p_pp_z | SVEPredicateLogicalSetFlagsBit, 4173 ORR_p_p_pp_z = SVEPredicateLogicalFixed | 0x00800000, 4174 ORRS_p_p_pp_z = ORR_p_p_pp_z | SVEPredicateLogicalSetFlagsBit, 4175 ORN_p_p_pp_z = SVEPredicateLogicalFixed | 0x00800010, 4176 ORNS_p_p_pp_z = ORN_p_p_pp_z | SVEPredicateLogicalSetFlagsBit, 4177 NAND_p_p_pp_z = SVEPredicateLogicalFixed | 0x00800210, 4178 NANDS_p_p_pp_z = NAND_p_p_pp_z | SVEPredicateLogicalSetFlagsBit, 4179 NOR_p_p_pp_z = SVEPredicateLogicalFixed | 0x00800200, 4180 NORS_p_p_pp_z = NOR_p_p_pp_z | SVEPredicateLogicalSetFlagsBit, 4181 SEL_p_p_pp = SVEPredicateLogicalFixed | 0x00000210 4182}; 4183 4184enum SVEPredicateNextActiveOp { 4185 SVEPredicateNextActiveFixed = 0x2519C400, 4186 SVEPredicateNextActiveFMask = 0xFF3FFE10, 4187 SVEPredicateNextActiveMask = 0xFF3FFE10, 4188 PNEXT_p_p_p = SVEPredicateNextActiveFixed 4189}; 4190 4191enum SVEPredicateReadFromFFR_PredicatedOp { 4192 SVEPredicateReadFromFFR_PredicatedFixed = 0x2518F000, 4193 SVEPredicateReadFromFFR_PredicatedFMask = 0xFF3FFE10, 4194 SVEPredicateReadFromFFR_PredicatedMask = 0xFFFFFE10, 4195 RDFFR_p_p_f = SVEPredicateReadFromFFR_PredicatedFixed, 4196 RDFFRS_p_p_f = SVEPredicateReadFromFFR_PredicatedFixed | 0x00400000 4197}; 4198 4199enum SVEPredicateReadFromFFR_UnpredicatedOp { 4200 SVEPredicateReadFromFFR_UnpredicatedFixed = 0x2519F000, 4201 SVEPredicateReadFromFFR_UnpredicatedFMask = 0xFF3FFFF0, 4202 SVEPredicateReadFromFFR_UnpredicatedMask = 0xFFFFFFF0, 4203 RDFFR_p_f = SVEPredicateReadFromFFR_UnpredicatedFixed 4204}; 4205 4206enum SVEPredicateTestOp { 4207 SVEPredicateTestFixed = 0x2510C000, 4208 SVEPredicateTestFMask = 0xFF3FC210, 4209 SVEPredicateTestMask = 0xFFFFC21F, 4210 PTEST_p_p = SVEPredicateTestFixed | 0x00400000 4211}; 4212 4213enum SVEPredicateZeroOp { 4214 SVEPredicateZeroFixed = 0x2518E400, 4215 SVEPredicateZeroFMask = 0xFF3FFFF0, 4216 SVEPredicateZeroMask = 0xFFFFFFF0, 4217 PFALSE_p = SVEPredicateZeroFixed 4218}; 4219 4220enum SVEPropagateBreakOp { 4221 SVEPropagateBreakFixed = 0x2500C000, 4222 SVEPropagateBreakFMask = 0xFF30C000, 4223 SVEPropagateBreakMask = 0xFFF0C210, 4224 BRKPA_p_p_pp = SVEPropagateBreakFixed, 4225 BRKPB_p_p_pp = SVEPropagateBreakFixed | 0x00000010, 4226 BRKPAS_p_p_pp = SVEPropagateBreakFixed | 0x00400000, 4227 BRKPBS_p_p_pp = SVEPropagateBreakFixed | 0x00400010 4228}; 4229 4230enum SVEPropagateBreakToNextPartitionOp { 4231 SVEPropagateBreakToNextPartitionFixed = 0x25184000, 4232 SVEPropagateBreakToNextPartitionFMask = 0xFFBFC210, 4233 SVEPropagateBreakToNextPartitionMask = 0xFFFFC210, 4234 BRKN_p_p_pp = SVEPropagateBreakToNextPartitionFixed, 4235 BRKNS_p_p_pp = SVEPropagateBreakToNextPartitionFixed | 0x00400000 4236}; 4237 4238enum SVEReversePredicateElementsOp { 4239 SVEReversePredicateElementsFixed = 0x05344000, 4240 SVEReversePredicateElementsFMask = 0xFF3FFE10, 4241 SVEReversePredicateElementsMask = 0xFF3FFE10, 4242 REV_p_p = SVEReversePredicateElementsFixed 4243}; 4244 4245enum SVEReverseVectorElementsOp { 4246 SVEReverseVectorElementsFixed = 0x05383800, 4247 SVEReverseVectorElementsFMask = 0xFF3FFC00, 4248 SVEReverseVectorElementsMask = 0xFF3FFC00, 4249 REV_z_z = SVEReverseVectorElementsFixed 4250}; 4251 4252enum SVEReverseWithinElementsOp { 4253 SVEReverseWithinElementsFixed = 0x05248000, 4254 SVEReverseWithinElementsFMask = 0xFF3CE000, 4255 SVEReverseWithinElementsMask = 0xFF3FE000, 4256 REVB_z_z = SVEReverseWithinElementsFixed, 4257 REVH_z_z = SVEReverseWithinElementsFixed | 0x00010000, 4258 REVW_z_z = SVEReverseWithinElementsFixed | 0x00020000, 4259 RBIT_z_p_z = SVEReverseWithinElementsFixed | 0x00030000 4260}; 4261 4262enum SVESaturatingIncDecRegisterByElementCountOp { 4263 SVESaturatingIncDecRegisterByElementCountFixed = 0x0420F000, 4264 SVESaturatingIncDecRegisterByElementCountFMask = 0xFF20F000, 4265 SVESaturatingIncDecRegisterByElementCountMask = 0xFFF0FC00, 4266 SQINCB_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed, 4267 UQINCB_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00000400, 4268 SQDECB_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00000800, 4269 UQDECB_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00000C00, 4270 SQINCB_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00100000, 4271 UQINCB_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00100400, 4272 SQDECB_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00100800, 4273 UQDECB_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00100C00, 4274 SQINCH_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00400000, 4275 UQINCH_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00400400, 4276 SQDECH_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00400800, 4277 UQDECH_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00400C00, 4278 SQINCH_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00500000, 4279 UQINCH_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00500400, 4280 SQDECH_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00500800, 4281 UQDECH_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00500C00, 4282 SQINCW_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00800000, 4283 UQINCW_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00800400, 4284 SQDECW_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00800800, 4285 UQDECW_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00800C00, 4286 SQINCW_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00900000, 4287 UQINCW_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00900400, 4288 SQDECW_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00900800, 4289 UQDECW_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00900C00, 4290 SQINCD_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00C00000, 4291 UQINCD_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00C00400, 4292 SQDECD_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00C00800, 4293 UQDECD_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00C00C00, 4294 SQINCD_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00D00000, 4295 UQINCD_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00D00400, 4296 SQDECD_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00D00800, 4297 UQDECD_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00D00C00 4298}; 4299 4300enum SVESaturatingIncDecVectorByElementCountOp { 4301 SVESaturatingIncDecVectorByElementCountFixed = 0x0420C000, 4302 SVESaturatingIncDecVectorByElementCountFMask = 0xFF30F000, 4303 SVESaturatingIncDecVectorByElementCountMask = 0xFFF0FC00, 4304 SQINCH_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00400000, 4305 UQINCH_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00400400, 4306 SQDECH_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00400800, 4307 UQDECH_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00400C00, 4308 SQINCW_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00800000, 4309 UQINCW_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00800400, 4310 SQDECW_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00800800, 4311 UQDECW_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00800C00, 4312 SQINCD_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00C00000, 4313 UQINCD_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00C00400, 4314 SQDECD_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00C00800, 4315 UQDECD_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00C00C00 4316}; 4317 4318enum SVEStackFrameAdjustmentOp { 4319 SVEStackFrameAdjustmentFixed = 0x04205000, 4320 SVEStackFrameAdjustmentFMask = 0xFFA0F800, 4321 SVEStackFrameAdjustmentMask = 0xFFE0F800, 4322 ADDVL_r_ri = SVEStackFrameAdjustmentFixed, 4323 ADDPL_r_ri = SVEStackFrameAdjustmentFixed | 0x00400000 4324}; 4325 4326enum SVEStackFrameSizeOp { 4327 SVEStackFrameSizeFixed = 0x04BF5000, 4328 SVEStackFrameSizeFMask = 0xFFFFF800, 4329 SVEStackFrameSizeMask = 0xFFFFF800, 4330 RDVL_r_i = SVEStackFrameSizeFixed 4331}; 4332 4333enum SVEStoreMultipleStructures_ScalarPlusImmOp { 4334 SVEStoreMultipleStructures_ScalarPlusImmFixed = 0xE410E000, 4335 SVEStoreMultipleStructures_ScalarPlusImmFMask = 0xFE10E000, 4336 SVEStoreMultipleStructures_ScalarPlusImmMask = 0xFFF0E000, 4337 ST2B_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00200000, 4338 ST3B_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00400000, 4339 ST4B_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00600000, 4340 ST2H_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00A00000, 4341 ST3H_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00C00000, 4342 ST4H_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00E00000, 4343 ST2W_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01200000, 4344 ST3W_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01400000, 4345 ST4W_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01600000, 4346 ST2D_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01A00000, 4347 ST3D_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01C00000, 4348 ST4D_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01E00000 4349}; 4350 4351enum SVEStoreMultipleStructures_ScalarPlusScalarOp { 4352 SVEStoreMultipleStructures_ScalarPlusScalarFixed = 0xE4006000, 4353 SVEStoreMultipleStructures_ScalarPlusScalarFMask = 0xFE00E000, 4354 SVEStoreMultipleStructures_ScalarPlusScalarMask = 0xFFE0E000, 4355 ST2B_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00200000, 4356 ST3B_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00400000, 4357 ST4B_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00600000, 4358 ST2H_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00A00000, 4359 ST3H_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00C00000, 4360 ST4H_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00E00000, 4361 ST2W_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01200000, 4362 ST3W_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01400000, 4363 ST4W_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01600000, 4364 ST2D_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01A00000, 4365 ST3D_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01C00000, 4366 ST4D_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01E00000 4367}; 4368 4369enum SVEStorePredicateRegisterOp { 4370 SVEStorePredicateRegisterFixed = 0xE5800000, 4371 SVEStorePredicateRegisterFMask = 0xFFC0E010, 4372 SVEStorePredicateRegisterMask = 0xFFC0E010, 4373 STR_p_bi = SVEStorePredicateRegisterFixed 4374}; 4375 4376enum SVEStoreVectorRegisterOp { 4377 SVEStoreVectorRegisterFixed = 0xE5804000, 4378 SVEStoreVectorRegisterFMask = 0xFFC0E000, 4379 SVEStoreVectorRegisterMask = 0xFFC0E000, 4380 STR_z_bi = SVEStoreVectorRegisterFixed 4381}; 4382 4383enum SVETableLookupOp { 4384 SVETableLookupFixed = 0x05203000, 4385 SVETableLookupFMask = 0xFF20FC00, 4386 SVETableLookupMask = 0xFF20FC00, 4387 TBL_z_zz_1 = SVETableLookupFixed 4388}; 4389 4390enum SVEUnpackPredicateElementsOp { 4391 SVEUnpackPredicateElementsFixed = 0x05304000, 4392 SVEUnpackPredicateElementsFMask = 0xFFFEFE10, 4393 SVEUnpackPredicateElementsMask = 0xFFFFFE10, 4394 PUNPKLO_p_p = SVEUnpackPredicateElementsFixed, 4395 PUNPKHI_p_p = SVEUnpackPredicateElementsFixed | 0x00010000 4396}; 4397 4398enum SVEUnpackVectorElementsOp { 4399 SVEUnpackVectorElementsFixed = 0x05303800, 4400 SVEUnpackVectorElementsFMask = 0xFF3CFC00, 4401 SVEUnpackVectorElementsMask = 0xFF3FFC00, 4402 SUNPKLO_z_z = SVEUnpackVectorElementsFixed, 4403 SUNPKHI_z_z = SVEUnpackVectorElementsFixed | 0x00010000, 4404 UUNPKLO_z_z = SVEUnpackVectorElementsFixed | 0x00020000, 4405 UUNPKHI_z_z = SVEUnpackVectorElementsFixed | 0x00030000 4406}; 4407 4408enum SVEVectorSelectOp { 4409 SVEVectorSelectFixed = 0x0520C000, 4410 SVEVectorSelectFMask = 0xFF20C000, 4411 SVEVectorSelectMask = 0xFF20C000, 4412 SEL_z_p_zz = SVEVectorSelectFixed 4413}; 4414 4415enum SVEVectorSpliceOp { 4416 SVEVectorSpliceFixed = 0x052C8000, 4417 SVEVectorSpliceFMask = 0xFF3FE000, 4418 SVEVectorSpliceMask = 0xFF3FE000, 4419 SPLICE_z_p_zz_des = SVEVectorSpliceFixed 4420}; 4421 4422enum ReservedOp { 4423 ReservedFixed = 0x00000000, 4424 ReservedFMask = 0x1E000000, 4425 ReservedMask = 0xFFFF0000, 4426 UDF = ReservedFixed | 0x00000000 4427}; 4428 4429// Unimplemented and unallocated instructions. These are defined to make fixed 4430// bit assertion easier. 4431enum UnimplementedOp { 4432 UnimplementedFixed = 0x00000000, 4433 UnimplementedFMask = 0x00000000 4434}; 4435 4436enum UnallocatedOp { 4437 UnallocatedFixed = 0x00000000, 4438 UnallocatedFMask = 0x00000000 4439}; 4440 4441// Re-enable `clang-format` after the `enum`s. 4442// clang-format on 4443 4444} // namespace aarch64 4445} // namespace vixl 4446 4447#endif // VIXL_AARCH64_CONSTANTS_AARCH64_H_ 4448