1// Copyright 2017, VIXL authors
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are met:
6//
7//   * Redistributions of source code must retain the above copyright notice,
8//     this list of conditions and the following disclaimer.
9//   * Redistributions in binary form must reproduce the above copyright notice,
10//     this list of conditions and the following disclaimer in the documentation
11//     and/or other materials provided with the distribution.
12//   * Neither the name of ARM Limited nor the names of its contributors may be
13//     used to endorse or promote products derived from this software without
14//     specific prior written permission.
15//
16// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
17// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
20// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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24// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
27#ifndef VIXL_DISASM_AARCH32_H_
28#define VIXL_DISASM_AARCH32_H_
29
30extern "C" {
31#include <stdint.h>
32}
33
34#include <iomanip>
35
36#include "aarch32/constants-aarch32.h"
37#include "aarch32/operands-aarch32.h"
38
39// Microsoft Visual C++ defines a `mvn` macro that conflicts with our own
40// definition.
41#if defined(_MSC_VER) && defined(mvn)
42#undef mvn
43#endif
44
45namespace vixl {
46namespace aarch32 {
47
48class ITBlock {
49  Condition first_condition_;
50  Condition condition_;
51  uint16_t it_mask_;
52
53 public:
54  ITBlock() : first_condition_(al), condition_(al), it_mask_(0) {}
55  void Advance() {
56    condition_ = Condition((condition_.GetCondition() & 0xe) | (it_mask_ >> 3));
57    it_mask_ = (it_mask_ << 1) & 0xf;
58  }
59  bool InITBlock() const { return it_mask_ != 0; }
60  bool OutsideITBlock() const { return !InITBlock(); }
61  bool LastInITBlock() const { return it_mask_ == 0x8; }
62  bool OutsideITBlockOrLast() const {
63    return OutsideITBlock() || LastInITBlock();
64  }
65  void Set(Condition first_condition, uint16_t mask) {
66    condition_ = first_condition_ = first_condition;
67    it_mask_ = mask;
68  }
69  Condition GetFirstCondition() const { return first_condition_; }
70  Condition GetCurrentCondition() const { return condition_; }
71};
72
73class Disassembler {
74 public:
75  enum LocationType {
76    kAnyLocation,
77    kCodeLocation,
78    kDataLocation,
79    kCoprocLocation,
80    kLoadByteLocation,
81    kLoadHalfWordLocation,
82    kLoadWordLocation,
83    kLoadDoubleWordLocation,
84    kLoadSignedByteLocation,
85    kLoadSignedHalfWordLocation,
86    kLoadSinglePrecisionLocation,
87    kLoadDoublePrecisionLocation,
88    kStoreByteLocation,
89    kStoreHalfWordLocation,
90    kStoreWordLocation,
91    kStoreDoubleWordLocation,
92    kStoreSinglePrecisionLocation,
93    kStoreDoublePrecisionLocation,
94    kVld1Location,
95    kVld2Location,
96    kVld3Location,
97    kVld4Location,
98    kVst1Location,
99    kVst2Location,
100    kVst3Location,
101    kVst4Location
102  };
103
104  class ConditionPrinter {
105    const ITBlock& it_block_;
106    Condition cond_;
107
108   public:
109    ConditionPrinter(const ITBlock& it_block, Condition cond)
110        : it_block_(it_block), cond_(cond) {}
111    const ITBlock& GetITBlock() const { return it_block_; }
112    Condition GetCond() const { return cond_; }
113    friend std::ostream& operator<<(std::ostream& os, ConditionPrinter cond) {
114      if (cond.it_block_.InITBlock() && cond.cond_.Is(al) &&
115          !cond.cond_.IsNone()) {
116        return os << "al";
117      }
118      return os << cond.cond_;
119    }
120  };
121
122  class ImmediatePrinter {
123    uint32_t imm_;
124
125   public:
126    explicit ImmediatePrinter(uint32_t imm) : imm_(imm) {}
127    uint32_t GetImm() const { return imm_; }
128    friend std::ostream& operator<<(std::ostream& os, ImmediatePrinter imm) {
129      return os << "#" << imm.GetImm();
130    }
131  };
132
133  class SignedImmediatePrinter {
134    int32_t imm_;
135
136   public:
137    explicit SignedImmediatePrinter(int32_t imm) : imm_(imm) {}
138    int32_t GetImm() const { return imm_; }
139    friend std::ostream& operator<<(std::ostream& os,
140                                    SignedImmediatePrinter imm) {
141      return os << "#" << imm.GetImm();
142    }
143  };
144
145  class RawImmediatePrinter {
146    uint32_t imm_;
147
148   public:
149    explicit RawImmediatePrinter(uint32_t imm) : imm_(imm) {}
150    uint32_t GetImm() const { return imm_; }
151    friend std::ostream& operator<<(std::ostream& os, RawImmediatePrinter imm) {
152      return os << imm.GetImm();
153    }
154  };
155
156  class DtPrinter {
157    DataType dt_;
158    DataType default_dt_;
159
160   public:
161    DtPrinter(DataType dt, DataType default_dt)
162        : dt_(dt), default_dt_(default_dt) {}
163    DataType GetDt() const { return dt_; }
164    DataType GetDefaultDt() const { return default_dt_; }
165    friend std::ostream& operator<<(std::ostream& os, DtPrinter dt) {
166      if (dt.dt_.Is(dt.default_dt_)) return os;
167      return os << dt.dt_;
168    }
169  };
170
171  class IndexedRegisterPrinter {
172    DRegister reg_;
173    uint32_t index_;
174
175   public:
176    IndexedRegisterPrinter(DRegister reg, uint32_t index)
177        : reg_(reg), index_(index) {}
178    DRegister GetReg() const { return reg_; }
179    uint32_t GetIndex() const { return index_; }
180    friend std::ostream& operator<<(std::ostream& os,
181                                    IndexedRegisterPrinter reg) {
182      return os << reg.GetReg() << "[" << reg.GetIndex() << "]";
183    }
184  };
185
186  // TODO: Merge this class with PrintLabel below. This Location class
187  // represents a PC-relative offset, not an address.
188  class Location {
189   public:
190    typedef int32_t Offset;
191
192    Location(Offset immediate, Offset pc_offset)
193        : immediate_(immediate), pc_offset_(pc_offset) {}
194    Offset GetImmediate() const { return immediate_; }
195    Offset GetPCOffset() const { return pc_offset_; }
196
197   private:
198    Offset immediate_;
199    Offset pc_offset_;
200  };
201
202  class PrintLabel {
203    LocationType location_type_;
204    Location::Offset immediate_;
205    Location::Offset location_;
206
207   public:
208    PrintLabel(LocationType location_type,
209               Location* offset,
210               Location::Offset position)
211        : location_type_(location_type),
212          immediate_(offset->GetImmediate()),
213          location_(static_cast<Location::Offset>(
214              static_cast<int64_t>(offset->GetPCOffset()) +
215              offset->GetImmediate() + position)) {}
216
217    LocationType GetLocationType() const { return location_type_; }
218    Location::Offset GetLocation() const { return location_; }
219    Location::Offset GetImmediate() const { return immediate_; }
220
221    friend inline std::ostream& operator<<(std::ostream& os,
222                                           const PrintLabel& label) {
223      os << "0x" << std::hex << std::setw(8) << std::setfill('0')
224         << label.GetLocation() << std::dec;
225      return os;
226    }
227  };
228
229
230  class PrintMemOperand {
231    LocationType location_type_;
232    const MemOperand& operand_;
233
234   public:
235    PrintMemOperand(LocationType location_type, const MemOperand& operand)
236        : location_type_(location_type), operand_(operand) {}
237    LocationType GetLocationType() const { return location_type_; }
238    const MemOperand& GetOperand() const { return operand_; }
239  };
240
241  class PrintAlignedMemOperand {
242    LocationType location_type_;
243    const AlignedMemOperand& operand_;
244
245   public:
246    PrintAlignedMemOperand(LocationType location_type,
247                           const AlignedMemOperand& operand)
248        : location_type_(location_type), operand_(operand) {}
249    LocationType GetLocationType() const { return location_type_; }
250    const AlignedMemOperand& GetOperand() const { return operand_; }
251  };
252
253  class DisassemblerStream {
254    std::ostream& os_;
255    InstructionType current_instruction_type_;
256    InstructionAttribute current_instruction_attributes_;
257
258   public:
259    explicit DisassemblerStream(std::ostream& os)  // NOLINT(runtime/references)
260        : os_(os),
261          current_instruction_type_(kUndefInstructionType),
262          current_instruction_attributes_(kNoAttribute) {}
263    virtual ~DisassemblerStream() {}
264    std::ostream& os() const { return os_; }
265    void SetCurrentInstruction(
266        InstructionType current_instruction_type,
267        InstructionAttribute current_instruction_attributes) {
268      current_instruction_type_ = current_instruction_type;
269      current_instruction_attributes_ = current_instruction_attributes;
270    }
271    InstructionType GetCurrentInstructionType() const {
272      return current_instruction_type_;
273    }
274    InstructionAttribute GetCurrentInstructionAttributes() const {
275      return current_instruction_attributes_;
276    }
277    bool Has(InstructionAttribute attributes) const {
278      return (current_instruction_attributes_ & attributes) == attributes;
279    }
280    template <typename T>
281    DisassemblerStream& operator<<(T value) {
282      os_ << value;
283      return *this;
284    }
285    virtual DisassemblerStream& operator<<(const char* string) {
286      os_ << string;
287      return *this;
288    }
289    virtual DisassemblerStream& operator<<(const ConditionPrinter& cond) {
290      os_ << cond;
291      return *this;
292    }
293    virtual DisassemblerStream& operator<<(Condition cond) {
294      os_ << cond;
295      return *this;
296    }
297    virtual DisassemblerStream& operator<<(const EncodingSize& size) {
298      os_ << size;
299      return *this;
300    }
301    virtual DisassemblerStream& operator<<(const ImmediatePrinter& imm) {
302      os_ << imm;
303      return *this;
304    }
305    virtual DisassemblerStream& operator<<(const SignedImmediatePrinter& imm) {
306      os_ << imm;
307      return *this;
308    }
309    virtual DisassemblerStream& operator<<(const RawImmediatePrinter& imm) {
310      os_ << imm;
311      return *this;
312    }
313    virtual DisassemblerStream& operator<<(const DtPrinter& dt) {
314      os_ << dt;
315      return *this;
316    }
317    virtual DisassemblerStream& operator<<(const DataType& type) {
318      os_ << type;
319      return *this;
320    }
321    virtual DisassemblerStream& operator<<(Shift shift) {
322      os_ << shift;
323      return *this;
324    }
325    virtual DisassemblerStream& operator<<(Sign sign) {
326      os_ << sign;
327      return *this;
328    }
329    virtual DisassemblerStream& operator<<(Alignment alignment) {
330      os_ << alignment;
331      return *this;
332    }
333    virtual DisassemblerStream& operator<<(const PrintLabel& label) {
334      os_ << label;
335      return *this;
336    }
337    virtual DisassemblerStream& operator<<(const WriteBack& write_back) {
338      os_ << write_back;
339      return *this;
340    }
341    virtual DisassemblerStream& operator<<(const NeonImmediate& immediate) {
342      os_ << immediate;
343      return *this;
344    }
345    virtual DisassemblerStream& operator<<(Register reg) {
346      os_ << reg;
347      return *this;
348    }
349    virtual DisassemblerStream& operator<<(SRegister reg) {
350      os_ << reg;
351      return *this;
352    }
353    virtual DisassemblerStream& operator<<(DRegister reg) {
354      os_ << reg;
355      return *this;
356    }
357    virtual DisassemblerStream& operator<<(QRegister reg) {
358      os_ << reg;
359      return *this;
360    }
361    virtual DisassemblerStream& operator<<(const RegisterOrAPSR_nzcv reg) {
362      os_ << reg;
363      return *this;
364    }
365    virtual DisassemblerStream& operator<<(SpecialRegister reg) {
366      os_ << reg;
367      return *this;
368    }
369    virtual DisassemblerStream& operator<<(MaskedSpecialRegister reg) {
370      os_ << reg;
371      return *this;
372    }
373    virtual DisassemblerStream& operator<<(SpecialFPRegister reg) {
374      os_ << reg;
375      return *this;
376    }
377    virtual DisassemblerStream& operator<<(BankedRegister reg) {
378      os_ << reg;
379      return *this;
380    }
381    virtual DisassemblerStream& operator<<(const RegisterList& list) {
382      os_ << list;
383      return *this;
384    }
385    virtual DisassemblerStream& operator<<(const SRegisterList& list) {
386      os_ << list;
387      return *this;
388    }
389    virtual DisassemblerStream& operator<<(const DRegisterList& list) {
390      os_ << list;
391      return *this;
392    }
393    virtual DisassemblerStream& operator<<(const NeonRegisterList& list) {
394      os_ << list;
395      return *this;
396    }
397    virtual DisassemblerStream& operator<<(const DRegisterLane& reg) {
398      os_ << reg;
399      return *this;
400    }
401    virtual DisassemblerStream& operator<<(const IndexedRegisterPrinter& reg) {
402      os_ << reg;
403      return *this;
404    }
405    virtual DisassemblerStream& operator<<(Coprocessor coproc) {
406      os_ << coproc;
407      return *this;
408    }
409    virtual DisassemblerStream& operator<<(CRegister reg) {
410      os_ << reg;
411      return *this;
412    }
413    virtual DisassemblerStream& operator<<(Endianness endian_specifier) {
414      os_ << endian_specifier;
415      return *this;
416    }
417    virtual DisassemblerStream& operator<<(MemoryBarrier option) {
418      os_ << option;
419      return *this;
420    }
421    virtual DisassemblerStream& operator<<(InterruptFlags iflags) {
422      os_ << iflags;
423      return *this;
424    }
425    virtual DisassemblerStream& operator<<(const Operand& operand) {
426      if (operand.IsImmediate()) {
427        if (Has(kBitwise)) {
428          return *this << "#0x" << std::hex << operand.GetImmediate()
429                       << std::dec;
430        }
431        return *this << "#" << operand.GetImmediate();
432      }
433      if (operand.IsImmediateShiftedRegister()) {
434        if ((operand.GetShift().IsLSL() || operand.GetShift().IsROR()) &&
435            (operand.GetShiftAmount() == 0)) {
436          return *this << operand.GetBaseRegister();
437        }
438        if (operand.GetShift().IsRRX()) {
439          return *this << operand.GetBaseRegister() << ", rrx";
440        }
441        return *this << operand.GetBaseRegister() << ", " << operand.GetShift()
442                     << " #" << operand.GetShiftAmount();
443      }
444      if (operand.IsRegisterShiftedRegister()) {
445        return *this << operand.GetBaseRegister() << ", " << operand.GetShift()
446                     << " " << operand.GetShiftRegister();
447      }
448      VIXL_UNREACHABLE();
449      return *this;
450    }
451    virtual DisassemblerStream& operator<<(const SOperand& operand) {
452      if (operand.IsImmediate()) {
453        return *this << operand.GetNeonImmediate();
454      }
455      return *this << operand.GetRegister();
456    }
457    virtual DisassemblerStream& operator<<(const DOperand& operand) {
458      if (operand.IsImmediate()) {
459        return *this << operand.GetNeonImmediate();
460      }
461      return *this << operand.GetRegister();
462    }
463    virtual DisassemblerStream& operator<<(const QOperand& operand) {
464      if (operand.IsImmediate()) {
465        return *this << operand.GetNeonImmediate();
466      }
467      return *this << operand.GetRegister();
468    }
469    virtual DisassemblerStream& operator<<(const MemOperand& operand) {
470      *this << "[" << operand.GetBaseRegister();
471      if (operand.GetAddrMode() == PostIndex) {
472        *this << "]";
473        if (operand.IsRegisterOnly()) return *this << "!";
474      }
475      if (operand.IsImmediate()) {
476        if ((operand.GetOffsetImmediate() != 0) ||
477            operand.GetSign().IsMinus() ||
478            ((operand.GetAddrMode() != Offset) && !operand.IsRegisterOnly())) {
479          if (operand.GetOffsetImmediate() == 0) {
480            *this << ", #" << operand.GetSign() << operand.GetOffsetImmediate();
481          } else {
482            *this << ", #" << operand.GetOffsetImmediate();
483          }
484        }
485      } else if (operand.IsPlainRegister()) {
486        *this << ", " << operand.GetSign() << operand.GetOffsetRegister();
487      } else if (operand.IsShiftedRegister()) {
488        *this << ", " << operand.GetSign() << operand.GetOffsetRegister()
489              << ImmediateShiftOperand(operand.GetShift(),
490                                       operand.GetShiftAmount());
491      } else {
492        VIXL_UNREACHABLE();
493        return *this;
494      }
495      if (operand.GetAddrMode() == Offset) {
496        *this << "]";
497      } else if (operand.GetAddrMode() == PreIndex) {
498        *this << "]!";
499      }
500      return *this;
501    }
502    virtual DisassemblerStream& operator<<(const PrintMemOperand& operand) {
503      return *this << operand.GetOperand();
504    }
505    virtual DisassemblerStream& operator<<(const AlignedMemOperand& operand) {
506      *this << "[" << operand.GetBaseRegister() << operand.GetAlignment()
507            << "]";
508      if (operand.GetAddrMode() == PostIndex) {
509        if (operand.IsPlainRegister()) {
510          *this << ", " << operand.GetOffsetRegister();
511        } else {
512          *this << "!";
513        }
514      }
515      return *this;
516    }
517    virtual DisassemblerStream& operator<<(
518        const PrintAlignedMemOperand& operand) {
519      return *this << operand.GetOperand();
520    }
521  };
522
523 private:
524  class ITBlockScope {
525    ITBlock* const it_block_;
526    bool inside_;
527
528   public:
529    explicit ITBlockScope(ITBlock* it_block)
530        : it_block_(it_block), inside_(it_block->InITBlock()) {}
531    ~ITBlockScope() {
532      if (inside_) it_block_->Advance();
533    }
534  };
535
536  std::optional<AllocatorWrapper> allocator_;
537  ITBlock it_block_;
538  DisassemblerStream* os_;
539  bool owns_os_ {false};
540  uint32_t code_address_;
541  // True if the disassembler always output instructions with all the
542  // registers (even if two registers are identical and only one could be
543  // output).
544  bool use_short_hand_form_;
545
546 public:
547#ifndef PANDA_BUILD
548  explicit Disassembler(std::ostream& os,  // NOLINT(runtime/references)
549                        uint32_t code_address = 0)
550      : allocator_(std::make_optional<AllocatorWrapper>()),
551        os_(new DisassemblerStream(os)),
552#else
553    explicit Disassembler(std::ostream& os, uint32_t code_address = 0) = delete;
554    explicit Disassembler(PandaAllocator* allocator, std::ostream& os,  // NOLINT(runtime/references)
555                          uint32_t code_address = 0)
556        : allocator_(std::make_optional<AllocatorWrapper>(allocator)),
557          os_(allocator_->New<DisassemblerStream>(os)),
558#endif
559        owns_os_(true),
560        code_address_(code_address),
561        use_short_hand_form_(true) {}
562  explicit Disassembler(DisassemblerStream* os, uint32_t code_address = 0)
563      : os_(os),
564        owns_os_(false),
565        code_address_(code_address),
566        use_short_hand_form_(true) {}
567  virtual ~Disassembler() {
568    if (owns_os_) {
569      allocator_->DeleteObject(os_);
570    }
571  }
572  DisassemblerStream& os() const { return *os_; }
573  void SetIT(Condition first_condition, uint16_t it_mask) {
574    it_block_.Set(first_condition, it_mask);
575  }
576  const ITBlock& GetITBlock() const { return it_block_; }
577  bool InITBlock() const { return it_block_.InITBlock(); }
578  bool OutsideITBlock() const { return it_block_.OutsideITBlock(); }
579  bool OutsideITBlockOrLast() const { return it_block_.OutsideITBlockOrLast(); }
580  void CheckNotIT() const { VIXL_ASSERT(it_block_.OutsideITBlock()); }
581  // Return the current condition depending on the IT state for T32.
582  Condition CurrentCond() const {
583    if (it_block_.OutsideITBlock()) return al;
584    return it_block_.GetCurrentCondition();
585  }
586  bool UseShortHandForm() const { return use_short_hand_form_; }
587  void SetUseShortHandForm(bool use_short_hand_form) {
588    use_short_hand_form_ = use_short_hand_form;
589  }
590
591  virtual void UnallocatedT32(uint32_t instruction) {
592    if (T32Size(instruction) == 2) {
593      os() << "unallocated " << std::hex << std::setw(4) << std::setfill('0')
594           << (instruction >> 16) << std::dec;
595    } else {
596      os() << "unallocated " << std::hex << std::setw(8) << std::setfill('0')
597           << instruction << std::dec;
598    }
599  }
600  virtual void UnallocatedA32(uint32_t instruction) {
601    os() << "unallocated " << std::hex << std::setw(8) << std::setfill('0')
602         << instruction << std::dec;
603  }
604  virtual void UnimplementedT32_16(const char* name, uint32_t instruction) {
605    os() << "unimplemented " << name << " T32:" << std::hex << std::setw(4)
606         << std::setfill('0') << (instruction >> 16) << std::dec;
607  }
608  virtual void UnimplementedT32_32(const char* name, uint32_t instruction) {
609    os() << "unimplemented " << name << " T32:" << std::hex << std::setw(8)
610         << std::setfill('0') << instruction << std::dec;
611  }
612  virtual void UnimplementedA32(const char* name, uint32_t instruction) {
613    os() << "unimplemented " << name << " ARM:" << std::hex << std::setw(8)
614         << std::setfill('0') << instruction << std::dec;
615  }
616  virtual void Unpredictable() { os() << " ; unpredictable"; }
617  virtual void UnpredictableT32(uint32_t /*instr*/) { return Unpredictable(); }
618  virtual void UnpredictableA32(uint32_t /*instr*/) { return Unpredictable(); }
619
620  static bool Is16BitEncoding(uint32_t instr) { return instr < 0xe8000000; }
621  uint32_t GetCodeAddress() const { return code_address_; }
622  void SetCodeAddress(uint32_t code_address) { code_address_ = code_address; }
623
624  // Start of generated code.
625
626  void adc(Condition cond,
627           EncodingSize size,
628           Register rd,
629           Register rn,
630           const Operand& operand);
631
632  void adcs(Condition cond,
633            EncodingSize size,
634            Register rd,
635            Register rn,
636            const Operand& operand);
637
638  void add(Condition cond,
639           EncodingSize size,
640           Register rd,
641           Register rn,
642           const Operand& operand);
643
644  void add(Condition cond, Register rd, const Operand& operand);
645
646  void adds(Condition cond,
647            EncodingSize size,
648            Register rd,
649            Register rn,
650            const Operand& operand);
651
652  void adds(Register rd, const Operand& operand);
653
654  void addw(Condition cond, Register rd, Register rn, const Operand& operand);
655
656  void adr(Condition cond, EncodingSize size, Register rd, Location* location);
657
658  void and_(Condition cond,
659            EncodingSize size,
660            Register rd,
661            Register rn,
662            const Operand& operand);
663
664  void ands(Condition cond,
665            EncodingSize size,
666            Register rd,
667            Register rn,
668            const Operand& operand);
669
670  void asr(Condition cond,
671           EncodingSize size,
672           Register rd,
673           Register rm,
674           const Operand& operand);
675
676  void asrs(Condition cond,
677            EncodingSize size,
678            Register rd,
679            Register rm,
680            const Operand& operand);
681
682  void b(Condition cond, EncodingSize size, Location* location);
683
684  void bfc(Condition cond, Register rd, uint32_t lsb, uint32_t width);
685
686  void bfi(
687      Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width);
688
689  void bic(Condition cond,
690           EncodingSize size,
691           Register rd,
692           Register rn,
693           const Operand& operand);
694
695  void bics(Condition cond,
696            EncodingSize size,
697            Register rd,
698            Register rn,
699            const Operand& operand);
700
701  void bkpt(Condition cond, uint32_t imm);
702
703  void bl(Condition cond, Location* location);
704
705  void blx(Condition cond, Location* location);
706
707  void blx(Condition cond, Register rm);
708
709  void bx(Condition cond, Register rm);
710
711  void bxj(Condition cond, Register rm);
712
713  void cbnz(Register rn, Location* location);
714
715  void cbz(Register rn, Location* location);
716
717  void clrex(Condition cond);
718
719  void clz(Condition cond, Register rd, Register rm);
720
721  void cmn(Condition cond,
722           EncodingSize size,
723           Register rn,
724           const Operand& operand);
725
726  void cmp(Condition cond,
727           EncodingSize size,
728           Register rn,
729           const Operand& operand);
730
731  void crc32b(Condition cond, Register rd, Register rn, Register rm);
732
733  void crc32cb(Condition cond, Register rd, Register rn, Register rm);
734
735  void crc32ch(Condition cond, Register rd, Register rn, Register rm);
736
737  void crc32cw(Condition cond, Register rd, Register rn, Register rm);
738
739  void crc32h(Condition cond, Register rd, Register rn, Register rm);
740
741  void crc32w(Condition cond, Register rd, Register rn, Register rm);
742
743  void dmb(Condition cond, MemoryBarrier option);
744
745  void dsb(Condition cond, MemoryBarrier option);
746
747  void eor(Condition cond,
748           EncodingSize size,
749           Register rd,
750           Register rn,
751           const Operand& operand);
752
753  void eors(Condition cond,
754            EncodingSize size,
755            Register rd,
756            Register rn,
757            const Operand& operand);
758
759  void fldmdbx(Condition cond,
760               Register rn,
761               WriteBack write_back,
762               DRegisterList dreglist);
763
764  void fldmiax(Condition cond,
765               Register rn,
766               WriteBack write_back,
767               DRegisterList dreglist);
768
769  void fstmdbx(Condition cond,
770               Register rn,
771               WriteBack write_back,
772               DRegisterList dreglist);
773
774  void fstmiax(Condition cond,
775               Register rn,
776               WriteBack write_back,
777               DRegisterList dreglist);
778
779  void hlt(Condition cond, uint32_t imm);
780
781  void hvc(Condition cond, uint32_t imm);
782
783  void isb(Condition cond, MemoryBarrier option);
784
785  void it(Condition cond, uint16_t mask);
786
787  void lda(Condition cond, Register rt, const MemOperand& operand);
788
789  void ldab(Condition cond, Register rt, const MemOperand& operand);
790
791  void ldaex(Condition cond, Register rt, const MemOperand& operand);
792
793  void ldaexb(Condition cond, Register rt, const MemOperand& operand);
794
795  void ldaexd(Condition cond,
796              Register rt,
797              Register rt2,
798              const MemOperand& operand);
799
800  void ldaexh(Condition cond, Register rt, const MemOperand& operand);
801
802  void ldah(Condition cond, Register rt, const MemOperand& operand);
803
804  void ldm(Condition cond,
805           EncodingSize size,
806           Register rn,
807           WriteBack write_back,
808           RegisterList registers);
809
810  void ldmda(Condition cond,
811             Register rn,
812             WriteBack write_back,
813             RegisterList registers);
814
815  void ldmdb(Condition cond,
816             Register rn,
817             WriteBack write_back,
818             RegisterList registers);
819
820  void ldmea(Condition cond,
821             Register rn,
822             WriteBack write_back,
823             RegisterList registers);
824
825  void ldmed(Condition cond,
826             Register rn,
827             WriteBack write_back,
828             RegisterList registers);
829
830  void ldmfa(Condition cond,
831             Register rn,
832             WriteBack write_back,
833             RegisterList registers);
834
835  void ldmfd(Condition cond,
836             EncodingSize size,
837             Register rn,
838             WriteBack write_back,
839             RegisterList registers);
840
841  void ldmib(Condition cond,
842             Register rn,
843             WriteBack write_back,
844             RegisterList registers);
845
846  void ldr(Condition cond,
847           EncodingSize size,
848           Register rt,
849           const MemOperand& operand);
850
851  void ldr(Condition cond, EncodingSize size, Register rt, Location* location);
852
853  void ldrb(Condition cond,
854            EncodingSize size,
855            Register rt,
856            const MemOperand& operand);
857
858  void ldrb(Condition cond, Register rt, Location* location);
859
860  void ldrd(Condition cond,
861            Register rt,
862            Register rt2,
863            const MemOperand& operand);
864
865  void ldrd(Condition cond, Register rt, Register rt2, Location* location);
866
867  void ldrex(Condition cond, Register rt, const MemOperand& operand);
868
869  void ldrexb(Condition cond, Register rt, const MemOperand& operand);
870
871  void ldrexd(Condition cond,
872              Register rt,
873              Register rt2,
874              const MemOperand& operand);
875
876  void ldrexh(Condition cond, Register rt, const MemOperand& operand);
877
878  void ldrh(Condition cond,
879            EncodingSize size,
880            Register rt,
881            const MemOperand& operand);
882
883  void ldrh(Condition cond, Register rt, Location* location);
884
885  void ldrsb(Condition cond,
886             EncodingSize size,
887             Register rt,
888             const MemOperand& operand);
889
890  void ldrsb(Condition cond, Register rt, Location* location);
891
892  void ldrsh(Condition cond,
893             EncodingSize size,
894             Register rt,
895             const MemOperand& operand);
896
897  void ldrsh(Condition cond, Register rt, Location* location);
898
899  void lsl(Condition cond,
900           EncodingSize size,
901           Register rd,
902           Register rm,
903           const Operand& operand);
904
905  void lsls(Condition cond,
906            EncodingSize size,
907            Register rd,
908            Register rm,
909            const Operand& operand);
910
911  void lsr(Condition cond,
912           EncodingSize size,
913           Register rd,
914           Register rm,
915           const Operand& operand);
916
917  void lsrs(Condition cond,
918            EncodingSize size,
919            Register rd,
920            Register rm,
921            const Operand& operand);
922
923  void mla(Condition cond, Register rd, Register rn, Register rm, Register ra);
924
925  void mlas(Condition cond, Register rd, Register rn, Register rm, Register ra);
926
927  void mls(Condition cond, Register rd, Register rn, Register rm, Register ra);
928
929  void mov(Condition cond,
930           EncodingSize size,
931           Register rd,
932           const Operand& operand);
933
934  void movs(Condition cond,
935            EncodingSize size,
936            Register rd,
937            const Operand& operand);
938
939  void movt(Condition cond, Register rd, const Operand& operand);
940
941  void movw(Condition cond, Register rd, const Operand& operand);
942
943  void mrs(Condition cond, Register rd, SpecialRegister spec_reg);
944
945  void msr(Condition cond,
946           MaskedSpecialRegister spec_reg,
947           const Operand& operand);
948
949  void mul(
950      Condition cond, EncodingSize size, Register rd, Register rn, Register rm);
951
952  void muls(Condition cond, Register rd, Register rn, Register rm);
953
954  void mvn(Condition cond,
955           EncodingSize size,
956           Register rd,
957           const Operand& operand);
958
959  void mvns(Condition cond,
960            EncodingSize size,
961            Register rd,
962            const Operand& operand);
963
964  void nop(Condition cond, EncodingSize size);
965
966  void orn(Condition cond, Register rd, Register rn, const Operand& operand);
967
968  void orns(Condition cond, Register rd, Register rn, const Operand& operand);
969
970  void orr(Condition cond,
971           EncodingSize size,
972           Register rd,
973           Register rn,
974           const Operand& operand);
975
976  void orrs(Condition cond,
977            EncodingSize size,
978            Register rd,
979            Register rn,
980            const Operand& operand);
981
982  void pkhbt(Condition cond, Register rd, Register rn, const Operand& operand);
983
984  void pkhtb(Condition cond, Register rd, Register rn, const Operand& operand);
985
986  void pld(Condition cond, Location* location);
987
988  void pld(Condition cond, const MemOperand& operand);
989
990  void pldw(Condition cond, const MemOperand& operand);
991
992  void pli(Condition cond, const MemOperand& operand);
993
994  void pli(Condition cond, Location* location);
995
996  void pop(Condition cond, EncodingSize size, RegisterList registers);
997
998  void pop(Condition cond, EncodingSize size, Register rt);
999
1000  void push(Condition cond, EncodingSize size, RegisterList registers);
1001
1002  void push(Condition cond, EncodingSize size, Register rt);
1003
1004  void qadd(Condition cond, Register rd, Register rm, Register rn);
1005
1006  void qadd16(Condition cond, Register rd, Register rn, Register rm);
1007
1008  void qadd8(Condition cond, Register rd, Register rn, Register rm);
1009
1010  void qasx(Condition cond, Register rd, Register rn, Register rm);
1011
1012  void qdadd(Condition cond, Register rd, Register rm, Register rn);
1013
1014  void qdsub(Condition cond, Register rd, Register rm, Register rn);
1015
1016  void qsax(Condition cond, Register rd, Register rn, Register rm);
1017
1018  void qsub(Condition cond, Register rd, Register rm, Register rn);
1019
1020  void qsub16(Condition cond, Register rd, Register rn, Register rm);
1021
1022  void qsub8(Condition cond, Register rd, Register rn, Register rm);
1023
1024  void rbit(Condition cond, Register rd, Register rm);
1025
1026  void rev(Condition cond, EncodingSize size, Register rd, Register rm);
1027
1028  void rev16(Condition cond, EncodingSize size, Register rd, Register rm);
1029
1030  void revsh(Condition cond, EncodingSize size, Register rd, Register rm);
1031
1032  void ror(Condition cond,
1033           EncodingSize size,
1034           Register rd,
1035           Register rm,
1036           const Operand& operand);
1037
1038  void rors(Condition cond,
1039            EncodingSize size,
1040            Register rd,
1041            Register rm,
1042            const Operand& operand);
1043
1044  void rrx(Condition cond, Register rd, Register rm);
1045
1046  void rrxs(Condition cond, Register rd, Register rm);
1047
1048  void rsb(Condition cond,
1049           EncodingSize size,
1050           Register rd,
1051           Register rn,
1052           const Operand& operand);
1053
1054  void rsbs(Condition cond,
1055            EncodingSize size,
1056            Register rd,
1057            Register rn,
1058            const Operand& operand);
1059
1060  void rsc(Condition cond, Register rd, Register rn, const Operand& operand);
1061
1062  void rscs(Condition cond, Register rd, Register rn, const Operand& operand);
1063
1064  void sadd16(Condition cond, Register rd, Register rn, Register rm);
1065
1066  void sadd8(Condition cond, Register rd, Register rn, Register rm);
1067
1068  void sasx(Condition cond, Register rd, Register rn, Register rm);
1069
1070  void sbc(Condition cond,
1071           EncodingSize size,
1072           Register rd,
1073           Register rn,
1074           const Operand& operand);
1075
1076  void sbcs(Condition cond,
1077            EncodingSize size,
1078            Register rd,
1079            Register rn,
1080            const Operand& operand);
1081
1082  void sbfx(
1083      Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width);
1084
1085  void sdiv(Condition cond, Register rd, Register rn, Register rm);
1086
1087  void sel(Condition cond, Register rd, Register rn, Register rm);
1088
1089  void shadd16(Condition cond, Register rd, Register rn, Register rm);
1090
1091  void shadd8(Condition cond, Register rd, Register rn, Register rm);
1092
1093  void shasx(Condition cond, Register rd, Register rn, Register rm);
1094
1095  void shsax(Condition cond, Register rd, Register rn, Register rm);
1096
1097  void shsub16(Condition cond, Register rd, Register rn, Register rm);
1098
1099  void shsub8(Condition cond, Register rd, Register rn, Register rm);
1100
1101  void smlabb(
1102      Condition cond, Register rd, Register rn, Register rm, Register ra);
1103
1104  void smlabt(
1105      Condition cond, Register rd, Register rn, Register rm, Register ra);
1106
1107  void smlad(
1108      Condition cond, Register rd, Register rn, Register rm, Register ra);
1109
1110  void smladx(
1111      Condition cond, Register rd, Register rn, Register rm, Register ra);
1112
1113  void smlal(
1114      Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
1115
1116  void smlalbb(
1117      Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
1118
1119  void smlalbt(
1120      Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
1121
1122  void smlald(
1123      Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
1124
1125  void smlaldx(
1126      Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
1127
1128  void smlals(
1129      Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
1130
1131  void smlaltb(
1132      Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
1133
1134  void smlaltt(
1135      Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
1136
1137  void smlatb(
1138      Condition cond, Register rd, Register rn, Register rm, Register ra);
1139
1140  void smlatt(
1141      Condition cond, Register rd, Register rn, Register rm, Register ra);
1142
1143  void smlawb(
1144      Condition cond, Register rd, Register rn, Register rm, Register ra);
1145
1146  void smlawt(
1147      Condition cond, Register rd, Register rn, Register rm, Register ra);
1148
1149  void smlsd(
1150      Condition cond, Register rd, Register rn, Register rm, Register ra);
1151
1152  void smlsdx(
1153      Condition cond, Register rd, Register rn, Register rm, Register ra);
1154
1155  void smlsld(
1156      Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
1157
1158  void smlsldx(
1159      Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
1160
1161  void smmla(
1162      Condition cond, Register rd, Register rn, Register rm, Register ra);
1163
1164  void smmlar(
1165      Condition cond, Register rd, Register rn, Register rm, Register ra);
1166
1167  void smmls(
1168      Condition cond, Register rd, Register rn, Register rm, Register ra);
1169
1170  void smmlsr(
1171      Condition cond, Register rd, Register rn, Register rm, Register ra);
1172
1173  void smmul(Condition cond, Register rd, Register rn, Register rm);
1174
1175  void smmulr(Condition cond, Register rd, Register rn, Register rm);
1176
1177  void smuad(Condition cond, Register rd, Register rn, Register rm);
1178
1179  void smuadx(Condition cond, Register rd, Register rn, Register rm);
1180
1181  void smulbb(Condition cond, Register rd, Register rn, Register rm);
1182
1183  void smulbt(Condition cond, Register rd, Register rn, Register rm);
1184
1185  void smull(
1186      Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
1187
1188  void smulls(
1189      Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
1190
1191  void smultb(Condition cond, Register rd, Register rn, Register rm);
1192
1193  void smultt(Condition cond, Register rd, Register rn, Register rm);
1194
1195  void smulwb(Condition cond, Register rd, Register rn, Register rm);
1196
1197  void smulwt(Condition cond, Register rd, Register rn, Register rm);
1198
1199  void smusd(Condition cond, Register rd, Register rn, Register rm);
1200
1201  void smusdx(Condition cond, Register rd, Register rn, Register rm);
1202
1203  void ssat(Condition cond, Register rd, uint32_t imm, const Operand& operand);
1204
1205  void ssat16(Condition cond, Register rd, uint32_t imm, Register rn);
1206
1207  void ssax(Condition cond, Register rd, Register rn, Register rm);
1208
1209  void ssub16(Condition cond, Register rd, Register rn, Register rm);
1210
1211  void ssub8(Condition cond, Register rd, Register rn, Register rm);
1212
1213  void stl(Condition cond, Register rt, const MemOperand& operand);
1214
1215  void stlb(Condition cond, Register rt, const MemOperand& operand);
1216
1217  void stlex(Condition cond,
1218             Register rd,
1219             Register rt,
1220             const MemOperand& operand);
1221
1222  void stlexb(Condition cond,
1223              Register rd,
1224              Register rt,
1225              const MemOperand& operand);
1226
1227  void stlexd(Condition cond,
1228              Register rd,
1229              Register rt,
1230              Register rt2,
1231              const MemOperand& operand);
1232
1233  void stlexh(Condition cond,
1234              Register rd,
1235              Register rt,
1236              const MemOperand& operand);
1237
1238  void stlh(Condition cond, Register rt, const MemOperand& operand);
1239
1240  void stm(Condition cond,
1241           EncodingSize size,
1242           Register rn,
1243           WriteBack write_back,
1244           RegisterList registers);
1245
1246  void stmda(Condition cond,
1247             Register rn,
1248             WriteBack write_back,
1249             RegisterList registers);
1250
1251  void stmdb(Condition cond,
1252             EncodingSize size,
1253             Register rn,
1254             WriteBack write_back,
1255             RegisterList registers);
1256
1257  void stmea(Condition cond,
1258             EncodingSize size,
1259             Register rn,
1260             WriteBack write_back,
1261             RegisterList registers);
1262
1263  void stmed(Condition cond,
1264             Register rn,
1265             WriteBack write_back,
1266             RegisterList registers);
1267
1268  void stmfa(Condition cond,
1269             Register rn,
1270             WriteBack write_back,
1271             RegisterList registers);
1272
1273  void stmfd(Condition cond,
1274             Register rn,
1275             WriteBack write_back,
1276             RegisterList registers);
1277
1278  void stmib(Condition cond,
1279             Register rn,
1280             WriteBack write_back,
1281             RegisterList registers);
1282
1283  void str(Condition cond,
1284           EncodingSize size,
1285           Register rt,
1286           const MemOperand& operand);
1287
1288  void strb(Condition cond,
1289            EncodingSize size,
1290            Register rt,
1291            const MemOperand& operand);
1292
1293  void strd(Condition cond,
1294            Register rt,
1295            Register rt2,
1296            const MemOperand& operand);
1297
1298  void strex(Condition cond,
1299             Register rd,
1300             Register rt,
1301             const MemOperand& operand);
1302
1303  void strexb(Condition cond,
1304              Register rd,
1305              Register rt,
1306              const MemOperand& operand);
1307
1308  void strexd(Condition cond,
1309              Register rd,
1310              Register rt,
1311              Register rt2,
1312              const MemOperand& operand);
1313
1314  void strexh(Condition cond,
1315              Register rd,
1316              Register rt,
1317              const MemOperand& operand);
1318
1319  void strh(Condition cond,
1320            EncodingSize size,
1321            Register rt,
1322            const MemOperand& operand);
1323
1324  void sub(Condition cond,
1325           EncodingSize size,
1326           Register rd,
1327           Register rn,
1328           const Operand& operand);
1329
1330  void sub(Condition cond, Register rd, const Operand& operand);
1331
1332  void subs(Condition cond,
1333            EncodingSize size,
1334            Register rd,
1335            Register rn,
1336            const Operand& operand);
1337
1338  void subs(Register rd, const Operand& operand);
1339
1340  void subw(Condition cond, Register rd, Register rn, const Operand& operand);
1341
1342  void svc(Condition cond, uint32_t imm);
1343
1344  void sxtab(Condition cond, Register rd, Register rn, const Operand& operand);
1345
1346  void sxtab16(Condition cond,
1347               Register rd,
1348               Register rn,
1349               const Operand& operand);
1350
1351  void sxtah(Condition cond, Register rd, Register rn, const Operand& operand);
1352
1353  void sxtb(Condition cond,
1354            EncodingSize size,
1355            Register rd,
1356            const Operand& operand);
1357
1358  void sxtb16(Condition cond, Register rd, const Operand& operand);
1359
1360  void sxth(Condition cond,
1361            EncodingSize size,
1362            Register rd,
1363            const Operand& operand);
1364
1365  void tbb(Condition cond, Register rn, Register rm);
1366
1367  void tbh(Condition cond, Register rn, Register rm);
1368
1369  void teq(Condition cond, Register rn, const Operand& operand);
1370
1371  void tst(Condition cond,
1372           EncodingSize size,
1373           Register rn,
1374           const Operand& operand);
1375
1376  void uadd16(Condition cond, Register rd, Register rn, Register rm);
1377
1378  void uadd8(Condition cond, Register rd, Register rn, Register rm);
1379
1380  void uasx(Condition cond, Register rd, Register rn, Register rm);
1381
1382  void ubfx(
1383      Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width);
1384
1385  void udf(Condition cond, EncodingSize size, uint32_t imm);
1386
1387  void udiv(Condition cond, Register rd, Register rn, Register rm);
1388
1389  void uhadd16(Condition cond, Register rd, Register rn, Register rm);
1390
1391  void uhadd8(Condition cond, Register rd, Register rn, Register rm);
1392
1393  void uhasx(Condition cond, Register rd, Register rn, Register rm);
1394
1395  void uhsax(Condition cond, Register rd, Register rn, Register rm);
1396
1397  void uhsub16(Condition cond, Register rd, Register rn, Register rm);
1398
1399  void uhsub8(Condition cond, Register rd, Register rn, Register rm);
1400
1401  void umaal(
1402      Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
1403
1404  void umlal(
1405      Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
1406
1407  void umlals(
1408      Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
1409
1410  void umull(
1411      Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
1412
1413  void umulls(
1414      Condition cond, Register rdlo, Register rdhi, Register rn, Register rm);
1415
1416  void uqadd16(Condition cond, Register rd, Register rn, Register rm);
1417
1418  void uqadd8(Condition cond, Register rd, Register rn, Register rm);
1419
1420  void uqasx(Condition cond, Register rd, Register rn, Register rm);
1421
1422  void uqsax(Condition cond, Register rd, Register rn, Register rm);
1423
1424  void uqsub16(Condition cond, Register rd, Register rn, Register rm);
1425
1426  void uqsub8(Condition cond, Register rd, Register rn, Register rm);
1427
1428  void usad8(Condition cond, Register rd, Register rn, Register rm);
1429
1430  void usada8(
1431      Condition cond, Register rd, Register rn, Register rm, Register ra);
1432
1433  void usat(Condition cond, Register rd, uint32_t imm, const Operand& operand);
1434
1435  void usat16(Condition cond, Register rd, uint32_t imm, Register rn);
1436
1437  void usax(Condition cond, Register rd, Register rn, Register rm);
1438
1439  void usub16(Condition cond, Register rd, Register rn, Register rm);
1440
1441  void usub8(Condition cond, Register rd, Register rn, Register rm);
1442
1443  void uxtab(Condition cond, Register rd, Register rn, const Operand& operand);
1444
1445  void uxtab16(Condition cond,
1446               Register rd,
1447               Register rn,
1448               const Operand& operand);
1449
1450  void uxtah(Condition cond, Register rd, Register rn, const Operand& operand);
1451
1452  void uxtb(Condition cond,
1453            EncodingSize size,
1454            Register rd,
1455            const Operand& operand);
1456
1457  void uxtb16(Condition cond, Register rd, const Operand& operand);
1458
1459  void uxth(Condition cond,
1460            EncodingSize size,
1461            Register rd,
1462            const Operand& operand);
1463
1464  void vaba(
1465      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
1466
1467  void vaba(
1468      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
1469
1470  void vabal(
1471      Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm);
1472
1473  void vabd(
1474      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
1475
1476  void vabd(
1477      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
1478
1479  void vabdl(
1480      Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm);
1481
1482  void vabs(Condition cond, DataType dt, DRegister rd, DRegister rm);
1483
1484  void vabs(Condition cond, DataType dt, QRegister rd, QRegister rm);
1485
1486  void vabs(Condition cond, DataType dt, SRegister rd, SRegister rm);
1487
1488  void vacge(
1489      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
1490
1491  void vacge(
1492      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
1493
1494  void vacgt(
1495      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
1496
1497  void vacgt(
1498      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
1499
1500  void vacle(
1501      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
1502
1503  void vacle(
1504      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
1505
1506  void vaclt(
1507      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
1508
1509  void vaclt(
1510      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
1511
1512  void vadd(
1513      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
1514
1515  void vadd(
1516      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
1517
1518  void vadd(
1519      Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
1520
1521  void vaddhn(
1522      Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm);
1523
1524  void vaddl(
1525      Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm);
1526
1527  void vaddw(
1528      Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm);
1529
1530  void vand(Condition cond,
1531            DataType dt,
1532            DRegister rd,
1533            DRegister rn,
1534            const DOperand& operand);
1535
1536  void vand(Condition cond,
1537            DataType dt,
1538            QRegister rd,
1539            QRegister rn,
1540            const QOperand& operand);
1541
1542  void vbic(Condition cond,
1543            DataType dt,
1544            DRegister rd,
1545            DRegister rn,
1546            const DOperand& operand);
1547
1548  void vbic(Condition cond,
1549            DataType dt,
1550            QRegister rd,
1551            QRegister rn,
1552            const QOperand& operand);
1553
1554  void vbif(
1555      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
1556
1557  void vbif(
1558      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
1559
1560  void vbit(
1561      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
1562
1563  void vbit(
1564      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
1565
1566  void vbsl(
1567      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
1568
1569  void vbsl(
1570      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
1571
1572  void vceq(Condition cond,
1573            DataType dt,
1574            DRegister rd,
1575            DRegister rm,
1576            const DOperand& operand);
1577
1578  void vceq(Condition cond,
1579            DataType dt,
1580            QRegister rd,
1581            QRegister rm,
1582            const QOperand& operand);
1583
1584  void vceq(
1585      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
1586
1587  void vceq(
1588      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
1589
1590  void vcge(Condition cond,
1591            DataType dt,
1592            DRegister rd,
1593            DRegister rm,
1594            const DOperand& operand);
1595
1596  void vcge(Condition cond,
1597            DataType dt,
1598            QRegister rd,
1599            QRegister rm,
1600            const QOperand& operand);
1601
1602  void vcge(
1603      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
1604
1605  void vcge(
1606      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
1607
1608  void vcgt(Condition cond,
1609            DataType dt,
1610            DRegister rd,
1611            DRegister rm,
1612            const DOperand& operand);
1613
1614  void vcgt(Condition cond,
1615            DataType dt,
1616            QRegister rd,
1617            QRegister rm,
1618            const QOperand& operand);
1619
1620  void vcgt(
1621      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
1622
1623  void vcgt(
1624      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
1625
1626  void vcle(Condition cond,
1627            DataType dt,
1628            DRegister rd,
1629            DRegister rm,
1630            const DOperand& operand);
1631
1632  void vcle(Condition cond,
1633            DataType dt,
1634            QRegister rd,
1635            QRegister rm,
1636            const QOperand& operand);
1637
1638  void vcle(
1639      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
1640
1641  void vcle(
1642      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
1643
1644  void vcls(Condition cond, DataType dt, DRegister rd, DRegister rm);
1645
1646  void vcls(Condition cond, DataType dt, QRegister rd, QRegister rm);
1647
1648  void vclt(Condition cond,
1649            DataType dt,
1650            DRegister rd,
1651            DRegister rm,
1652            const DOperand& operand);
1653
1654  void vclt(Condition cond,
1655            DataType dt,
1656            QRegister rd,
1657            QRegister rm,
1658            const QOperand& operand);
1659
1660  void vclt(
1661      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
1662
1663  void vclt(
1664      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
1665
1666  void vclz(Condition cond, DataType dt, DRegister rd, DRegister rm);
1667
1668  void vclz(Condition cond, DataType dt, QRegister rd, QRegister rm);
1669
1670  void vcmp(Condition cond, DataType dt, SRegister rd, const SOperand& operand);
1671
1672  void vcmp(Condition cond, DataType dt, DRegister rd, const DOperand& operand);
1673
1674  void vcmpe(Condition cond,
1675             DataType dt,
1676             SRegister rd,
1677             const SOperand& operand);
1678
1679  void vcmpe(Condition cond,
1680             DataType dt,
1681             DRegister rd,
1682             const DOperand& operand);
1683
1684  void vcnt(Condition cond, DataType dt, DRegister rd, DRegister rm);
1685
1686  void vcnt(Condition cond, DataType dt, QRegister rd, QRegister rm);
1687
1688  void vcvt(
1689      Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm);
1690
1691  void vcvt(
1692      Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm);
1693
1694  void vcvt(Condition cond,
1695            DataType dt1,
1696            DataType dt2,
1697            DRegister rd,
1698            DRegister rm,
1699            int32_t fbits);
1700
1701  void vcvt(Condition cond,
1702            DataType dt1,
1703            DataType dt2,
1704            QRegister rd,
1705            QRegister rm,
1706            int32_t fbits);
1707
1708  void vcvt(Condition cond,
1709            DataType dt1,
1710            DataType dt2,
1711            SRegister rd,
1712            SRegister rm,
1713            int32_t fbits);
1714
1715  void vcvt(
1716      Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm);
1717
1718  void vcvt(
1719      Condition cond, DataType dt1, DataType dt2, QRegister rd, QRegister rm);
1720
1721  void vcvt(
1722      Condition cond, DataType dt1, DataType dt2, DRegister rd, QRegister rm);
1723
1724  void vcvt(
1725      Condition cond, DataType dt1, DataType dt2, QRegister rd, DRegister rm);
1726
1727  void vcvt(
1728      Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm);
1729
1730  void vcvta(DataType dt1, DataType dt2, DRegister rd, DRegister rm);
1731
1732  void vcvta(DataType dt1, DataType dt2, QRegister rd, QRegister rm);
1733
1734  void vcvta(DataType dt1, DataType dt2, SRegister rd, SRegister rm);
1735
1736  void vcvta(DataType dt1, DataType dt2, SRegister rd, DRegister rm);
1737
1738  void vcvtb(
1739      Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm);
1740
1741  void vcvtb(
1742      Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm);
1743
1744  void vcvtb(
1745      Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm);
1746
1747  void vcvtm(DataType dt1, DataType dt2, DRegister rd, DRegister rm);
1748
1749  void vcvtm(DataType dt1, DataType dt2, QRegister rd, QRegister rm);
1750
1751  void vcvtm(DataType dt1, DataType dt2, SRegister rd, SRegister rm);
1752
1753  void vcvtm(DataType dt1, DataType dt2, SRegister rd, DRegister rm);
1754
1755  void vcvtn(DataType dt1, DataType dt2, DRegister rd, DRegister rm);
1756
1757  void vcvtn(DataType dt1, DataType dt2, QRegister rd, QRegister rm);
1758
1759  void vcvtn(DataType dt1, DataType dt2, SRegister rd, SRegister rm);
1760
1761  void vcvtn(DataType dt1, DataType dt2, SRegister rd, DRegister rm);
1762
1763  void vcvtp(DataType dt1, DataType dt2, DRegister rd, DRegister rm);
1764
1765  void vcvtp(DataType dt1, DataType dt2, QRegister rd, QRegister rm);
1766
1767  void vcvtp(DataType dt1, DataType dt2, SRegister rd, SRegister rm);
1768
1769  void vcvtp(DataType dt1, DataType dt2, SRegister rd, DRegister rm);
1770
1771  void vcvtr(
1772      Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm);
1773
1774  void vcvtr(
1775      Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm);
1776
1777  void vcvtt(
1778      Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm);
1779
1780  void vcvtt(
1781      Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm);
1782
1783  void vcvtt(
1784      Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm);
1785
1786  void vdiv(
1787      Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
1788
1789  void vdiv(
1790      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
1791
1792  void vdup(Condition cond, DataType dt, QRegister rd, Register rt);
1793
1794  void vdup(Condition cond, DataType dt, DRegister rd, Register rt);
1795
1796  void vdup(Condition cond, DataType dt, DRegister rd, DRegisterLane rm);
1797
1798  void vdup(Condition cond, DataType dt, QRegister rd, DRegisterLane rm);
1799
1800  void veor(
1801      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
1802
1803  void veor(
1804      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
1805
1806  void vext(Condition cond,
1807            DataType dt,
1808            DRegister rd,
1809            DRegister rn,
1810            DRegister rm,
1811            const DOperand& operand);
1812
1813  void vext(Condition cond,
1814            DataType dt,
1815            QRegister rd,
1816            QRegister rn,
1817            QRegister rm,
1818            const QOperand& operand);
1819
1820  void vfma(
1821      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
1822
1823  void vfma(
1824      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
1825
1826  void vfma(
1827      Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
1828
1829  void vfms(
1830      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
1831
1832  void vfms(
1833      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
1834
1835  void vfms(
1836      Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
1837
1838  void vfnma(
1839      Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
1840
1841  void vfnma(
1842      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
1843
1844  void vfnms(
1845      Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
1846
1847  void vfnms(
1848      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
1849
1850  void vhadd(
1851      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
1852
1853  void vhadd(
1854      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
1855
1856  void vhsub(
1857      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
1858
1859  void vhsub(
1860      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
1861
1862  void vld1(Condition cond,
1863            DataType dt,
1864            const NeonRegisterList& nreglist,
1865            const AlignedMemOperand& operand);
1866
1867  void vld2(Condition cond,
1868            DataType dt,
1869            const NeonRegisterList& nreglist,
1870            const AlignedMemOperand& operand);
1871
1872  void vld3(Condition cond,
1873            DataType dt,
1874            const NeonRegisterList& nreglist,
1875            const AlignedMemOperand& operand);
1876
1877  void vld3(Condition cond,
1878            DataType dt,
1879            const NeonRegisterList& nreglist,
1880            const MemOperand& operand);
1881
1882  void vld4(Condition cond,
1883            DataType dt,
1884            const NeonRegisterList& nreglist,
1885            const AlignedMemOperand& operand);
1886
1887  void vldm(Condition cond,
1888            DataType dt,
1889            Register rn,
1890            WriteBack write_back,
1891            DRegisterList dreglist);
1892
1893  void vldm(Condition cond,
1894            DataType dt,
1895            Register rn,
1896            WriteBack write_back,
1897            SRegisterList sreglist);
1898
1899  void vldmdb(Condition cond,
1900              DataType dt,
1901              Register rn,
1902              WriteBack write_back,
1903              DRegisterList dreglist);
1904
1905  void vldmdb(Condition cond,
1906              DataType dt,
1907              Register rn,
1908              WriteBack write_back,
1909              SRegisterList sreglist);
1910
1911  void vldmia(Condition cond,
1912              DataType dt,
1913              Register rn,
1914              WriteBack write_back,
1915              DRegisterList dreglist);
1916
1917  void vldmia(Condition cond,
1918              DataType dt,
1919              Register rn,
1920              WriteBack write_back,
1921              SRegisterList sreglist);
1922
1923  void vldr(Condition cond, DataType dt, DRegister rd, Location* location);
1924
1925  void vldr(Condition cond,
1926            DataType dt,
1927            DRegister rd,
1928            const MemOperand& operand);
1929
1930  void vldr(Condition cond, DataType dt, SRegister rd, Location* location);
1931
1932  void vldr(Condition cond,
1933            DataType dt,
1934            SRegister rd,
1935            const MemOperand& operand);
1936
1937  void vmax(
1938      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
1939
1940  void vmax(
1941      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
1942
1943  void vmaxnm(DataType dt, DRegister rd, DRegister rn, DRegister rm);
1944
1945  void vmaxnm(DataType dt, QRegister rd, QRegister rn, QRegister rm);
1946
1947  void vmaxnm(DataType dt, SRegister rd, SRegister rn, SRegister rm);
1948
1949  void vmin(
1950      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
1951
1952  void vmin(
1953      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
1954
1955  void vminnm(DataType dt, DRegister rd, DRegister rn, DRegister rm);
1956
1957  void vminnm(DataType dt, QRegister rd, QRegister rn, QRegister rm);
1958
1959  void vminnm(DataType dt, SRegister rd, SRegister rn, SRegister rm);
1960
1961  void vmla(Condition cond,
1962            DataType dt,
1963            DRegister rd,
1964            DRegister rn,
1965            DRegisterLane rm);
1966
1967  void vmla(Condition cond,
1968            DataType dt,
1969            QRegister rd,
1970            QRegister rn,
1971            DRegisterLane rm);
1972
1973  void vmla(
1974      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
1975
1976  void vmla(
1977      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
1978
1979  void vmla(
1980      Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
1981
1982  void vmlal(Condition cond,
1983             DataType dt,
1984             QRegister rd,
1985             DRegister rn,
1986             DRegisterLane rm);
1987
1988  void vmlal(
1989      Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm);
1990
1991  void vmls(Condition cond,
1992            DataType dt,
1993            DRegister rd,
1994            DRegister rn,
1995            DRegisterLane rm);
1996
1997  void vmls(Condition cond,
1998            DataType dt,
1999            QRegister rd,
2000            QRegister rn,
2001            DRegisterLane rm);
2002
2003  void vmls(
2004      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
2005
2006  void vmls(
2007      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
2008
2009  void vmls(
2010      Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
2011
2012  void vmlsl(Condition cond,
2013             DataType dt,
2014             QRegister rd,
2015             DRegister rn,
2016             DRegisterLane rm);
2017
2018  void vmlsl(
2019      Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm);
2020
2021  void vmov(Condition cond, Register rt, SRegister rn);
2022
2023  void vmov(Condition cond, SRegister rn, Register rt);
2024
2025  void vmov(Condition cond, Register rt, Register rt2, DRegister rm);
2026
2027  void vmov(Condition cond, DRegister rm, Register rt, Register rt2);
2028
2029  void vmov(
2030      Condition cond, Register rt, Register rt2, SRegister rm, SRegister rm1);
2031
2032  void vmov(
2033      Condition cond, SRegister rm, SRegister rm1, Register rt, Register rt2);
2034
2035  void vmov(Condition cond, DataType dt, DRegisterLane rd, Register rt);
2036
2037  void vmov(Condition cond, DataType dt, DRegister rd, const DOperand& operand);
2038
2039  void vmov(Condition cond, DataType dt, QRegister rd, const QOperand& operand);
2040
2041  void vmov(Condition cond, DataType dt, SRegister rd, const SOperand& operand);
2042
2043  void vmov(Condition cond, DataType dt, Register rt, DRegisterLane rn);
2044
2045  void vmovl(Condition cond, DataType dt, QRegister rd, DRegister rm);
2046
2047  void vmovn(Condition cond, DataType dt, DRegister rd, QRegister rm);
2048
2049  void vmrs(Condition cond, RegisterOrAPSR_nzcv rt, SpecialFPRegister spec_reg);
2050
2051  void vmsr(Condition cond, SpecialFPRegister spec_reg, Register rt);
2052
2053  void vmul(Condition cond,
2054            DataType dt,
2055            DRegister rd,
2056            DRegister rn,
2057            DRegister dm,
2058            unsigned index);
2059
2060  void vmul(Condition cond,
2061            DataType dt,
2062            QRegister rd,
2063            QRegister rn,
2064            DRegister dm,
2065            unsigned index);
2066
2067  void vmul(
2068      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
2069
2070  void vmul(
2071      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
2072
2073  void vmul(
2074      Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
2075
2076  void vmull(Condition cond,
2077             DataType dt,
2078             QRegister rd,
2079             DRegister rn,
2080             DRegister dm,
2081             unsigned index);
2082
2083  void vmull(
2084      Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm);
2085
2086  void vmvn(Condition cond, DataType dt, DRegister rd, const DOperand& operand);
2087
2088  void vmvn(Condition cond, DataType dt, QRegister rd, const QOperand& operand);
2089
2090  void vneg(Condition cond, DataType dt, DRegister rd, DRegister rm);
2091
2092  void vneg(Condition cond, DataType dt, QRegister rd, QRegister rm);
2093
2094  void vneg(Condition cond, DataType dt, SRegister rd, SRegister rm);
2095
2096  void vnmla(
2097      Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
2098
2099  void vnmla(
2100      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
2101
2102  void vnmls(
2103      Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
2104
2105  void vnmls(
2106      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
2107
2108  void vnmul(
2109      Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
2110
2111  void vnmul(
2112      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
2113
2114  void vorn(Condition cond,
2115            DataType dt,
2116            DRegister rd,
2117            DRegister rn,
2118            const DOperand& operand);
2119
2120  void vorn(Condition cond,
2121            DataType dt,
2122            QRegister rd,
2123            QRegister rn,
2124            const QOperand& operand);
2125
2126  void vorr(Condition cond,
2127            DataType dt,
2128            DRegister rd,
2129            DRegister rn,
2130            const DOperand& operand);
2131
2132  void vorr(Condition cond,
2133            DataType dt,
2134            QRegister rd,
2135            QRegister rn,
2136            const QOperand& operand);
2137
2138  void vpadal(Condition cond, DataType dt, DRegister rd, DRegister rm);
2139
2140  void vpadal(Condition cond, DataType dt, QRegister rd, QRegister rm);
2141
2142  void vpadd(
2143      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
2144
2145  void vpaddl(Condition cond, DataType dt, DRegister rd, DRegister rm);
2146
2147  void vpaddl(Condition cond, DataType dt, QRegister rd, QRegister rm);
2148
2149  void vpmax(
2150      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
2151
2152  void vpmin(
2153      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
2154
2155  void vpop(Condition cond, DataType dt, DRegisterList dreglist);
2156
2157  void vpop(Condition cond, DataType dt, SRegisterList sreglist);
2158
2159  void vpush(Condition cond, DataType dt, DRegisterList dreglist);
2160
2161  void vpush(Condition cond, DataType dt, SRegisterList sreglist);
2162
2163  void vqabs(Condition cond, DataType dt, DRegister rd, DRegister rm);
2164
2165  void vqabs(Condition cond, DataType dt, QRegister rd, QRegister rm);
2166
2167  void vqadd(
2168      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
2169
2170  void vqadd(
2171      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
2172
2173  void vqdmlal(
2174      Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm);
2175
2176  void vqdmlal(Condition cond,
2177               DataType dt,
2178               QRegister rd,
2179               DRegister rn,
2180               DRegister dm,
2181               unsigned index);
2182
2183  void vqdmlsl(
2184      Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm);
2185
2186  void vqdmlsl(Condition cond,
2187               DataType dt,
2188               QRegister rd,
2189               DRegister rn,
2190               DRegister dm,
2191               unsigned index);
2192
2193  void vqdmulh(
2194      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
2195
2196  void vqdmulh(
2197      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
2198
2199  void vqdmulh(Condition cond,
2200               DataType dt,
2201               DRegister rd,
2202               DRegister rn,
2203               DRegisterLane rm);
2204
2205  void vqdmulh(Condition cond,
2206               DataType dt,
2207               QRegister rd,
2208               QRegister rn,
2209               DRegisterLane rm);
2210
2211  void vqdmull(
2212      Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm);
2213
2214  void vqdmull(Condition cond,
2215               DataType dt,
2216               QRegister rd,
2217               DRegister rn,
2218               DRegisterLane rm);
2219
2220  void vqmovn(Condition cond, DataType dt, DRegister rd, QRegister rm);
2221
2222  void vqmovun(Condition cond, DataType dt, DRegister rd, QRegister rm);
2223
2224  void vqneg(Condition cond, DataType dt, DRegister rd, DRegister rm);
2225
2226  void vqneg(Condition cond, DataType dt, QRegister rd, QRegister rm);
2227
2228  void vqrdmulh(
2229      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
2230
2231  void vqrdmulh(
2232      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
2233
2234  void vqrdmulh(Condition cond,
2235                DataType dt,
2236                DRegister rd,
2237                DRegister rn,
2238                DRegisterLane rm);
2239
2240  void vqrdmulh(Condition cond,
2241                DataType dt,
2242                QRegister rd,
2243                QRegister rn,
2244                DRegisterLane rm);
2245
2246  void vqrshl(
2247      Condition cond, DataType dt, DRegister rd, DRegister rm, DRegister rn);
2248
2249  void vqrshl(
2250      Condition cond, DataType dt, QRegister rd, QRegister rm, QRegister rn);
2251
2252  void vqrshrn(Condition cond,
2253               DataType dt,
2254               DRegister rd,
2255               QRegister rm,
2256               const QOperand& operand);
2257
2258  void vqrshrun(Condition cond,
2259                DataType dt,
2260                DRegister rd,
2261                QRegister rm,
2262                const QOperand& operand);
2263
2264  void vqshl(Condition cond,
2265             DataType dt,
2266             DRegister rd,
2267             DRegister rm,
2268             const DOperand& operand);
2269
2270  void vqshl(Condition cond,
2271             DataType dt,
2272             QRegister rd,
2273             QRegister rm,
2274             const QOperand& operand);
2275
2276  void vqshlu(Condition cond,
2277              DataType dt,
2278              DRegister rd,
2279              DRegister rm,
2280              const DOperand& operand);
2281
2282  void vqshlu(Condition cond,
2283              DataType dt,
2284              QRegister rd,
2285              QRegister rm,
2286              const QOperand& operand);
2287
2288  void vqshrn(Condition cond,
2289              DataType dt,
2290              DRegister rd,
2291              QRegister rm,
2292              const QOperand& operand);
2293
2294  void vqshrun(Condition cond,
2295               DataType dt,
2296               DRegister rd,
2297               QRegister rm,
2298               const QOperand& operand);
2299
2300  void vqsub(
2301      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
2302
2303  void vqsub(
2304      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
2305
2306  void vraddhn(
2307      Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm);
2308
2309  void vrecpe(Condition cond, DataType dt, DRegister rd, DRegister rm);
2310
2311  void vrecpe(Condition cond, DataType dt, QRegister rd, QRegister rm);
2312
2313  void vrecps(
2314      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
2315
2316  void vrecps(
2317      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
2318
2319  void vrev16(Condition cond, DataType dt, DRegister rd, DRegister rm);
2320
2321  void vrev16(Condition cond, DataType dt, QRegister rd, QRegister rm);
2322
2323  void vrev32(Condition cond, DataType dt, DRegister rd, DRegister rm);
2324
2325  void vrev32(Condition cond, DataType dt, QRegister rd, QRegister rm);
2326
2327  void vrev64(Condition cond, DataType dt, DRegister rd, DRegister rm);
2328
2329  void vrev64(Condition cond, DataType dt, QRegister rd, QRegister rm);
2330
2331  void vrhadd(
2332      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
2333
2334  void vrhadd(
2335      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
2336
2337  void vrinta(DataType dt, DRegister rd, DRegister rm);
2338
2339  void vrinta(DataType dt, QRegister rd, QRegister rm);
2340
2341  void vrinta(DataType dt, SRegister rd, SRegister rm);
2342
2343  void vrintm(DataType dt, DRegister rd, DRegister rm);
2344
2345  void vrintm(DataType dt, QRegister rd, QRegister rm);
2346
2347  void vrintm(DataType dt, SRegister rd, SRegister rm);
2348
2349  void vrintn(DataType dt, DRegister rd, DRegister rm);
2350
2351  void vrintn(DataType dt, QRegister rd, QRegister rm);
2352
2353  void vrintn(DataType dt, SRegister rd, SRegister rm);
2354
2355  void vrintp(DataType dt, DRegister rd, DRegister rm);
2356
2357  void vrintp(DataType dt, QRegister rd, QRegister rm);
2358
2359  void vrintp(DataType dt, SRegister rd, SRegister rm);
2360
2361  void vrintr(Condition cond, DataType dt, SRegister rd, SRegister rm);
2362
2363  void vrintr(Condition cond, DataType dt, DRegister rd, DRegister rm);
2364
2365  void vrintx(Condition cond, DataType dt, DRegister rd, DRegister rm);
2366
2367  void vrintx(DataType dt, QRegister rd, QRegister rm);
2368
2369  void vrintx(Condition cond, DataType dt, SRegister rd, SRegister rm);
2370
2371  void vrintz(Condition cond, DataType dt, DRegister rd, DRegister rm);
2372
2373  void vrintz(DataType dt, QRegister rd, QRegister rm);
2374
2375  void vrintz(Condition cond, DataType dt, SRegister rd, SRegister rm);
2376
2377  void vrshl(
2378      Condition cond, DataType dt, DRegister rd, DRegister rm, DRegister rn);
2379
2380  void vrshl(
2381      Condition cond, DataType dt, QRegister rd, QRegister rm, QRegister rn);
2382
2383  void vrshr(Condition cond,
2384             DataType dt,
2385             DRegister rd,
2386             DRegister rm,
2387             const DOperand& operand);
2388
2389  void vrshr(Condition cond,
2390             DataType dt,
2391             QRegister rd,
2392             QRegister rm,
2393             const QOperand& operand);
2394
2395  void vrshrn(Condition cond,
2396              DataType dt,
2397              DRegister rd,
2398              QRegister rm,
2399              const QOperand& operand);
2400
2401  void vrsqrte(Condition cond, DataType dt, DRegister rd, DRegister rm);
2402
2403  void vrsqrte(Condition cond, DataType dt, QRegister rd, QRegister rm);
2404
2405  void vrsqrts(
2406      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
2407
2408  void vrsqrts(
2409      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
2410
2411  void vrsra(Condition cond,
2412             DataType dt,
2413             DRegister rd,
2414             DRegister rm,
2415             const DOperand& operand);
2416
2417  void vrsra(Condition cond,
2418             DataType dt,
2419             QRegister rd,
2420             QRegister rm,
2421             const QOperand& operand);
2422
2423  void vrsubhn(
2424      Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm);
2425
2426  void vseleq(DataType dt, DRegister rd, DRegister rn, DRegister rm);
2427
2428  void vseleq(DataType dt, SRegister rd, SRegister rn, SRegister rm);
2429
2430  void vselge(DataType dt, DRegister rd, DRegister rn, DRegister rm);
2431
2432  void vselge(DataType dt, SRegister rd, SRegister rn, SRegister rm);
2433
2434  void vselgt(DataType dt, DRegister rd, DRegister rn, DRegister rm);
2435
2436  void vselgt(DataType dt, SRegister rd, SRegister rn, SRegister rm);
2437
2438  void vselvs(DataType dt, DRegister rd, DRegister rn, DRegister rm);
2439
2440  void vselvs(DataType dt, SRegister rd, SRegister rn, SRegister rm);
2441
2442  void vshl(Condition cond,
2443            DataType dt,
2444            DRegister rd,
2445            DRegister rm,
2446            const DOperand& operand);
2447
2448  void vshl(Condition cond,
2449            DataType dt,
2450            QRegister rd,
2451            QRegister rm,
2452            const QOperand& operand);
2453
2454  void vshll(Condition cond,
2455             DataType dt,
2456             QRegister rd,
2457             DRegister rm,
2458             const DOperand& operand);
2459
2460  void vshr(Condition cond,
2461            DataType dt,
2462            DRegister rd,
2463            DRegister rm,
2464            const DOperand& operand);
2465
2466  void vshr(Condition cond,
2467            DataType dt,
2468            QRegister rd,
2469            QRegister rm,
2470            const QOperand& operand);
2471
2472  void vshrn(Condition cond,
2473             DataType dt,
2474             DRegister rd,
2475             QRegister rm,
2476             const QOperand& operand);
2477
2478  void vsli(Condition cond,
2479            DataType dt,
2480            DRegister rd,
2481            DRegister rm,
2482            const DOperand& operand);
2483
2484  void vsli(Condition cond,
2485            DataType dt,
2486            QRegister rd,
2487            QRegister rm,
2488            const QOperand& operand);
2489
2490  void vsqrt(Condition cond, DataType dt, SRegister rd, SRegister rm);
2491
2492  void vsqrt(Condition cond, DataType dt, DRegister rd, DRegister rm);
2493
2494  void vsra(Condition cond,
2495            DataType dt,
2496            DRegister rd,
2497            DRegister rm,
2498            const DOperand& operand);
2499
2500  void vsra(Condition cond,
2501            DataType dt,
2502            QRegister rd,
2503            QRegister rm,
2504            const QOperand& operand);
2505
2506  void vsri(Condition cond,
2507            DataType dt,
2508            DRegister rd,
2509            DRegister rm,
2510            const DOperand& operand);
2511
2512  void vsri(Condition cond,
2513            DataType dt,
2514            QRegister rd,
2515            QRegister rm,
2516            const QOperand& operand);
2517
2518  void vst1(Condition cond,
2519            DataType dt,
2520            const NeonRegisterList& nreglist,
2521            const AlignedMemOperand& operand);
2522
2523  void vst2(Condition cond,
2524            DataType dt,
2525            const NeonRegisterList& nreglist,
2526            const AlignedMemOperand& operand);
2527
2528  void vst3(Condition cond,
2529            DataType dt,
2530            const NeonRegisterList& nreglist,
2531            const AlignedMemOperand& operand);
2532
2533  void vst3(Condition cond,
2534            DataType dt,
2535            const NeonRegisterList& nreglist,
2536            const MemOperand& operand);
2537
2538  void vst4(Condition cond,
2539            DataType dt,
2540            const NeonRegisterList& nreglist,
2541            const AlignedMemOperand& operand);
2542
2543  void vstm(Condition cond,
2544            DataType dt,
2545            Register rn,
2546            WriteBack write_back,
2547            DRegisterList dreglist);
2548
2549  void vstm(Condition cond,
2550            DataType dt,
2551            Register rn,
2552            WriteBack write_back,
2553            SRegisterList sreglist);
2554
2555  void vstmdb(Condition cond,
2556              DataType dt,
2557              Register rn,
2558              WriteBack write_back,
2559              DRegisterList dreglist);
2560
2561  void vstmdb(Condition cond,
2562              DataType dt,
2563              Register rn,
2564              WriteBack write_back,
2565              SRegisterList sreglist);
2566
2567  void vstmia(Condition cond,
2568              DataType dt,
2569              Register rn,
2570              WriteBack write_back,
2571              DRegisterList dreglist);
2572
2573  void vstmia(Condition cond,
2574              DataType dt,
2575              Register rn,
2576              WriteBack write_back,
2577              SRegisterList sreglist);
2578
2579  void vstr(Condition cond,
2580            DataType dt,
2581            DRegister rd,
2582            const MemOperand& operand);
2583
2584  void vstr(Condition cond,
2585            DataType dt,
2586            SRegister rd,
2587            const MemOperand& operand);
2588
2589  void vsub(
2590      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
2591
2592  void vsub(
2593      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
2594
2595  void vsub(
2596      Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
2597
2598  void vsubhn(
2599      Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm);
2600
2601  void vsubl(
2602      Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm);
2603
2604  void vsubw(
2605      Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm);
2606
2607  void vswp(Condition cond, DataType dt, DRegister rd, DRegister rm);
2608
2609  void vswp(Condition cond, DataType dt, QRegister rd, QRegister rm);
2610
2611  void vtbl(Condition cond,
2612            DataType dt,
2613            DRegister rd,
2614            const NeonRegisterList& nreglist,
2615            DRegister rm);
2616
2617  void vtbx(Condition cond,
2618            DataType dt,
2619            DRegister rd,
2620            const NeonRegisterList& nreglist,
2621            DRegister rm);
2622
2623  void vtrn(Condition cond, DataType dt, DRegister rd, DRegister rm);
2624
2625  void vtrn(Condition cond, DataType dt, QRegister rd, QRegister rm);
2626
2627  void vtst(
2628      Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
2629
2630  void vtst(
2631      Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm);
2632
2633  void vuzp(Condition cond, DataType dt, DRegister rd, DRegister rm);
2634
2635  void vuzp(Condition cond, DataType dt, QRegister rd, QRegister rm);
2636
2637  void vzip(Condition cond, DataType dt, DRegister rd, DRegister rm);
2638
2639  void vzip(Condition cond, DataType dt, QRegister rd, QRegister rm);
2640
2641  void yield(Condition cond, EncodingSize size);
2642
2643  int T32Size(uint32_t instr);
2644  void DecodeT32(uint32_t instr);
2645  void DecodeA32(uint32_t instr);
2646};
2647
2648DataTypeValue Dt_L_imm6_1_Decode(uint32_t value, uint32_t type_value);
2649DataTypeValue Dt_L_imm6_2_Decode(uint32_t value, uint32_t type_value);
2650DataTypeValue Dt_L_imm6_3_Decode(uint32_t value);
2651DataTypeValue Dt_L_imm6_4_Decode(uint32_t value);
2652DataTypeValue Dt_imm6_1_Decode(uint32_t value, uint32_t type_value);
2653DataTypeValue Dt_imm6_2_Decode(uint32_t value, uint32_t type_value);
2654DataTypeValue Dt_imm6_3_Decode(uint32_t value);
2655DataTypeValue Dt_imm6_4_Decode(uint32_t value, uint32_t type_value);
2656DataTypeValue Dt_op_U_size_1_Decode(uint32_t value);
2657DataTypeValue Dt_op_size_1_Decode(uint32_t value);
2658DataTypeValue Dt_op_size_2_Decode(uint32_t value);
2659DataTypeValue Dt_op_size_3_Decode(uint32_t value);
2660DataTypeValue Dt_U_imm3H_1_Decode(uint32_t value);
2661DataTypeValue Dt_U_opc1_opc2_1_Decode(uint32_t value, unsigned* lane);
2662DataTypeValue Dt_opc1_opc2_1_Decode(uint32_t value, unsigned* lane);
2663DataTypeValue Dt_imm4_1_Decode(uint32_t value, unsigned* lane);
2664DataTypeValue Dt_B_E_1_Decode(uint32_t value);
2665DataTypeValue Dt_op_1_Decode1(uint32_t value);
2666DataTypeValue Dt_op_1_Decode2(uint32_t value);
2667DataTypeValue Dt_op_2_Decode(uint32_t value);
2668DataTypeValue Dt_op_3_Decode(uint32_t value);
2669DataTypeValue Dt_U_sx_1_Decode(uint32_t value);
2670DataTypeValue Dt_op_U_1_Decode1(uint32_t value);
2671DataTypeValue Dt_op_U_1_Decode2(uint32_t value);
2672DataTypeValue Dt_sz_1_Decode(uint32_t value);
2673DataTypeValue Dt_F_size_1_Decode(uint32_t value);
2674DataTypeValue Dt_F_size_2_Decode(uint32_t value);
2675DataTypeValue Dt_F_size_3_Decode(uint32_t value);
2676DataTypeValue Dt_F_size_4_Decode(uint32_t value);
2677DataTypeValue Dt_U_size_1_Decode(uint32_t value);
2678DataTypeValue Dt_U_size_2_Decode(uint32_t value);
2679DataTypeValue Dt_U_size_3_Decode(uint32_t value);
2680DataTypeValue Dt_size_1_Decode(uint32_t value);
2681DataTypeValue Dt_size_2_Decode(uint32_t value);
2682DataTypeValue Dt_size_3_Decode(uint32_t value);
2683DataTypeValue Dt_size_4_Decode(uint32_t value);
2684DataTypeValue Dt_size_5_Decode(uint32_t value);
2685DataTypeValue Dt_size_6_Decode(uint32_t value);
2686DataTypeValue Dt_size_7_Decode(uint32_t value);
2687DataTypeValue Dt_size_8_Decode(uint32_t value);
2688DataTypeValue Dt_size_9_Decode(uint32_t value, uint32_t type_value);
2689DataTypeValue Dt_size_10_Decode(uint32_t value);
2690DataTypeValue Dt_size_11_Decode(uint32_t value, uint32_t type_value);
2691DataTypeValue Dt_size_12_Decode(uint32_t value, uint32_t type_value);
2692DataTypeValue Dt_size_13_Decode(uint32_t value);
2693DataTypeValue Dt_size_14_Decode(uint32_t value);
2694DataTypeValue Dt_size_15_Decode(uint32_t value);
2695DataTypeValue Dt_size_16_Decode(uint32_t value);
2696DataTypeValue Dt_size_17_Decode(uint32_t value);
2697// End of generated code.
2698
2699class PrintDisassembler : public Disassembler {
2700 public:
2701#ifndef PANDA_BUILD
2702  explicit PrintDisassembler(std::ostream& os,  // NOLINT(runtime/references)
2703                             uint32_t code_address = 0)
2704      : Disassembler(os, code_address) {}
2705#else
2706  explicit PrintDisassembler(std::ostream& os,  // NOLINT(runtime/references)
2707                           uint32_t code_address = 0) = delete;
2708  PrintDisassembler(PandaAllocator* allocator, std::ostream& os,  // NOLINT(runtime/references)
2709                          uint32_t code_address = 0)
2710    : Disassembler(allocator, os, code_address) {}
2711
2712#endif
2713  explicit PrintDisassembler(DisassemblerStream* os, uint32_t code_address = 0)
2714      : Disassembler(os, code_address) {}
2715
2716  virtual void PrintCodeAddress(uint32_t code_address) {
2717    if (code_address != 0) {
2718        os() << "0x" << std::hex << std::setw(8) << std::setfill('0')
2719             << code_address << "\t";
2720    }
2721  }
2722
2723  virtual void PrintOpcode16(uint32_t opcode) {
2724    os() << std::hex << std::setw(4) << std::setfill('0') << opcode << "    "
2725         << std::dec << "\t";
2726  }
2727
2728  virtual void PrintOpcode32(uint32_t opcode) {
2729    os() << std::hex << std::setw(8) << std::setfill('0') << opcode << std::dec
2730         << "\t";
2731  }
2732
2733  const uint32_t* DecodeA32At(const uint32_t* instruction_address) {
2734    DecodeA32(*instruction_address);
2735    return instruction_address + 1;
2736  }
2737
2738  // Returns the address of the next instruction.
2739  const uint16_t* DecodeT32At(const uint16_t* instruction_address,
2740                              const uint16_t* buffer_end);
2741  void DecodeT32(uint32_t instruction);
2742  void DecodeA32(uint32_t instruction);
2743  void DisassembleA32Buffer(const uint32_t* buffer, size_t size_in_bytes);
2744  void DisassembleT32Buffer(const uint16_t* buffer, size_t size_in_bytes);
2745};
2746
2747}  // namespace aarch32
2748}  // namespace vixl
2749
2750#endif  // VIXL_DISASM_AARCH32_H_
2751