1// Copyright 2014 the V8 project authors. All rights reserved. 2// Use of this source code is governed by a BSD-style license that can be 3// found in the LICENSE file. 4 5#ifndef V8_COMPILER_BACKEND_PPC_INSTRUCTION_CODES_PPC_H_ 6#define V8_COMPILER_BACKEND_PPC_INSTRUCTION_CODES_PPC_H_ 7 8namespace v8 { 9namespace internal { 10namespace compiler { 11 12// PPC-specific opcodes that specify which assembly sequence to emit. 13// Most opcodes specify a single instruction. 14 15#define TARGET_ARCH_OPCODE_LIST(V) \ 16 V(PPC_Peek) \ 17 V(PPC_Sync) \ 18 V(PPC_And) \ 19 V(PPC_AndComplement) \ 20 V(PPC_Or) \ 21 V(PPC_OrComplement) \ 22 V(PPC_Xor) \ 23 V(PPC_ShiftLeft32) \ 24 V(PPC_ShiftLeft64) \ 25 V(PPC_ShiftLeftPair) \ 26 V(PPC_ShiftRight32) \ 27 V(PPC_ShiftRight64) \ 28 V(PPC_ShiftRightPair) \ 29 V(PPC_ShiftRightAlg32) \ 30 V(PPC_ShiftRightAlg64) \ 31 V(PPC_ShiftRightAlgPair) \ 32 V(PPC_RotRight32) \ 33 V(PPC_RotRight64) \ 34 V(PPC_Not) \ 35 V(PPC_RotLeftAndMask32) \ 36 V(PPC_RotLeftAndClear64) \ 37 V(PPC_RotLeftAndClearLeft64) \ 38 V(PPC_RotLeftAndClearRight64) \ 39 V(PPC_Add32) \ 40 V(PPC_Add64) \ 41 V(PPC_AddWithOverflow32) \ 42 V(PPC_AddPair) \ 43 V(PPC_AddDouble) \ 44 V(PPC_Sub) \ 45 V(PPC_SubWithOverflow32) \ 46 V(PPC_SubPair) \ 47 V(PPC_SubDouble) \ 48 V(PPC_Mul32) \ 49 V(PPC_Mul32WithHigh32) \ 50 V(PPC_Mul64) \ 51 V(PPC_MulHigh32) \ 52 V(PPC_MulHighU32) \ 53 V(PPC_MulPair) \ 54 V(PPC_MulDouble) \ 55 V(PPC_Div32) \ 56 V(PPC_Div64) \ 57 V(PPC_DivU32) \ 58 V(PPC_DivU64) \ 59 V(PPC_DivDouble) \ 60 V(PPC_Mod32) \ 61 V(PPC_Mod64) \ 62 V(PPC_ModU32) \ 63 V(PPC_ModU64) \ 64 V(PPC_ModDouble) \ 65 V(PPC_Neg) \ 66 V(PPC_NegDouble) \ 67 V(PPC_SqrtDouble) \ 68 V(PPC_FloorDouble) \ 69 V(PPC_CeilDouble) \ 70 V(PPC_TruncateDouble) \ 71 V(PPC_RoundDouble) \ 72 V(PPC_MaxDouble) \ 73 V(PPC_MinDouble) \ 74 V(PPC_AbsDouble) \ 75 V(PPC_Cntlz32) \ 76 V(PPC_Cntlz64) \ 77 V(PPC_Popcnt32) \ 78 V(PPC_Popcnt64) \ 79 V(PPC_Cmp32) \ 80 V(PPC_Cmp64) \ 81 V(PPC_CmpDouble) \ 82 V(PPC_Tst32) \ 83 V(PPC_Tst64) \ 84 V(PPC_Push) \ 85 V(PPC_PushFrame) \ 86 V(PPC_StoreToStackSlot) \ 87 V(PPC_ExtendSignWord8) \ 88 V(PPC_ExtendSignWord16) \ 89 V(PPC_ExtendSignWord32) \ 90 V(PPC_Uint32ToUint64) \ 91 V(PPC_Int64ToInt32) \ 92 V(PPC_Int64ToFloat32) \ 93 V(PPC_Int64ToDouble) \ 94 V(PPC_Uint64ToFloat32) \ 95 V(PPC_Uint64ToDouble) \ 96 V(PPC_Int32ToFloat32) \ 97 V(PPC_Int32ToDouble) \ 98 V(PPC_Uint32ToFloat32) \ 99 V(PPC_Float32ToInt32) \ 100 V(PPC_Float32ToUint32) \ 101 V(PPC_Uint32ToDouble) \ 102 V(PPC_Float32ToDouble) \ 103 V(PPC_Float64SilenceNaN) \ 104 V(PPC_DoubleToInt32) \ 105 V(PPC_DoubleToUint32) \ 106 V(PPC_DoubleToInt64) \ 107 V(PPC_DoubleToUint64) \ 108 V(PPC_DoubleToFloat32) \ 109 V(PPC_DoubleExtractLowWord32) \ 110 V(PPC_DoubleExtractHighWord32) \ 111 V(PPC_DoubleInsertLowWord32) \ 112 V(PPC_DoubleInsertHighWord32) \ 113 V(PPC_DoubleConstruct) \ 114 V(PPC_BitcastInt32ToFloat32) \ 115 V(PPC_BitcastFloat32ToInt32) \ 116 V(PPC_BitcastInt64ToDouble) \ 117 V(PPC_BitcastDoubleToInt64) \ 118 V(PPC_LoadWordS8) \ 119 V(PPC_LoadWordU8) \ 120 V(PPC_LoadWordS16) \ 121 V(PPC_LoadWordU16) \ 122 V(PPC_LoadWordS32) \ 123 V(PPC_LoadWordU32) \ 124 V(PPC_LoadByteRev32) \ 125 V(PPC_LoadWord64) \ 126 V(PPC_LoadByteRev64) \ 127 V(PPC_LoadFloat32) \ 128 V(PPC_LoadDouble) \ 129 V(PPC_LoadSimd128) \ 130 V(PPC_LoadReverseSimd128RR) \ 131 V(PPC_StoreWord8) \ 132 V(PPC_StoreWord16) \ 133 V(PPC_StoreWord32) \ 134 V(PPC_StoreByteRev32) \ 135 V(PPC_StoreWord64) \ 136 V(PPC_StoreByteRev64) \ 137 V(PPC_StoreFloat32) \ 138 V(PPC_StoreDouble) \ 139 V(PPC_StoreSimd128) \ 140 V(PPC_ByteRev32) \ 141 V(PPC_ByteRev64) \ 142 V(PPC_AtomicExchangeUint8) \ 143 V(PPC_AtomicExchangeUint16) \ 144 V(PPC_AtomicExchangeWord32) \ 145 V(PPC_AtomicExchangeWord64) \ 146 V(PPC_AtomicCompareExchangeUint8) \ 147 V(PPC_AtomicCompareExchangeUint16) \ 148 V(PPC_AtomicCompareExchangeWord32) \ 149 V(PPC_AtomicCompareExchangeWord64) \ 150 V(PPC_AtomicAddUint8) \ 151 V(PPC_AtomicAddUint16) \ 152 V(PPC_AtomicAddUint32) \ 153 V(PPC_AtomicAddUint64) \ 154 V(PPC_AtomicAddInt8) \ 155 V(PPC_AtomicAddInt16) \ 156 V(PPC_AtomicAddInt32) \ 157 V(PPC_AtomicAddInt64) \ 158 V(PPC_AtomicSubUint8) \ 159 V(PPC_AtomicSubUint16) \ 160 V(PPC_AtomicSubUint32) \ 161 V(PPC_AtomicSubUint64) \ 162 V(PPC_AtomicSubInt8) \ 163 V(PPC_AtomicSubInt16) \ 164 V(PPC_AtomicSubInt32) \ 165 V(PPC_AtomicSubInt64) \ 166 V(PPC_AtomicAndUint8) \ 167 V(PPC_AtomicAndUint16) \ 168 V(PPC_AtomicAndUint32) \ 169 V(PPC_AtomicAndUint64) \ 170 V(PPC_AtomicAndInt8) \ 171 V(PPC_AtomicAndInt16) \ 172 V(PPC_AtomicAndInt32) \ 173 V(PPC_AtomicAndInt64) \ 174 V(PPC_AtomicOrUint8) \ 175 V(PPC_AtomicOrUint16) \ 176 V(PPC_AtomicOrUint32) \ 177 V(PPC_AtomicOrUint64) \ 178 V(PPC_AtomicOrInt8) \ 179 V(PPC_AtomicOrInt16) \ 180 V(PPC_AtomicOrInt32) \ 181 V(PPC_AtomicOrInt64) \ 182 V(PPC_AtomicXorUint8) \ 183 V(PPC_AtomicXorUint16) \ 184 V(PPC_AtomicXorUint32) \ 185 V(PPC_AtomicXorUint64) \ 186 V(PPC_AtomicXorInt8) \ 187 V(PPC_AtomicXorInt16) \ 188 V(PPC_AtomicXorInt32) \ 189 V(PPC_AtomicXorInt64) \ 190 V(PPC_F64x2Splat) \ 191 V(PPC_F64x2ExtractLane) \ 192 V(PPC_F64x2ReplaceLane) \ 193 V(PPC_F64x2Add) \ 194 V(PPC_F64x2Sub) \ 195 V(PPC_F64x2Mul) \ 196 V(PPC_F64x2Eq) \ 197 V(PPC_F64x2Ne) \ 198 V(PPC_F64x2Le) \ 199 V(PPC_F64x2Lt) \ 200 V(PPC_F64x2Abs) \ 201 V(PPC_F64x2Neg) \ 202 V(PPC_F64x2Sqrt) \ 203 V(PPC_F64x2Qfma) \ 204 V(PPC_F64x2Qfms) \ 205 V(PPC_F64x2Div) \ 206 V(PPC_F64x2Min) \ 207 V(PPC_F64x2Max) \ 208 V(PPC_F64x2Ceil) \ 209 V(PPC_F64x2Floor) \ 210 V(PPC_F64x2Trunc) \ 211 V(PPC_F64x2Pmin) \ 212 V(PPC_F64x2Pmax) \ 213 V(PPC_F64x2ConvertLowI32x4S) \ 214 V(PPC_F64x2ConvertLowI32x4U) \ 215 V(PPC_F64x2PromoteLowF32x4) \ 216 V(PPC_F32x4Splat) \ 217 V(PPC_F32x4ExtractLane) \ 218 V(PPC_F32x4ReplaceLane) \ 219 V(PPC_F32x4Add) \ 220 V(PPC_F32x4Sub) \ 221 V(PPC_F32x4Mul) \ 222 V(PPC_F32x4Eq) \ 223 V(PPC_F32x4Ne) \ 224 V(PPC_F32x4Lt) \ 225 V(PPC_F32x4Le) \ 226 V(PPC_F32x4Abs) \ 227 V(PPC_F32x4Neg) \ 228 V(PPC_F32x4RecipApprox) \ 229 V(PPC_F32x4RecipSqrtApprox) \ 230 V(PPC_F32x4Sqrt) \ 231 V(PPC_F32x4SConvertI32x4) \ 232 V(PPC_F32x4UConvertI32x4) \ 233 V(PPC_F32x4Div) \ 234 V(PPC_F32x4Min) \ 235 V(PPC_F32x4Max) \ 236 V(PPC_F32x4Ceil) \ 237 V(PPC_F32x4Floor) \ 238 V(PPC_F32x4Trunc) \ 239 V(PPC_F32x4Pmin) \ 240 V(PPC_F32x4Pmax) \ 241 V(PPC_F32x4Qfma) \ 242 V(PPC_F32x4Qfms) \ 243 V(PPC_F32x4DemoteF64x2Zero) \ 244 V(PPC_I64x2Splat) \ 245 V(PPC_I64x2ExtractLane) \ 246 V(PPC_I64x2ReplaceLane) \ 247 V(PPC_I64x2Add) \ 248 V(PPC_I64x2Sub) \ 249 V(PPC_I64x2Mul) \ 250 V(PPC_I64x2Eq) \ 251 V(PPC_I64x2Ne) \ 252 V(PPC_I64x2GtS) \ 253 V(PPC_I64x2GeS) \ 254 V(PPC_I64x2Shl) \ 255 V(PPC_I64x2ShrS) \ 256 V(PPC_I64x2ShrU) \ 257 V(PPC_I64x2Neg) \ 258 V(PPC_I64x2BitMask) \ 259 V(PPC_I64x2SConvertI32x4Low) \ 260 V(PPC_I64x2SConvertI32x4High) \ 261 V(PPC_I64x2UConvertI32x4Low) \ 262 V(PPC_I64x2UConvertI32x4High) \ 263 V(PPC_I64x2ExtMulLowI32x4S) \ 264 V(PPC_I64x2ExtMulHighI32x4S) \ 265 V(PPC_I64x2ExtMulLowI32x4U) \ 266 V(PPC_I64x2ExtMulHighI32x4U) \ 267 V(PPC_I64x2Abs) \ 268 V(PPC_I32x4Splat) \ 269 V(PPC_I32x4ExtractLane) \ 270 V(PPC_I32x4ReplaceLane) \ 271 V(PPC_I32x4Add) \ 272 V(PPC_I32x4Sub) \ 273 V(PPC_I32x4Mul) \ 274 V(PPC_I32x4MinS) \ 275 V(PPC_I32x4MinU) \ 276 V(PPC_I32x4MaxS) \ 277 V(PPC_I32x4MaxU) \ 278 V(PPC_I32x4Eq) \ 279 V(PPC_I32x4Ne) \ 280 V(PPC_I32x4GtS) \ 281 V(PPC_I32x4GeS) \ 282 V(PPC_I32x4GtU) \ 283 V(PPC_I32x4GeU) \ 284 V(PPC_I32x4Shl) \ 285 V(PPC_I32x4ShrS) \ 286 V(PPC_I32x4ShrU) \ 287 V(PPC_I32x4Neg) \ 288 V(PPC_I32x4Abs) \ 289 V(PPC_I32x4SConvertF32x4) \ 290 V(PPC_I32x4UConvertF32x4) \ 291 V(PPC_I32x4SConvertI16x8Low) \ 292 V(PPC_I32x4SConvertI16x8High) \ 293 V(PPC_I32x4UConvertI16x8Low) \ 294 V(PPC_I32x4UConvertI16x8High) \ 295 V(PPC_I32x4BitMask) \ 296 V(PPC_I32x4DotI16x8S) \ 297 V(PPC_I32x4ExtAddPairwiseI16x8S) \ 298 V(PPC_I32x4ExtAddPairwiseI16x8U) \ 299 V(PPC_I32x4ExtMulLowI16x8S) \ 300 V(PPC_I32x4ExtMulHighI16x8S) \ 301 V(PPC_I32x4ExtMulLowI16x8U) \ 302 V(PPC_I32x4ExtMulHighI16x8U) \ 303 V(PPC_I32x4TruncSatF64x2SZero) \ 304 V(PPC_I32x4TruncSatF64x2UZero) \ 305 V(PPC_I16x8Splat) \ 306 V(PPC_I16x8ExtractLaneU) \ 307 V(PPC_I16x8ExtractLaneS) \ 308 V(PPC_I16x8ReplaceLane) \ 309 V(PPC_I16x8Add) \ 310 V(PPC_I16x8Sub) \ 311 V(PPC_I16x8Mul) \ 312 V(PPC_I16x8MinS) \ 313 V(PPC_I16x8MinU) \ 314 V(PPC_I16x8MaxS) \ 315 V(PPC_I16x8MaxU) \ 316 V(PPC_I16x8Eq) \ 317 V(PPC_I16x8Ne) \ 318 V(PPC_I16x8GtS) \ 319 V(PPC_I16x8GeS) \ 320 V(PPC_I16x8GtU) \ 321 V(PPC_I16x8GeU) \ 322 V(PPC_I16x8Shl) \ 323 V(PPC_I16x8ShrS) \ 324 V(PPC_I16x8ShrU) \ 325 V(PPC_I16x8Neg) \ 326 V(PPC_I16x8Abs) \ 327 V(PPC_I16x8SConvertI32x4) \ 328 V(PPC_I16x8UConvertI32x4) \ 329 V(PPC_I16x8SConvertI8x16Low) \ 330 V(PPC_I16x8SConvertI8x16High) \ 331 V(PPC_I16x8UConvertI8x16Low) \ 332 V(PPC_I16x8UConvertI8x16High) \ 333 V(PPC_I16x8AddSatS) \ 334 V(PPC_I16x8SubSatS) \ 335 V(PPC_I16x8AddSatU) \ 336 V(PPC_I16x8SubSatU) \ 337 V(PPC_I16x8RoundingAverageU) \ 338 V(PPC_I16x8BitMask) \ 339 V(PPC_I16x8ExtAddPairwiseI8x16S) \ 340 V(PPC_I16x8ExtAddPairwiseI8x16U) \ 341 V(PPC_I16x8Q15MulRSatS) \ 342 V(PPC_I16x8ExtMulLowI8x16S) \ 343 V(PPC_I16x8ExtMulHighI8x16S) \ 344 V(PPC_I16x8ExtMulLowI8x16U) \ 345 V(PPC_I16x8ExtMulHighI8x16U) \ 346 V(PPC_I8x16Splat) \ 347 V(PPC_I8x16ExtractLaneU) \ 348 V(PPC_I8x16ExtractLaneS) \ 349 V(PPC_I8x16ReplaceLane) \ 350 V(PPC_I8x16Add) \ 351 V(PPC_I8x16Sub) \ 352 V(PPC_I8x16MinS) \ 353 V(PPC_I8x16MinU) \ 354 V(PPC_I8x16MaxS) \ 355 V(PPC_I8x16MaxU) \ 356 V(PPC_I8x16Eq) \ 357 V(PPC_I8x16Ne) \ 358 V(PPC_I8x16GtS) \ 359 V(PPC_I8x16GeS) \ 360 V(PPC_I8x16GtU) \ 361 V(PPC_I8x16GeU) \ 362 V(PPC_I8x16Shl) \ 363 V(PPC_I8x16ShrS) \ 364 V(PPC_I8x16ShrU) \ 365 V(PPC_I8x16Neg) \ 366 V(PPC_I8x16Abs) \ 367 V(PPC_I8x16SConvertI16x8) \ 368 V(PPC_I8x16UConvertI16x8) \ 369 V(PPC_I8x16AddSatS) \ 370 V(PPC_I8x16SubSatS) \ 371 V(PPC_I8x16AddSatU) \ 372 V(PPC_I8x16SubSatU) \ 373 V(PPC_I8x16RoundingAverageU) \ 374 V(PPC_I8x16Shuffle) \ 375 V(PPC_I8x16Swizzle) \ 376 V(PPC_I8x16BitMask) \ 377 V(PPC_I8x16Popcnt) \ 378 V(PPC_I64x2AllTrue) \ 379 V(PPC_I32x4AllTrue) \ 380 V(PPC_I16x8AllTrue) \ 381 V(PPC_I8x16AllTrue) \ 382 V(PPC_V128AnyTrue) \ 383 V(PPC_S128And) \ 384 V(PPC_S128Or) \ 385 V(PPC_S128Xor) \ 386 V(PPC_S128Const) \ 387 V(PPC_S128Zero) \ 388 V(PPC_S128AllOnes) \ 389 V(PPC_S128Not) \ 390 V(PPC_S128Select) \ 391 V(PPC_S128AndNot) \ 392 V(PPC_S128Load8Splat) \ 393 V(PPC_S128Load16Splat) \ 394 V(PPC_S128Load32Splat) \ 395 V(PPC_S128Load64Splat) \ 396 V(PPC_S128Load8x8S) \ 397 V(PPC_S128Load8x8U) \ 398 V(PPC_S128Load16x4S) \ 399 V(PPC_S128Load16x4U) \ 400 V(PPC_S128Load32x2S) \ 401 V(PPC_S128Load32x2U) \ 402 V(PPC_S128Load32Zero) \ 403 V(PPC_S128Load64Zero) \ 404 V(PPC_S128Load8Lane) \ 405 V(PPC_S128Load16Lane) \ 406 V(PPC_S128Load32Lane) \ 407 V(PPC_S128Load64Lane) \ 408 V(PPC_S128Store8Lane) \ 409 V(PPC_S128Store16Lane) \ 410 V(PPC_S128Store32Lane) \ 411 V(PPC_S128Store64Lane) \ 412 V(PPC_StoreCompressTagged) \ 413 V(PPC_LoadDecompressTaggedSigned) \ 414 V(PPC_LoadDecompressTaggedPointer) \ 415 V(PPC_LoadDecompressAnyTagged) 416 417// Addressing modes represent the "shape" of inputs to an instruction. 418// Many instructions support multiple addressing modes. Addressing modes 419// are encoded into the InstructionCode of the instruction and tell the 420// code generator after register allocation which assembler method to call. 421// 422// We use the following local notation for addressing modes: 423// 424// R = register 425// O = register or stack slot 426// D = double register 427// I = immediate (handle, external, int32) 428// MRI = [register + immediate] 429// MRR = [register + register] 430#define TARGET_ADDRESSING_MODE_LIST(V) \ 431 V(MRI) /* [%r0 + K] */ \ 432 V(MRR) /* [%r0 + %r1] */ 433 434} // namespace compiler 435} // namespace internal 436} // namespace v8 437 438#endif // V8_COMPILER_BACKEND_PPC_INSTRUCTION_CODES_PPC_H_ 439