1// Copyright 2014 the V8 project authors. All rights reserved. 2// Use of this source code is governed by a BSD-style license that can be 3// found in the LICENSE file. 4 5#ifndef V8_COMPILER_BACKEND_IA32_INSTRUCTION_CODES_IA32_H_ 6#define V8_COMPILER_BACKEND_IA32_INSTRUCTION_CODES_IA32_H_ 7 8namespace v8 { 9namespace internal { 10namespace compiler { 11 12// IA32-specific opcodes that specify which assembly sequence to emit. 13// Most opcodes specify a single instruction. 14 15#define TARGET_ARCH_OPCODE_LIST(V) \ 16 V(IA32Add) \ 17 V(IA32And) \ 18 V(IA32Cmp) \ 19 V(IA32Cmp16) \ 20 V(IA32Cmp8) \ 21 V(IA32Test) \ 22 V(IA32Test16) \ 23 V(IA32Test8) \ 24 V(IA32Or) \ 25 V(IA32Xor) \ 26 V(IA32Sub) \ 27 V(IA32Imul) \ 28 V(IA32ImulHigh) \ 29 V(IA32UmulHigh) \ 30 V(IA32Idiv) \ 31 V(IA32Udiv) \ 32 V(IA32Not) \ 33 V(IA32Neg) \ 34 V(IA32Shl) \ 35 V(IA32Shr) \ 36 V(IA32Sar) \ 37 V(IA32AddPair) \ 38 V(IA32SubPair) \ 39 V(IA32MulPair) \ 40 V(IA32ShlPair) \ 41 V(IA32ShrPair) \ 42 V(IA32SarPair) \ 43 V(IA32Rol) \ 44 V(IA32Ror) \ 45 V(IA32Lzcnt) \ 46 V(IA32Tzcnt) \ 47 V(IA32Popcnt) \ 48 V(IA32Bswap) \ 49 V(IA32MFence) \ 50 V(IA32LFence) \ 51 V(IA32Float32Cmp) \ 52 V(IA32Float32Sqrt) \ 53 V(IA32Float32Round) \ 54 V(IA32Float64Cmp) \ 55 V(IA32Float64Mod) \ 56 V(IA32Float32Max) \ 57 V(IA32Float64Max) \ 58 V(IA32Float32Min) \ 59 V(IA32Float64Min) \ 60 V(IA32Float64Sqrt) \ 61 V(IA32Float64Round) \ 62 V(IA32Float32ToFloat64) \ 63 V(IA32Float64ToFloat32) \ 64 V(IA32Float32ToInt32) \ 65 V(IA32Float32ToUint32) \ 66 V(IA32Float64ToInt32) \ 67 V(IA32Float64ToUint32) \ 68 V(SSEInt32ToFloat32) \ 69 V(IA32Uint32ToFloat32) \ 70 V(SSEInt32ToFloat64) \ 71 V(IA32Uint32ToFloat64) \ 72 V(IA32Float64ExtractLowWord32) \ 73 V(IA32Float64ExtractHighWord32) \ 74 V(IA32Float64InsertLowWord32) \ 75 V(IA32Float64InsertHighWord32) \ 76 V(IA32Float64LoadLowWord32) \ 77 V(IA32Float64SilenceNaN) \ 78 V(Float32Add) \ 79 V(Float32Sub) \ 80 V(Float64Add) \ 81 V(Float64Sub) \ 82 V(Float32Mul) \ 83 V(Float32Div) \ 84 V(Float64Mul) \ 85 V(Float64Div) \ 86 V(Float64Abs) \ 87 V(Float64Neg) \ 88 V(Float32Abs) \ 89 V(Float32Neg) \ 90 V(IA32Movsxbl) \ 91 V(IA32Movzxbl) \ 92 V(IA32Movb) \ 93 V(IA32Movsxwl) \ 94 V(IA32Movzxwl) \ 95 V(IA32Movw) \ 96 V(IA32Movl) \ 97 V(IA32Movss) \ 98 V(IA32Movsd) \ 99 V(IA32Movdqu) \ 100 V(IA32Movlps) \ 101 V(IA32Movhps) \ 102 V(IA32BitcastFI) \ 103 V(IA32BitcastIF) \ 104 V(IA32Lea) \ 105 V(IA32Pblendvb) \ 106 V(IA32Push) \ 107 V(IA32Poke) \ 108 V(IA32Peek) \ 109 V(IA32Cvttps2dq) \ 110 V(IA32Cvttpd2dq) \ 111 V(IA32I32x4TruncF32x4U) \ 112 V(IA32I32x4TruncF64x2UZero) \ 113 V(IA32F64x2Splat) \ 114 V(IA32F64x2ExtractLane) \ 115 V(IA32F64x2ReplaceLane) \ 116 V(IA32F64x2Sqrt) \ 117 V(IA32F64x2Add) \ 118 V(IA32F64x2Sub) \ 119 V(IA32F64x2Mul) \ 120 V(IA32F64x2Div) \ 121 V(IA32F64x2Min) \ 122 V(IA32F64x2Max) \ 123 V(IA32F64x2Eq) \ 124 V(IA32F64x2Ne) \ 125 V(IA32F64x2Lt) \ 126 V(IA32F64x2Le) \ 127 V(IA32F64x2Qfma) \ 128 V(IA32F64x2Qfms) \ 129 V(IA32Minpd) \ 130 V(IA32Maxpd) \ 131 V(IA32F64x2Round) \ 132 V(IA32F64x2ConvertLowI32x4S) \ 133 V(IA32F64x2ConvertLowI32x4U) \ 134 V(IA32F64x2PromoteLowF32x4) \ 135 V(IA32I64x2SplatI32Pair) \ 136 V(IA32I64x2ReplaceLaneI32Pair) \ 137 V(IA32I64x2Abs) \ 138 V(IA32I64x2Neg) \ 139 V(IA32I64x2Shl) \ 140 V(IA32I64x2ShrS) \ 141 V(IA32I64x2Add) \ 142 V(IA32I64x2Sub) \ 143 V(IA32I64x2Mul) \ 144 V(IA32I64x2ShrU) \ 145 V(IA32I64x2BitMask) \ 146 V(IA32I64x2Eq) \ 147 V(IA32I64x2Ne) \ 148 V(IA32I64x2GtS) \ 149 V(IA32I64x2GeS) \ 150 V(IA32I64x2ExtMulLowI32x4S) \ 151 V(IA32I64x2ExtMulHighI32x4S) \ 152 V(IA32I64x2ExtMulLowI32x4U) \ 153 V(IA32I64x2ExtMulHighI32x4U) \ 154 V(IA32I64x2SConvertI32x4Low) \ 155 V(IA32I64x2SConvertI32x4High) \ 156 V(IA32I64x2UConvertI32x4Low) \ 157 V(IA32I64x2UConvertI32x4High) \ 158 V(IA32F32x4Splat) \ 159 V(IA32F32x4ExtractLane) \ 160 V(IA32Insertps) \ 161 V(IA32F32x4SConvertI32x4) \ 162 V(IA32F32x4UConvertI32x4) \ 163 V(IA32F32x4Sqrt) \ 164 V(IA32F32x4RecipApprox) \ 165 V(IA32F32x4RecipSqrtApprox) \ 166 V(IA32F32x4Add) \ 167 V(IA32F32x4Sub) \ 168 V(IA32F32x4Mul) \ 169 V(IA32F32x4Div) \ 170 V(IA32F32x4Min) \ 171 V(IA32F32x4Max) \ 172 V(IA32F32x4Eq) \ 173 V(IA32F32x4Ne) \ 174 V(IA32F32x4Lt) \ 175 V(IA32F32x4Le) \ 176 V(IA32F32x4Qfma) \ 177 V(IA32F32x4Qfms) \ 178 V(IA32Minps) \ 179 V(IA32Maxps) \ 180 V(IA32F32x4Round) \ 181 V(IA32F32x4DemoteF64x2Zero) \ 182 V(IA32I32x4Splat) \ 183 V(IA32I32x4ExtractLane) \ 184 V(IA32I32x4SConvertF32x4) \ 185 V(IA32I32x4SConvertI16x8Low) \ 186 V(IA32I32x4SConvertI16x8High) \ 187 V(IA32I32x4Neg) \ 188 V(IA32I32x4Shl) \ 189 V(IA32I32x4ShrS) \ 190 V(IA32I32x4Add) \ 191 V(IA32I32x4Sub) \ 192 V(IA32I32x4Mul) \ 193 V(IA32I32x4MinS) \ 194 V(IA32I32x4MaxS) \ 195 V(IA32I32x4Eq) \ 196 V(IA32I32x4Ne) \ 197 V(IA32I32x4GtS) \ 198 V(IA32I32x4GeS) \ 199 V(SSEI32x4UConvertF32x4) \ 200 V(AVXI32x4UConvertF32x4) \ 201 V(IA32I32x4UConvertI16x8Low) \ 202 V(IA32I32x4UConvertI16x8High) \ 203 V(IA32I32x4ShrU) \ 204 V(IA32I32x4MinU) \ 205 V(IA32I32x4MaxU) \ 206 V(SSEI32x4GtU) \ 207 V(AVXI32x4GtU) \ 208 V(SSEI32x4GeU) \ 209 V(AVXI32x4GeU) \ 210 V(IA32I32x4Abs) \ 211 V(IA32I32x4BitMask) \ 212 V(IA32I32x4DotI16x8S) \ 213 V(IA32I32x4ExtMulLowI16x8S) \ 214 V(IA32I32x4ExtMulHighI16x8S) \ 215 V(IA32I32x4ExtMulLowI16x8U) \ 216 V(IA32I32x4ExtMulHighI16x8U) \ 217 V(IA32I32x4ExtAddPairwiseI16x8S) \ 218 V(IA32I32x4ExtAddPairwiseI16x8U) \ 219 V(IA32I32x4TruncSatF64x2SZero) \ 220 V(IA32I32x4TruncSatF64x2UZero) \ 221 V(IA32I16x8Splat) \ 222 V(IA32I16x8ExtractLaneS) \ 223 V(IA32I16x8SConvertI8x16Low) \ 224 V(IA32I16x8SConvertI8x16High) \ 225 V(IA32I16x8Neg) \ 226 V(IA32I16x8Shl) \ 227 V(IA32I16x8ShrS) \ 228 V(IA32I16x8SConvertI32x4) \ 229 V(IA32I16x8Add) \ 230 V(IA32I16x8AddSatS) \ 231 V(IA32I16x8Sub) \ 232 V(IA32I16x8SubSatS) \ 233 V(IA32I16x8Mul) \ 234 V(IA32I16x8MinS) \ 235 V(IA32I16x8MaxS) \ 236 V(IA32I16x8Eq) \ 237 V(SSEI16x8Ne) \ 238 V(AVXI16x8Ne) \ 239 V(IA32I16x8GtS) \ 240 V(SSEI16x8GeS) \ 241 V(AVXI16x8GeS) \ 242 V(IA32I16x8UConvertI8x16Low) \ 243 V(IA32I16x8UConvertI8x16High) \ 244 V(IA32I16x8ShrU) \ 245 V(IA32I16x8UConvertI32x4) \ 246 V(IA32I16x8AddSatU) \ 247 V(IA32I16x8SubSatU) \ 248 V(IA32I16x8MinU) \ 249 V(IA32I16x8MaxU) \ 250 V(SSEI16x8GtU) \ 251 V(AVXI16x8GtU) \ 252 V(SSEI16x8GeU) \ 253 V(AVXI16x8GeU) \ 254 V(IA32I16x8RoundingAverageU) \ 255 V(IA32I16x8Abs) \ 256 V(IA32I16x8BitMask) \ 257 V(IA32I16x8ExtMulLowI8x16S) \ 258 V(IA32I16x8ExtMulHighI8x16S) \ 259 V(IA32I16x8ExtMulLowI8x16U) \ 260 V(IA32I16x8ExtMulHighI8x16U) \ 261 V(IA32I16x8ExtAddPairwiseI8x16S) \ 262 V(IA32I16x8ExtAddPairwiseI8x16U) \ 263 V(IA32I16x8Q15MulRSatS) \ 264 V(IA32I8x16Splat) \ 265 V(IA32I8x16ExtractLaneS) \ 266 V(IA32Pinsrb) \ 267 V(IA32Pinsrw) \ 268 V(IA32Pinsrd) \ 269 V(IA32Pextrb) \ 270 V(IA32Pextrw) \ 271 V(IA32S128Store32Lane) \ 272 V(IA32I8x16SConvertI16x8) \ 273 V(IA32I8x16Neg) \ 274 V(IA32I8x16Shl) \ 275 V(IA32I8x16ShrS) \ 276 V(IA32I8x16Add) \ 277 V(IA32I8x16AddSatS) \ 278 V(IA32I8x16Sub) \ 279 V(IA32I8x16SubSatS) \ 280 V(IA32I8x16MinS) \ 281 V(IA32I8x16MaxS) \ 282 V(IA32I8x16Eq) \ 283 V(SSEI8x16Ne) \ 284 V(AVXI8x16Ne) \ 285 V(IA32I8x16GtS) \ 286 V(SSEI8x16GeS) \ 287 V(AVXI8x16GeS) \ 288 V(IA32I8x16UConvertI16x8) \ 289 V(IA32I8x16AddSatU) \ 290 V(IA32I8x16SubSatU) \ 291 V(IA32I8x16ShrU) \ 292 V(IA32I8x16MinU) \ 293 V(IA32I8x16MaxU) \ 294 V(SSEI8x16GtU) \ 295 V(AVXI8x16GtU) \ 296 V(SSEI8x16GeU) \ 297 V(AVXI8x16GeU) \ 298 V(IA32I8x16RoundingAverageU) \ 299 V(IA32I8x16Abs) \ 300 V(IA32I8x16BitMask) \ 301 V(IA32I8x16Popcnt) \ 302 V(IA32S128Const) \ 303 V(IA32S128Zero) \ 304 V(IA32S128AllOnes) \ 305 V(IA32S128Not) \ 306 V(IA32S128And) \ 307 V(IA32S128Or) \ 308 V(IA32S128Xor) \ 309 V(IA32S128Select) \ 310 V(IA32S128AndNot) \ 311 V(IA32I8x16Swizzle) \ 312 V(IA32I8x16Shuffle) \ 313 V(IA32S128Load8Splat) \ 314 V(IA32S128Load16Splat) \ 315 V(IA32S128Load32Splat) \ 316 V(IA32S128Load64Splat) \ 317 V(IA32S128Load8x8S) \ 318 V(IA32S128Load8x8U) \ 319 V(IA32S128Load16x4S) \ 320 V(IA32S128Load16x4U) \ 321 V(IA32S128Load32x2S) \ 322 V(IA32S128Load32x2U) \ 323 V(IA32S32x4Rotate) \ 324 V(IA32S32x4Swizzle) \ 325 V(IA32S32x4Shuffle) \ 326 V(IA32S16x8Blend) \ 327 V(IA32S16x8HalfShuffle1) \ 328 V(IA32S16x8HalfShuffle2) \ 329 V(IA32S8x16Alignr) \ 330 V(IA32S16x8Dup) \ 331 V(IA32S8x16Dup) \ 332 V(SSES16x8UnzipHigh) \ 333 V(AVXS16x8UnzipHigh) \ 334 V(SSES16x8UnzipLow) \ 335 V(AVXS16x8UnzipLow) \ 336 V(SSES8x16UnzipHigh) \ 337 V(AVXS8x16UnzipHigh) \ 338 V(SSES8x16UnzipLow) \ 339 V(AVXS8x16UnzipLow) \ 340 V(IA32S64x2UnpackHigh) \ 341 V(IA32S32x4UnpackHigh) \ 342 V(IA32S16x8UnpackHigh) \ 343 V(IA32S8x16UnpackHigh) \ 344 V(IA32S64x2UnpackLow) \ 345 V(IA32S32x4UnpackLow) \ 346 V(IA32S16x8UnpackLow) \ 347 V(IA32S8x16UnpackLow) \ 348 V(SSES8x16TransposeLow) \ 349 V(AVXS8x16TransposeLow) \ 350 V(SSES8x16TransposeHigh) \ 351 V(AVXS8x16TransposeHigh) \ 352 V(SSES8x8Reverse) \ 353 V(AVXS8x8Reverse) \ 354 V(SSES8x4Reverse) \ 355 V(AVXS8x4Reverse) \ 356 V(SSES8x2Reverse) \ 357 V(AVXS8x2Reverse) \ 358 V(IA32S128AnyTrue) \ 359 V(IA32I64x2AllTrue) \ 360 V(IA32I32x4AllTrue) \ 361 V(IA32I16x8AllTrue) \ 362 V(IA32I8x16AllTrue) \ 363 V(IA32Word32AtomicPairLoad) \ 364 V(IA32Word32ReleasePairStore) \ 365 V(IA32Word32SeqCstPairStore) \ 366 V(IA32Word32AtomicPairAdd) \ 367 V(IA32Word32AtomicPairSub) \ 368 V(IA32Word32AtomicPairAnd) \ 369 V(IA32Word32AtomicPairOr) \ 370 V(IA32Word32AtomicPairXor) \ 371 V(IA32Word32AtomicPairExchange) \ 372 V(IA32Word32AtomicPairCompareExchange) 373 374// Addressing modes represent the "shape" of inputs to an instruction. 375// Many instructions support multiple addressing modes. Addressing modes 376// are encoded into the InstructionCode of the instruction and tell the 377// code generator after register allocation which assembler method to call. 378// 379// We use the following local notation for addressing modes: 380// 381// M = memory operand 382// R = base register 383// N = index register * N for N in {1, 2, 4, 8} 384// I = immediate displacement (int32_t) 385 386#define TARGET_ADDRESSING_MODE_LIST(V) \ 387 V(MR) /* [%r1 ] */ \ 388 V(MRI) /* [%r1 + K] */ \ 389 V(MR1) /* [%r1 + %r2*1 ] */ \ 390 V(MR2) /* [%r1 + %r2*2 ] */ \ 391 V(MR4) /* [%r1 + %r2*4 ] */ \ 392 V(MR8) /* [%r1 + %r2*8 ] */ \ 393 V(MR1I) /* [%r1 + %r2*1 + K] */ \ 394 V(MR2I) /* [%r1 + %r2*2 + K] */ \ 395 V(MR4I) /* [%r1 + %r2*4 + K] */ \ 396 V(MR8I) /* [%r1 + %r2*8 + K] */ \ 397 V(M1) /* [ %r2*1 ] */ \ 398 V(M2) /* [ %r2*2 ] */ \ 399 V(M4) /* [ %r2*4 ] */ \ 400 V(M8) /* [ %r2*8 ] */ \ 401 V(M1I) /* [ %r2*1 + K] */ \ 402 V(M2I) /* [ %r2*2 + K] */ \ 403 V(M4I) /* [ %r2*4 + K] */ \ 404 V(M8I) /* [ %r2*8 + K] */ \ 405 V(MI) /* [ K] */ \ 406 V(Root) /* [%root + K] */ 407 408} // namespace compiler 409} // namespace internal 410} // namespace v8 411 412#endif // V8_COMPILER_BACKEND_IA32_INSTRUCTION_CODES_IA32_H_ 413