1// Copyright 2014 the V8 project authors. All rights reserved. 2// Use of this source code is governed by a BSD-style license that can be 3// found in the LICENSE file. 4 5#ifndef V8_COMPILER_BACKEND_ARM_INSTRUCTION_CODES_ARM_H_ 6#define V8_COMPILER_BACKEND_ARM_INSTRUCTION_CODES_ARM_H_ 7 8namespace v8 { 9namespace internal { 10namespace compiler { 11 12// ARM-specific opcodes that specify which assembly sequence to emit. 13// Most opcodes specify a single instruction. 14 15#define TARGET_ARCH_OPCODE_LIST(V) \ 16 V(ArmAdd) \ 17 V(ArmAnd) \ 18 V(ArmBic) \ 19 V(ArmClz) \ 20 V(ArmCmp) \ 21 V(ArmCmn) \ 22 V(ArmTst) \ 23 V(ArmTeq) \ 24 V(ArmOrr) \ 25 V(ArmEor) \ 26 V(ArmSub) \ 27 V(ArmRsb) \ 28 V(ArmMul) \ 29 V(ArmMla) \ 30 V(ArmMls) \ 31 V(ArmSmull) \ 32 V(ArmSmmul) \ 33 V(ArmSmmla) \ 34 V(ArmUmull) \ 35 V(ArmSdiv) \ 36 V(ArmUdiv) \ 37 V(ArmMov) \ 38 V(ArmMvn) \ 39 V(ArmBfc) \ 40 V(ArmUbfx) \ 41 V(ArmSbfx) \ 42 V(ArmSxtb) \ 43 V(ArmSxth) \ 44 V(ArmSxtab) \ 45 V(ArmSxtah) \ 46 V(ArmUxtb) \ 47 V(ArmUxth) \ 48 V(ArmUxtab) \ 49 V(ArmRbit) \ 50 V(ArmRev) \ 51 V(ArmUxtah) \ 52 V(ArmAddPair) \ 53 V(ArmSubPair) \ 54 V(ArmMulPair) \ 55 V(ArmLslPair) \ 56 V(ArmLsrPair) \ 57 V(ArmAsrPair) \ 58 V(ArmVcmpF32) \ 59 V(ArmVaddF32) \ 60 V(ArmVsubF32) \ 61 V(ArmVmulF32) \ 62 V(ArmVmlaF32) \ 63 V(ArmVmlsF32) \ 64 V(ArmVdivF32) \ 65 V(ArmVabsF32) \ 66 V(ArmVnegF32) \ 67 V(ArmVsqrtF32) \ 68 V(ArmVcmpF64) \ 69 V(ArmVaddF64) \ 70 V(ArmVsubF64) \ 71 V(ArmVmulF64) \ 72 V(ArmVmlaF64) \ 73 V(ArmVmlsF64) \ 74 V(ArmVdivF64) \ 75 V(ArmVmodF64) \ 76 V(ArmVabsF64) \ 77 V(ArmVnegF64) \ 78 V(ArmVsqrtF64) \ 79 V(ArmVmullLow) \ 80 V(ArmVmullHigh) \ 81 V(ArmVrintmF32) \ 82 V(ArmVrintmF64) \ 83 V(ArmVrintpF32) \ 84 V(ArmVrintpF64) \ 85 V(ArmVrintzF32) \ 86 V(ArmVrintzF64) \ 87 V(ArmVrintaF64) \ 88 V(ArmVrintnF32) \ 89 V(ArmVrintnF64) \ 90 V(ArmVcvtF32F64) \ 91 V(ArmVcvtF64F32) \ 92 V(ArmVcvtF32S32) \ 93 V(ArmVcvtF32U32) \ 94 V(ArmVcvtF64S32) \ 95 V(ArmVcvtF64U32) \ 96 V(ArmVcvtS32F32) \ 97 V(ArmVcvtU32F32) \ 98 V(ArmVcvtS32F64) \ 99 V(ArmVcvtU32F64) \ 100 V(ArmVmovU32F32) \ 101 V(ArmVmovF32U32) \ 102 V(ArmVmovLowU32F64) \ 103 V(ArmVmovLowF64U32) \ 104 V(ArmVmovHighU32F64) \ 105 V(ArmVmovHighF64U32) \ 106 V(ArmVmovF64U32U32) \ 107 V(ArmVmovU32U32F64) \ 108 V(ArmVldrF32) \ 109 V(ArmVstrF32) \ 110 V(ArmVldrF64) \ 111 V(ArmVld1F64) \ 112 V(ArmVstrF64) \ 113 V(ArmVst1F64) \ 114 V(ArmVld1S128) \ 115 V(ArmVst1S128) \ 116 V(ArmVcnt) \ 117 V(ArmVpadal) \ 118 V(ArmVpaddl) \ 119 V(ArmFloat32Max) \ 120 V(ArmFloat64Max) \ 121 V(ArmFloat32Min) \ 122 V(ArmFloat64Min) \ 123 V(ArmFloat64SilenceNaN) \ 124 V(ArmLdrb) \ 125 V(ArmLdrsb) \ 126 V(ArmStrb) \ 127 V(ArmLdrh) \ 128 V(ArmLdrsh) \ 129 V(ArmStrh) \ 130 V(ArmLdr) \ 131 V(ArmStr) \ 132 V(ArmPush) \ 133 V(ArmPoke) \ 134 V(ArmPeek) \ 135 V(ArmDmbIsh) \ 136 V(ArmDsbIsb) \ 137 V(ArmF64x2Splat) \ 138 V(ArmF64x2ExtractLane) \ 139 V(ArmF64x2ReplaceLane) \ 140 V(ArmF64x2Abs) \ 141 V(ArmF64x2Neg) \ 142 V(ArmF64x2Sqrt) \ 143 V(ArmF64x2Add) \ 144 V(ArmF64x2Sub) \ 145 V(ArmF64x2Mul) \ 146 V(ArmF64x2Div) \ 147 V(ArmF64x2Min) \ 148 V(ArmF64x2Max) \ 149 V(ArmF64x2Eq) \ 150 V(ArmF64x2Ne) \ 151 V(ArmF64x2Lt) \ 152 V(ArmF64x2Le) \ 153 V(ArmF64x2Pmin) \ 154 V(ArmF64x2Pmax) \ 155 V(ArmF64x2Ceil) \ 156 V(ArmF64x2Floor) \ 157 V(ArmF64x2Trunc) \ 158 V(ArmF64x2NearestInt) \ 159 V(ArmF64x2ConvertLowI32x4S) \ 160 V(ArmF64x2ConvertLowI32x4U) \ 161 V(ArmF64x2PromoteLowF32x4) \ 162 V(ArmF32x4Splat) \ 163 V(ArmF32x4ExtractLane) \ 164 V(ArmF32x4ReplaceLane) \ 165 V(ArmF32x4SConvertI32x4) \ 166 V(ArmF32x4UConvertI32x4) \ 167 V(ArmF32x4Abs) \ 168 V(ArmF32x4Neg) \ 169 V(ArmF32x4Sqrt) \ 170 V(ArmF32x4RecipApprox) \ 171 V(ArmF32x4RecipSqrtApprox) \ 172 V(ArmF32x4Add) \ 173 V(ArmF32x4Sub) \ 174 V(ArmF32x4Mul) \ 175 V(ArmF32x4Div) \ 176 V(ArmF32x4Min) \ 177 V(ArmF32x4Max) \ 178 V(ArmF32x4Eq) \ 179 V(ArmF32x4Ne) \ 180 V(ArmF32x4Lt) \ 181 V(ArmF32x4Le) \ 182 V(ArmF32x4Pmin) \ 183 V(ArmF32x4Pmax) \ 184 V(ArmF32x4DemoteF64x2Zero) \ 185 V(ArmI64x2SplatI32Pair) \ 186 V(ArmI64x2ReplaceLaneI32Pair) \ 187 V(ArmI64x2Abs) \ 188 V(ArmI64x2Neg) \ 189 V(ArmI64x2Shl) \ 190 V(ArmI64x2ShrS) \ 191 V(ArmI64x2Add) \ 192 V(ArmI64x2Sub) \ 193 V(ArmI64x2Mul) \ 194 V(ArmI64x2ShrU) \ 195 V(ArmI64x2BitMask) \ 196 V(ArmI64x2Eq) \ 197 V(ArmI64x2Ne) \ 198 V(ArmI64x2GtS) \ 199 V(ArmI64x2GeS) \ 200 V(ArmI64x2SConvertI32x4Low) \ 201 V(ArmI64x2SConvertI32x4High) \ 202 V(ArmI64x2UConvertI32x4Low) \ 203 V(ArmI64x2UConvertI32x4High) \ 204 V(ArmI32x4Splat) \ 205 V(ArmI32x4ExtractLane) \ 206 V(ArmI32x4ReplaceLane) \ 207 V(ArmI32x4SConvertF32x4) \ 208 V(ArmI32x4SConvertI16x8Low) \ 209 V(ArmI32x4SConvertI16x8High) \ 210 V(ArmI32x4Neg) \ 211 V(ArmI32x4Shl) \ 212 V(ArmI32x4ShrS) \ 213 V(ArmI32x4Add) \ 214 V(ArmI32x4Sub) \ 215 V(ArmI32x4Mul) \ 216 V(ArmI32x4MinS) \ 217 V(ArmI32x4MaxS) \ 218 V(ArmI32x4Eq) \ 219 V(ArmI32x4Ne) \ 220 V(ArmI32x4GtS) \ 221 V(ArmI32x4GeS) \ 222 V(ArmI32x4UConvertF32x4) \ 223 V(ArmI32x4UConvertI16x8Low) \ 224 V(ArmI32x4UConvertI16x8High) \ 225 V(ArmI32x4ShrU) \ 226 V(ArmI32x4MinU) \ 227 V(ArmI32x4MaxU) \ 228 V(ArmI32x4GtU) \ 229 V(ArmI32x4GeU) \ 230 V(ArmI32x4Abs) \ 231 V(ArmI32x4BitMask) \ 232 V(ArmI32x4DotI16x8S) \ 233 V(ArmI32x4TruncSatF64x2SZero) \ 234 V(ArmI32x4TruncSatF64x2UZero) \ 235 V(ArmI16x8Splat) \ 236 V(ArmI16x8ExtractLaneS) \ 237 V(ArmI16x8ReplaceLane) \ 238 V(ArmI16x8SConvertI8x16Low) \ 239 V(ArmI16x8SConvertI8x16High) \ 240 V(ArmI16x8Neg) \ 241 V(ArmI16x8Shl) \ 242 V(ArmI16x8ShrS) \ 243 V(ArmI16x8SConvertI32x4) \ 244 V(ArmI16x8Add) \ 245 V(ArmI16x8AddSatS) \ 246 V(ArmI16x8Sub) \ 247 V(ArmI16x8SubSatS) \ 248 V(ArmI16x8Mul) \ 249 V(ArmI16x8MinS) \ 250 V(ArmI16x8MaxS) \ 251 V(ArmI16x8Eq) \ 252 V(ArmI16x8Ne) \ 253 V(ArmI16x8GtS) \ 254 V(ArmI16x8GeS) \ 255 V(ArmI16x8ExtractLaneU) \ 256 V(ArmI16x8UConvertI8x16Low) \ 257 V(ArmI16x8UConvertI8x16High) \ 258 V(ArmI16x8ShrU) \ 259 V(ArmI16x8UConvertI32x4) \ 260 V(ArmI16x8AddSatU) \ 261 V(ArmI16x8SubSatU) \ 262 V(ArmI16x8MinU) \ 263 V(ArmI16x8MaxU) \ 264 V(ArmI16x8GtU) \ 265 V(ArmI16x8GeU) \ 266 V(ArmI16x8RoundingAverageU) \ 267 V(ArmI16x8Abs) \ 268 V(ArmI16x8BitMask) \ 269 V(ArmI16x8Q15MulRSatS) \ 270 V(ArmI8x16Splat) \ 271 V(ArmI8x16ExtractLaneS) \ 272 V(ArmI8x16ReplaceLane) \ 273 V(ArmI8x16Neg) \ 274 V(ArmI8x16Shl) \ 275 V(ArmI8x16ShrS) \ 276 V(ArmI8x16SConvertI16x8) \ 277 V(ArmI8x16Add) \ 278 V(ArmI8x16AddSatS) \ 279 V(ArmI8x16Sub) \ 280 V(ArmI8x16SubSatS) \ 281 V(ArmI8x16MinS) \ 282 V(ArmI8x16MaxS) \ 283 V(ArmI8x16Eq) \ 284 V(ArmI8x16Ne) \ 285 V(ArmI8x16GtS) \ 286 V(ArmI8x16GeS) \ 287 V(ArmI8x16ExtractLaneU) \ 288 V(ArmI8x16ShrU) \ 289 V(ArmI8x16UConvertI16x8) \ 290 V(ArmI8x16AddSatU) \ 291 V(ArmI8x16SubSatU) \ 292 V(ArmI8x16MinU) \ 293 V(ArmI8x16MaxU) \ 294 V(ArmI8x16GtU) \ 295 V(ArmI8x16GeU) \ 296 V(ArmI8x16RoundingAverageU) \ 297 V(ArmI8x16Abs) \ 298 V(ArmI8x16BitMask) \ 299 V(ArmS128Const) \ 300 V(ArmS128Zero) \ 301 V(ArmS128AllOnes) \ 302 V(ArmS128Dup) \ 303 V(ArmS128And) \ 304 V(ArmS128Or) \ 305 V(ArmS128Xor) \ 306 V(ArmS128Not) \ 307 V(ArmS128Select) \ 308 V(ArmS128AndNot) \ 309 V(ArmS32x4ZipLeft) \ 310 V(ArmS32x4ZipRight) \ 311 V(ArmS32x4UnzipLeft) \ 312 V(ArmS32x4UnzipRight) \ 313 V(ArmS32x4TransposeLeft) \ 314 V(ArmS32x4TransposeRight) \ 315 V(ArmS32x4Shuffle) \ 316 V(ArmS16x8ZipLeft) \ 317 V(ArmS16x8ZipRight) \ 318 V(ArmS16x8UnzipLeft) \ 319 V(ArmS16x8UnzipRight) \ 320 V(ArmS16x8TransposeLeft) \ 321 V(ArmS16x8TransposeRight) \ 322 V(ArmS8x16ZipLeft) \ 323 V(ArmS8x16ZipRight) \ 324 V(ArmS8x16UnzipLeft) \ 325 V(ArmS8x16UnzipRight) \ 326 V(ArmS8x16TransposeLeft) \ 327 V(ArmS8x16TransposeRight) \ 328 V(ArmS8x16Concat) \ 329 V(ArmI8x16Swizzle) \ 330 V(ArmI8x16Shuffle) \ 331 V(ArmS32x2Reverse) \ 332 V(ArmS16x4Reverse) \ 333 V(ArmS16x2Reverse) \ 334 V(ArmS8x8Reverse) \ 335 V(ArmS8x4Reverse) \ 336 V(ArmS8x2Reverse) \ 337 V(ArmI64x2AllTrue) \ 338 V(ArmI32x4AllTrue) \ 339 V(ArmI16x8AllTrue) \ 340 V(ArmV128AnyTrue) \ 341 V(ArmI8x16AllTrue) \ 342 V(ArmS128Load8Splat) \ 343 V(ArmS128Load16Splat) \ 344 V(ArmS128Load32Splat) \ 345 V(ArmS128Load64Splat) \ 346 V(ArmS128Load8x8S) \ 347 V(ArmS128Load8x8U) \ 348 V(ArmS128Load16x4S) \ 349 V(ArmS128Load16x4U) \ 350 V(ArmS128Load32x2S) \ 351 V(ArmS128Load32x2U) \ 352 V(ArmS128Load32Zero) \ 353 V(ArmS128Load64Zero) \ 354 V(ArmS128LoadLaneLow) \ 355 V(ArmS128LoadLaneHigh) \ 356 V(ArmS128StoreLaneLow) \ 357 V(ArmS128StoreLaneHigh) \ 358 V(ArmWord32AtomicPairLoad) \ 359 V(ArmWord32AtomicPairStore) \ 360 V(ArmWord32AtomicPairAdd) \ 361 V(ArmWord32AtomicPairSub) \ 362 V(ArmWord32AtomicPairAnd) \ 363 V(ArmWord32AtomicPairOr) \ 364 V(ArmWord32AtomicPairXor) \ 365 V(ArmWord32AtomicPairExchange) \ 366 V(ArmWord32AtomicPairCompareExchange) 367 368// Addressing modes represent the "shape" of inputs to an instruction. 369// Many instructions support multiple addressing modes. Addressing modes 370// are encoded into the InstructionCode of the instruction and tell the 371// code generator after register allocation which assembler method to call. 372#define TARGET_ADDRESSING_MODE_LIST(V) \ 373 V(Offset_RI) /* [%r0 + K] */ \ 374 V(Offset_RR) /* [%r0 + %r1] */ \ 375 V(Operand2_I) /* K */ \ 376 V(Operand2_R) /* %r0 */ \ 377 V(Operand2_R_ASR_I) /* %r0 ASR K */ \ 378 V(Operand2_R_LSL_I) /* %r0 LSL K */ \ 379 V(Operand2_R_LSR_I) /* %r0 LSR K */ \ 380 V(Operand2_R_ROR_I) /* %r0 ROR K */ \ 381 V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \ 382 V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \ 383 V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \ 384 V(Operand2_R_ROR_R) /* %r0 ROR %r1 */ \ 385 V(Root) /* [%rr + K] */ 386 387} // namespace compiler 388} // namespace internal 389} // namespace v8 390 391#endif // V8_COMPILER_BACKEND_ARM_INSTRUCTION_CODES_ARM_H_ 392