1// Copyright (c) 1994-2006 Sun Microsystems Inc. 2// All Rights Reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: 7// 8// - Redistributions of source code must retain the above copyright notice, 9// this list of conditions and the following disclaimer. 10// 11// - Redistribution in binary form must reproduce the above copyright 12// notice, this list of conditions and the following disclaimer in the 13// documentation and/or other materials provided with the distribution. 14// 15// - Neither the name of Sun Microsystems or the names of contributors may 16// be used to endorse or promote products derived from this software without 17// specific prior written permission. 18// 19// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 20// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 23// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 26// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 27// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 28// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 29// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 31// The original source code covered by the above license above has been 32// modified significantly by Google Inc. 33// Copyright 2012 the V8 project authors. All rights reserved. 34 35#ifndef V8_CODEGEN_MIPS_ASSEMBLER_MIPS_H_ 36#define V8_CODEGEN_MIPS_ASSEMBLER_MIPS_H_ 37 38#include <stdio.h> 39#include <memory> 40 41#include <set> 42 43#include "src/codegen/assembler.h" 44#include "src/codegen/external-reference.h" 45#include "src/codegen/label.h" 46#include "src/codegen/mips/constants-mips.h" 47#include "src/codegen/mips/register-mips.h" 48#include "src/objects/smi.h" 49 50namespace v8 { 51namespace internal { 52 53class SafepointTableBuilder; 54 55// Allow programmer to use Branch Delay Slot of Branches, Jumps, Calls. 56enum BranchDelaySlot { USE_DELAY_SLOT, PROTECT }; 57 58// ----------------------------------------------------------------------------- 59// Machine instruction Operands. 60 61// Class Operand represents a shifter operand in data processing instructions. 62class Operand { 63 public: 64 // Immediate. 65 V8_INLINE explicit Operand(int32_t immediate, 66 RelocInfo::Mode rmode = RelocInfo::NO_INFO) 67 : rm_(no_reg), rmode_(rmode) { 68 value_.immediate = immediate; 69 } 70 V8_INLINE explicit Operand(const ExternalReference& f) 71 : rm_(no_reg), rmode_(RelocInfo::EXTERNAL_REFERENCE) { 72 value_.immediate = static_cast<int32_t>(f.address()); 73 } 74 V8_INLINE explicit Operand(const char* s); 75 explicit Operand(Handle<HeapObject> handle); 76 V8_INLINE explicit Operand(Smi value) 77 : rm_(no_reg), rmode_(RelocInfo::NO_INFO) { 78 value_.immediate = static_cast<intptr_t>(value.ptr()); 79 } 80 81 static Operand EmbeddedNumber(double number); // Smi or HeapNumber. 82 static Operand EmbeddedStringConstant(const StringConstantBase* str); 83 84 // Register. 85 V8_INLINE explicit Operand(Register rm) : rm_(rm) {} 86 87 // Return true if this is a register operand. 88 V8_INLINE bool is_reg() const; 89 90 inline int32_t immediate() const; 91 92 bool IsImmediate() const { return !rm_.is_valid(); } 93 94 HeapObjectRequest heap_object_request() const { 95 DCHECK(IsHeapObjectRequest()); 96 return value_.heap_object_request; 97 } 98 99 bool IsHeapObjectRequest() const { 100 DCHECK_IMPLIES(is_heap_object_request_, IsImmediate()); 101 DCHECK_IMPLIES(is_heap_object_request_, 102 rmode_ == RelocInfo::FULL_EMBEDDED_OBJECT || 103 rmode_ == RelocInfo::CODE_TARGET); 104 return is_heap_object_request_; 105 } 106 107 Register rm() const { return rm_; } 108 109 RelocInfo::Mode rmode() const { return rmode_; } 110 111 private: 112 Register rm_; 113 union Value { 114 Value() {} 115 HeapObjectRequest heap_object_request; // if is_heap_object_request_ 116 int32_t immediate; // otherwise 117 } value_; // valid if rm_ == no_reg 118 bool is_heap_object_request_ = false; 119 RelocInfo::Mode rmode_; 120 121 friend class Assembler; 122 // friend class MacroAssembler; 123}; 124 125// On MIPS we have only one addressing mode with base_reg + offset. 126// Class MemOperand represents a memory operand in load and store instructions. 127class V8_EXPORT_PRIVATE MemOperand : public Operand { 128 public: 129 // Immediate value attached to offset. 130 enum OffsetAddend { offset_minus_one = -1, offset_zero = 0 }; 131 132 explicit MemOperand(Register rn, int32_t offset = 0); 133 explicit MemOperand(Register rn, int32_t unit, int32_t multiplier, 134 OffsetAddend offset_addend = offset_zero); 135 int32_t offset() const { return offset_; } 136 137 bool OffsetIsInt16Encodable() const { return is_int16(offset_); } 138 139 private: 140 int32_t offset_; 141 142 friend class Assembler; 143}; 144 145class V8_EXPORT_PRIVATE Assembler : public AssemblerBase { 146 public: 147 // Create an assembler. Instructions and relocation information are emitted 148 // into a buffer, with the instructions starting from the beginning and the 149 // relocation information starting from the end of the buffer. See CodeDesc 150 // for a detailed comment on the layout (globals.h). 151 // 152 // If the provided buffer is nullptr, the assembler allocates and grows its 153 // own buffer. Otherwise it takes ownership of the provided buffer. 154 explicit Assembler(const AssemblerOptions&, 155 std::unique_ptr<AssemblerBuffer> = {}); 156 157 virtual ~Assembler() {} 158 159 // GetCode emits any pending (non-emitted) code and fills the descriptor desc. 160 static constexpr int kNoHandlerTable = 0; 161 static constexpr SafepointTableBuilder* kNoSafepointTable = nullptr; 162 void GetCode(Isolate* isolate, CodeDesc* desc, 163 SafepointTableBuilder* safepoint_table_builder, 164 int handler_table_offset); 165 166 // Convenience wrapper for code without safepoint or handler tables. 167 void GetCode(Isolate* isolate, CodeDesc* desc) { 168 GetCode(isolate, desc, kNoSafepointTable, kNoHandlerTable); 169 } 170 171 // Unused on this architecture. 172 void MaybeEmitOutOfLineConstantPool() {} 173 174 // Mips uses BlockTrampolinePool to prevent generating trampoline inside a 175 // continuous instruction block. For Call instrution, it prevents generating 176 // trampoline between jalr and delay slot instruction. In the destructor of 177 // BlockTrampolinePool, it must check if it needs to generate trampoline 178 // immediately, if it does not do this, the branch range will go beyond the 179 // max branch offset, that means the pc_offset after call CheckTrampolinePool 180 // may have changed. So we use pc_for_safepoint_ here for safepoint record. 181 int pc_offset_for_safepoint() { 182 return static_cast<int>(pc_for_safepoint_ - buffer_start_); 183 } 184 185 // Label operations & relative jumps (PPUM Appendix D). 186 // 187 // Takes a branch opcode (cc) and a label (L) and generates 188 // either a backward branch or a forward branch and links it 189 // to the label fixup chain. Usage: 190 // 191 // Label L; // unbound label 192 // j(cc, &L); // forward branch to unbound label 193 // bind(&L); // bind label to the current pc 194 // j(cc, &L); // backward branch to bound label 195 // bind(&L); // illegal: a label may be bound only once 196 // 197 // Note: The same Label can be used for forward and backward branches 198 // but it may be bound only once. 199 void bind(Label* L); // Binds an unbound label L to current code position. 200 201 enum OffsetSize : int { kOffset26 = 26, kOffset21 = 21, kOffset16 = 16 }; 202 203 // Determines if Label is bound and near enough so that branch instruction 204 // can be used to reach it, instead of jump instruction. 205 bool is_near(Label* L); 206 bool is_near(Label* L, OffsetSize bits); 207 bool is_near_branch(Label* L); 208 inline bool is_near_pre_r6(Label* L) { 209 DCHECK(!IsMipsArchVariant(kMips32r6)); 210 return pc_offset() - L->pos() < kMaxBranchOffset - 4 * kInstrSize; 211 } 212 inline bool is_near_r6(Label* L) { 213 DCHECK(IsMipsArchVariant(kMips32r6)); 214 return pc_offset() - L->pos() < kMaxCompactBranchOffset - 4 * kInstrSize; 215 } 216 217 int BranchOffset(Instr instr); 218 219 // Returns the branch offset to the given label from the current code 220 // position. Links the label to the current position if it is still unbound. 221 // Manages the jump elimination optimization if the second parameter is true. 222 int32_t branch_offset_helper(Label* L, OffsetSize bits); 223 inline int32_t branch_offset(Label* L) { 224 return branch_offset_helper(L, OffsetSize::kOffset16); 225 } 226 inline int32_t branch_offset21(Label* L) { 227 return branch_offset_helper(L, OffsetSize::kOffset21); 228 } 229 inline int32_t branch_offset26(Label* L) { 230 return branch_offset_helper(L, OffsetSize::kOffset26); 231 } 232 inline int32_t shifted_branch_offset(Label* L) { 233 return branch_offset(L) >> 2; 234 } 235 inline int32_t shifted_branch_offset21(Label* L) { 236 return branch_offset21(L) >> 2; 237 } 238 inline int32_t shifted_branch_offset26(Label* L) { 239 return branch_offset26(L) >> 2; 240 } 241 uint32_t jump_address(Label* L); 242 uint32_t branch_long_offset(Label* L); 243 244 // Puts a labels target address at the given position. 245 // The high 8 bits are set to zero. 246 void label_at_put(Label* L, int at_offset); 247 248 // Read/Modify the code target address in the branch/call instruction at pc. 249 // The isolate argument is unused (and may be nullptr) when skipping flushing. 250 static Address target_address_at(Address pc); 251 V8_INLINE static void set_target_address_at( 252 Address pc, Address target, 253 ICacheFlushMode icache_flush_mode = FLUSH_ICACHE_IF_NEEDED) { 254 set_target_value_at(pc, static_cast<uint32_t>(target), icache_flush_mode); 255 } 256 // On MIPS there is no Constant Pool so we skip that parameter. 257 V8_INLINE static Address target_address_at(Address pc, 258 Address constant_pool) { 259 return target_address_at(pc); 260 } 261 V8_INLINE static void set_target_address_at( 262 Address pc, Address constant_pool, Address target, 263 ICacheFlushMode icache_flush_mode = FLUSH_ICACHE_IF_NEEDED) { 264 set_target_address_at(pc, target, icache_flush_mode); 265 } 266 267 static void set_target_value_at( 268 Address pc, uint32_t target, 269 ICacheFlushMode icache_flush_mode = FLUSH_ICACHE_IF_NEEDED); 270 271 // This sets the branch destination (which gets loaded at the call address). 272 // This is for calls and branches within generated code. The serializer 273 // has already deserialized the lui/ori instructions etc. 274 inline static void deserialization_set_special_target_at( 275 Address instruction_payload, Code code, Address target); 276 277 // Get the size of the special target encoded at 'instruction_payload'. 278 inline static int deserialization_special_target_size( 279 Address instruction_payload); 280 281 // This sets the internal reference at the pc. 282 inline static void deserialization_set_target_internal_reference_at( 283 Address pc, Address target, 284 RelocInfo::Mode mode = RelocInfo::INTERNAL_REFERENCE); 285 286 // Difference between address of current opcode and target address offset. 287 static constexpr int kBranchPCOffset = kInstrSize; 288 289 // Difference between address of current opcode and target address offset, 290 // when we are generatinga sequence of instructions for long relative PC 291 // branches. It is distance between address of the first instruction in 292 // the jump sequence, and the value that ra gets after calling nal(). 293 static constexpr int kLongBranchPCOffset = 3 * kInstrSize; 294 295 // Adjust ra register in branch delay slot of bal instruction in order to skip 296 // instructions not needed after optimization of PIC in 297 // TurboAssembler::BranchAndLink method. 298 static constexpr int kOptimizedBranchAndLinkLongReturnOffset = 3 * kInstrSize; 299 300 // Offset of target relative address in calls/jumps for builtins. It is 301 // distance between instruction that is placed just after calling 302 // RecordRelocInfo, and the value that ra gets aftr calling nal(). 303 static constexpr int kRelativeJumpForBuiltinsOffset = 1 * kInstrSize; 304 // Relative target address of jumps for builtins when we use lui, ori, dsll, 305 // ori sequence when loading address that cannot fit into 32 bits. 306 static constexpr int kRelativeCallForBuiltinsOffset = 3 * kInstrSize; 307 308 // Here we are patching the address in the LUI/ORI instruction pair. 309 // These values are used in the serialization process and must be zero for 310 // MIPS platform, as Code, Embedded Object or External-reference pointers 311 // are split across two consecutive instructions and don't exist separately 312 // in the code, so the serializer should not step forwards in memory after 313 // a target is resolved and written. 314 315 static constexpr int kSpecialTargetSize = 0; 316 317 // Number of consecutive instructions used to store 32bit constant. This 318 // constant is used in RelocInfo::target_address_address() function to tell 319 // serializer address of the instruction that follows LUI/ORI instruction 320 // pair. 321 static constexpr int kInstructionsFor32BitConstant = 2; 322 323 // Max offset for instructions with 16-bit offset field 324 static constexpr int kMaxBranchOffset = (1 << (18 - 1)) - 1; 325 326 // Max offset for compact branch instructions with 26-bit offset field 327 static constexpr int kMaxCompactBranchOffset = (1 << (28 - 1)) - 1; 328 329 static constexpr int kTrampolineSlotsSize = 330 IsMipsArchVariant(kMips32r6) ? 2 * kInstrSize : 7 * kInstrSize; 331 332 RegList* GetScratchRegisterList() { return &scratch_register_list_; } 333 334 // --------------------------------------------------------------------------- 335 // Code generation. 336 337 // Insert the smallest number of nop instructions 338 // possible to align the pc offset to a multiple 339 // of m. m must be a power of 2 (>= 4). 340 void Align(int m); 341 // Insert the smallest number of zero bytes possible to align the pc offset 342 // to a mulitple of m. m must be a power of 2 (>= 2). 343 void DataAlign(int m); 344 // Aligns code to something that's optimal for a jump target for the platform. 345 void CodeTargetAlign(); 346 void LoopHeaderAlign() { CodeTargetAlign(); } 347 348 // Different nop operations are used by the code generator to detect certain 349 // states of the generated code. 350 enum NopMarkerTypes { 351 NON_MARKING_NOP = 0, 352 DEBUG_BREAK_NOP, 353 // IC markers. 354 PROPERTY_ACCESS_INLINED, 355 PROPERTY_ACCESS_INLINED_CONTEXT, 356 PROPERTY_ACCESS_INLINED_CONTEXT_DONT_DELETE, 357 // Helper values. 358 LAST_CODE_MARKER, 359 FIRST_IC_MARKER = PROPERTY_ACCESS_INLINED, 360 }; 361 362 // Type == 0 is the default non-marking nop. For mips this is a 363 // sll(zero_reg, zero_reg, 0). We use rt_reg == at for non-zero 364 // marking, to avoid conflict with ssnop and ehb instructions. 365 void nop(unsigned int type = 0) { 366 DCHECK_LT(type, 32); 367 Register nop_rt_reg = (type == 0) ? zero_reg : at; 368 sll(zero_reg, nop_rt_reg, type, true); 369 } 370 371 // --------Branch-and-jump-instructions---------- 372 // We don't use likely variant of instructions. 373 void b(int16_t offset); 374 inline void b(Label* L) { b(shifted_branch_offset(L)); } 375 void bal(int16_t offset); 376 inline void bal(Label* L) { bal(shifted_branch_offset(L)); } 377 void bc(int32_t offset); 378 inline void bc(Label* L) { bc(shifted_branch_offset26(L)); } 379 void balc(int32_t offset); 380 inline void balc(Label* L) { balc(shifted_branch_offset26(L)); } 381 382 void beq(Register rs, Register rt, int16_t offset); 383 inline void beq(Register rs, Register rt, Label* L) { 384 beq(rs, rt, shifted_branch_offset(L)); 385 } 386 void bgez(Register rs, int16_t offset); 387 void bgezc(Register rt, int16_t offset); 388 inline void bgezc(Register rt, Label* L) { 389 bgezc(rt, shifted_branch_offset(L)); 390 } 391 void bgeuc(Register rs, Register rt, int16_t offset); 392 inline void bgeuc(Register rs, Register rt, Label* L) { 393 bgeuc(rs, rt, shifted_branch_offset(L)); 394 } 395 void bgec(Register rs, Register rt, int16_t offset); 396 inline void bgec(Register rs, Register rt, Label* L) { 397 bgec(rs, rt, shifted_branch_offset(L)); 398 } 399 void bgezal(Register rs, int16_t offset); 400 void bgezalc(Register rt, int16_t offset); 401 inline void bgezalc(Register rt, Label* L) { 402 bgezalc(rt, shifted_branch_offset(L)); 403 } 404 void bgezall(Register rs, int16_t offset); 405 inline void bgezall(Register rs, Label* L) { 406 bgezall(rs, branch_offset(L) >> 2); 407 } 408 void bgtz(Register rs, int16_t offset); 409 void bgtzc(Register rt, int16_t offset); 410 inline void bgtzc(Register rt, Label* L) { 411 bgtzc(rt, shifted_branch_offset(L)); 412 } 413 void blez(Register rs, int16_t offset); 414 void blezc(Register rt, int16_t offset); 415 inline void blezc(Register rt, Label* L) { 416 blezc(rt, shifted_branch_offset(L)); 417 } 418 void bltz(Register rs, int16_t offset); 419 void bltzc(Register rt, int16_t offset); 420 inline void bltzc(Register rt, Label* L) { 421 bltzc(rt, shifted_branch_offset(L)); 422 } 423 void bltuc(Register rs, Register rt, int16_t offset); 424 inline void bltuc(Register rs, Register rt, Label* L) { 425 bltuc(rs, rt, shifted_branch_offset(L)); 426 } 427 void bltc(Register rs, Register rt, int16_t offset); 428 inline void bltc(Register rs, Register rt, Label* L) { 429 bltc(rs, rt, shifted_branch_offset(L)); 430 } 431 void bltzal(Register rs, int16_t offset); 432 void nal() { bltzal(zero_reg, 0); } 433 void blezalc(Register rt, int16_t offset); 434 inline void blezalc(Register rt, Label* L) { 435 blezalc(rt, shifted_branch_offset(L)); 436 } 437 void bltzalc(Register rt, int16_t offset); 438 inline void bltzalc(Register rt, Label* L) { 439 bltzalc(rt, shifted_branch_offset(L)); 440 } 441 void bgtzalc(Register rt, int16_t offset); 442 inline void bgtzalc(Register rt, Label* L) { 443 bgtzalc(rt, shifted_branch_offset(L)); 444 } 445 void beqzalc(Register rt, int16_t offset); 446 inline void beqzalc(Register rt, Label* L) { 447 beqzalc(rt, shifted_branch_offset(L)); 448 } 449 void beqc(Register rs, Register rt, int16_t offset); 450 inline void beqc(Register rs, Register rt, Label* L) { 451 beqc(rs, rt, shifted_branch_offset(L)); 452 } 453 void beqzc(Register rs, int32_t offset); 454 inline void beqzc(Register rs, Label* L) { 455 beqzc(rs, shifted_branch_offset21(L)); 456 } 457 void bnezalc(Register rt, int16_t offset); 458 inline void bnezalc(Register rt, Label* L) { 459 bnezalc(rt, shifted_branch_offset(L)); 460 } 461 void bnec(Register rs, Register rt, int16_t offset); 462 inline void bnec(Register rs, Register rt, Label* L) { 463 bnec(rs, rt, shifted_branch_offset(L)); 464 } 465 void bnezc(Register rt, int32_t offset); 466 inline void bnezc(Register rt, Label* L) { 467 bnezc(rt, shifted_branch_offset21(L)); 468 } 469 void bne(Register rs, Register rt, int16_t offset); 470 inline void bne(Register rs, Register rt, Label* L) { 471 bne(rs, rt, shifted_branch_offset(L)); 472 } 473 void bovc(Register rs, Register rt, int16_t offset); 474 inline void bovc(Register rs, Register rt, Label* L) { 475 bovc(rs, rt, shifted_branch_offset(L)); 476 } 477 void bnvc(Register rs, Register rt, int16_t offset); 478 inline void bnvc(Register rs, Register rt, Label* L) { 479 bnvc(rs, rt, shifted_branch_offset(L)); 480 } 481 482 // Never use the int16_t b(l)cond version with a branch offset 483 // instead of using the Label* version. 484 485 // Jump targets must be in the current 256 MB-aligned region. i.e. 28 bits. 486 void j(int32_t target); 487 void jal(int32_t target); 488 void jalr(Register rs, Register rd = ra); 489 void jr(Register target); 490 void jic(Register rt, int16_t offset); 491 void jialc(Register rt, int16_t offset); 492 493 // -------Data-processing-instructions--------- 494 495 // Arithmetic. 496 void addu(Register rd, Register rs, Register rt); 497 void subu(Register rd, Register rs, Register rt); 498 void mult(Register rs, Register rt); 499 void multu(Register rs, Register rt); 500 void div(Register rs, Register rt); 501 void divu(Register rs, Register rt); 502 void div(Register rd, Register rs, Register rt); 503 void divu(Register rd, Register rs, Register rt); 504 void mod(Register rd, Register rs, Register rt); 505 void modu(Register rd, Register rs, Register rt); 506 void mul(Register rd, Register rs, Register rt); 507 void muh(Register rd, Register rs, Register rt); 508 void mulu(Register rd, Register rs, Register rt); 509 void muhu(Register rd, Register rs, Register rt); 510 511 void addiu(Register rd, Register rs, int32_t j); 512 513 // Logical. 514 void and_(Register rd, Register rs, Register rt); 515 void or_(Register rd, Register rs, Register rt); 516 void xor_(Register rd, Register rs, Register rt); 517 void nor(Register rd, Register rs, Register rt); 518 519 void andi(Register rd, Register rs, int32_t j); 520 void ori(Register rd, Register rs, int32_t j); 521 void xori(Register rd, Register rs, int32_t j); 522 void lui(Register rd, int32_t j); 523 void aui(Register rs, Register rt, int32_t j); 524 525 // Shifts. 526 // Please note: sll(zero_reg, zero_reg, x) instructions are reserved as nop 527 // and may cause problems in normal code. coming_from_nop makes sure this 528 // doesn't happen. 529 void sll(Register rd, Register rt, uint16_t sa, bool coming_from_nop = false); 530 void sllv(Register rd, Register rt, Register rs); 531 void srl(Register rd, Register rt, uint16_t sa); 532 void srlv(Register rd, Register rt, Register rs); 533 void sra(Register rt, Register rd, uint16_t sa); 534 void srav(Register rt, Register rd, Register rs); 535 void rotr(Register rd, Register rt, uint16_t sa); 536 void rotrv(Register rd, Register rt, Register rs); 537 538 // ------------Memory-instructions------------- 539 540 void lb(Register rd, const MemOperand& rs); 541 void lbu(Register rd, const MemOperand& rs); 542 void lh(Register rd, const MemOperand& rs); 543 void lhu(Register rd, const MemOperand& rs); 544 void lw(Register rd, const MemOperand& rs); 545 void lwl(Register rd, const MemOperand& rs); 546 void lwr(Register rd, const MemOperand& rs); 547 void sb(Register rd, const MemOperand& rs); 548 void sh(Register rd, const MemOperand& rs); 549 void sw(Register rd, const MemOperand& rs); 550 void swl(Register rd, const MemOperand& rs); 551 void swr(Register rd, const MemOperand& rs); 552 553 // ----------Atomic instructions-------------- 554 555 void ll(Register rd, const MemOperand& rs); 556 void sc(Register rd, const MemOperand& rs); 557 void llx(Register rd, const MemOperand& rs); 558 void scx(Register rd, const MemOperand& rs); 559 560 // ---------PC-Relative-instructions----------- 561 562 void addiupc(Register rs, int32_t imm19); 563 void lwpc(Register rs, int32_t offset19); 564 void auipc(Register rs, int16_t imm16); 565 void aluipc(Register rs, int16_t imm16); 566 567 // ----------------Prefetch-------------------- 568 569 void pref(int32_t hint, const MemOperand& rs); 570 571 // -------------Misc-instructions-------------- 572 573 // Break / Trap instructions. 574 void break_(uint32_t code, bool break_as_stop = false); 575 void stop(uint32_t code = kMaxStopCode); 576 void tge(Register rs, Register rt, uint16_t code); 577 void tgeu(Register rs, Register rt, uint16_t code); 578 void tlt(Register rs, Register rt, uint16_t code); 579 void tltu(Register rs, Register rt, uint16_t code); 580 void teq(Register rs, Register rt, uint16_t code); 581 void tne(Register rs, Register rt, uint16_t code); 582 583 // Memory barrier instruction. 584 void sync(); 585 586 // Move from HI/LO register. 587 void mfhi(Register rd); 588 void mflo(Register rd); 589 590 // Set on less than. 591 void slt(Register rd, Register rs, Register rt); 592 void sltu(Register rd, Register rs, Register rt); 593 void slti(Register rd, Register rs, int32_t j); 594 void sltiu(Register rd, Register rs, int32_t j); 595 596 // Conditional move. 597 void movz(Register rd, Register rs, Register rt); 598 void movn(Register rd, Register rs, Register rt); 599 void movt(Register rd, Register rs, uint16_t cc = 0); 600 void movf(Register rd, Register rs, uint16_t cc = 0); 601 602 void sel(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft); 603 void sel_s(FPURegister fd, FPURegister fs, FPURegister ft); 604 void sel_d(FPURegister fd, FPURegister fs, FPURegister ft); 605 void seleqz(Register rd, Register rs, Register rt); 606 void seleqz(SecondaryField fmt, FPURegister fd, FPURegister fs, 607 FPURegister ft); 608 void selnez(Register rd, Register rs, Register rt); 609 void selnez(SecondaryField fmt, FPURegister fd, FPURegister fs, 610 FPURegister ft); 611 void seleqz_d(FPURegister fd, FPURegister fs, FPURegister ft); 612 void seleqz_s(FPURegister fd, FPURegister fs, FPURegister ft); 613 void selnez_d(FPURegister fd, FPURegister fs, FPURegister ft); 614 void selnez_s(FPURegister fd, FPURegister fs, FPURegister ft); 615 616 void movz_s(FPURegister fd, FPURegister fs, Register rt); 617 void movz_d(FPURegister fd, FPURegister fs, Register rt); 618 void movt_s(FPURegister fd, FPURegister fs, uint16_t cc = 0); 619 void movt_d(FPURegister fd, FPURegister fs, uint16_t cc = 0); 620 void movf_s(FPURegister fd, FPURegister fs, uint16_t cc = 0); 621 void movf_d(FPURegister fd, FPURegister fs, uint16_t cc = 0); 622 void movn_s(FPURegister fd, FPURegister fs, Register rt); 623 void movn_d(FPURegister fd, FPURegister fs, Register rt); 624 // Bit twiddling. 625 void clz(Register rd, Register rs); 626 void ins_(Register rt, Register rs, uint16_t pos, uint16_t size); 627 void ext_(Register rt, Register rs, uint16_t pos, uint16_t size); 628 void bitswap(Register rd, Register rt); 629 void align(Register rd, Register rs, Register rt, uint8_t bp); 630 631 void wsbh(Register rd, Register rt); 632 void seh(Register rd, Register rt); 633 void seb(Register rd, Register rt); 634 635 // --------Coprocessor-instructions---------------- 636 637 // Load, store, and move. 638 void lwc1(FPURegister fd, const MemOperand& src); 639 void swc1(FPURegister fs, const MemOperand& dst); 640 641 void mtc1(Register rt, FPURegister fs); 642 void mthc1(Register rt, FPURegister fs); 643 644 void mfc1(Register rt, FPURegister fs); 645 void mfhc1(Register rt, FPURegister fs); 646 647 void ctc1(Register rt, FPUControlRegister fs); 648 void cfc1(Register rt, FPUControlRegister fs); 649 650 // Arithmetic. 651 void add_s(FPURegister fd, FPURegister fs, FPURegister ft); 652 void add_d(FPURegister fd, FPURegister fs, FPURegister ft); 653 void sub_s(FPURegister fd, FPURegister fs, FPURegister ft); 654 void sub_d(FPURegister fd, FPURegister fs, FPURegister ft); 655 void mul_s(FPURegister fd, FPURegister fs, FPURegister ft); 656 void mul_d(FPURegister fd, FPURegister fs, FPURegister ft); 657 void madd_s(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft); 658 void madd_d(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft); 659 void msub_s(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft); 660 void msub_d(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft); 661 void maddf_s(FPURegister fd, FPURegister fs, FPURegister ft); 662 void maddf_d(FPURegister fd, FPURegister fs, FPURegister ft); 663 void msubf_s(FPURegister fd, FPURegister fs, FPURegister ft); 664 void msubf_d(FPURegister fd, FPURegister fs, FPURegister ft); 665 void div_s(FPURegister fd, FPURegister fs, FPURegister ft); 666 void div_d(FPURegister fd, FPURegister fs, FPURegister ft); 667 void abs_s(FPURegister fd, FPURegister fs); 668 void abs_d(FPURegister fd, FPURegister fs); 669 void mov_d(FPURegister fd, FPURegister fs); 670 void mov_s(FPURegister fd, FPURegister fs); 671 void neg_s(FPURegister fd, FPURegister fs); 672 void neg_d(FPURegister fd, FPURegister fs); 673 void sqrt_s(FPURegister fd, FPURegister fs); 674 void sqrt_d(FPURegister fd, FPURegister fs); 675 void rsqrt_s(FPURegister fd, FPURegister fs); 676 void rsqrt_d(FPURegister fd, FPURegister fs); 677 void recip_d(FPURegister fd, FPURegister fs); 678 void recip_s(FPURegister fd, FPURegister fs); 679 680 // Conversion. 681 void cvt_w_s(FPURegister fd, FPURegister fs); 682 void cvt_w_d(FPURegister fd, FPURegister fs); 683 void trunc_w_s(FPURegister fd, FPURegister fs); 684 void trunc_w_d(FPURegister fd, FPURegister fs); 685 void round_w_s(FPURegister fd, FPURegister fs); 686 void round_w_d(FPURegister fd, FPURegister fs); 687 void floor_w_s(FPURegister fd, FPURegister fs); 688 void floor_w_d(FPURegister fd, FPURegister fs); 689 void ceil_w_s(FPURegister fd, FPURegister fs); 690 void ceil_w_d(FPURegister fd, FPURegister fs); 691 void rint_s(FPURegister fd, FPURegister fs); 692 void rint_d(FPURegister fd, FPURegister fs); 693 void rint(SecondaryField fmt, FPURegister fd, FPURegister fs); 694 695 void cvt_l_s(FPURegister fd, FPURegister fs); 696 void cvt_l_d(FPURegister fd, FPURegister fs); 697 void trunc_l_s(FPURegister fd, FPURegister fs); 698 void trunc_l_d(FPURegister fd, FPURegister fs); 699 void round_l_s(FPURegister fd, FPURegister fs); 700 void round_l_d(FPURegister fd, FPURegister fs); 701 void floor_l_s(FPURegister fd, FPURegister fs); 702 void floor_l_d(FPURegister fd, FPURegister fs); 703 void ceil_l_s(FPURegister fd, FPURegister fs); 704 void ceil_l_d(FPURegister fd, FPURegister fs); 705 706 void class_s(FPURegister fd, FPURegister fs); 707 void class_d(FPURegister fd, FPURegister fs); 708 709 void min(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft); 710 void mina(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft); 711 void max(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft); 712 void maxa(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft); 713 void min_s(FPURegister fd, FPURegister fs, FPURegister ft); 714 void min_d(FPURegister fd, FPURegister fs, FPURegister ft); 715 void max_s(FPURegister fd, FPURegister fs, FPURegister ft); 716 void max_d(FPURegister fd, FPURegister fs, FPURegister ft); 717 void mina_s(FPURegister fd, FPURegister fs, FPURegister ft); 718 void mina_d(FPURegister fd, FPURegister fs, FPURegister ft); 719 void maxa_s(FPURegister fd, FPURegister fs, FPURegister ft); 720 void maxa_d(FPURegister fd, FPURegister fs, FPURegister ft); 721 722 void cvt_s_w(FPURegister fd, FPURegister fs); 723 void cvt_s_l(FPURegister fd, FPURegister fs); 724 void cvt_s_d(FPURegister fd, FPURegister fs); 725 726 void cvt_d_w(FPURegister fd, FPURegister fs); 727 void cvt_d_l(FPURegister fd, FPURegister fs); 728 void cvt_d_s(FPURegister fd, FPURegister fs); 729 730 // Conditions and branches for MIPSr6. 731 void cmp(FPUCondition cond, SecondaryField fmt, FPURegister fd, 732 FPURegister ft, FPURegister fs); 733 void cmp_s(FPUCondition cond, FPURegister fd, FPURegister fs, FPURegister ft); 734 void cmp_d(FPUCondition cond, FPURegister fd, FPURegister fs, FPURegister ft); 735 736 void bc1eqz(int16_t offset, FPURegister ft); 737 inline void bc1eqz(Label* L, FPURegister ft) { 738 bc1eqz(shifted_branch_offset(L), ft); 739 } 740 void bc1nez(int16_t offset, FPURegister ft); 741 inline void bc1nez(Label* L, FPURegister ft) { 742 bc1nez(shifted_branch_offset(L), ft); 743 } 744 745 // Conditions and branches for non MIPSr6. 746 void c(FPUCondition cond, SecondaryField fmt, FPURegister ft, FPURegister fs, 747 uint16_t cc = 0); 748 void c_s(FPUCondition cond, FPURegister ft, FPURegister fs, uint16_t cc = 0); 749 void c_d(FPUCondition cond, FPURegister ft, FPURegister fs, uint16_t cc = 0); 750 751 void bc1f(int16_t offset, uint16_t cc = 0); 752 inline void bc1f(Label* L, uint16_t cc = 0) { 753 bc1f(shifted_branch_offset(L), cc); 754 } 755 void bc1t(int16_t offset, uint16_t cc = 0); 756 inline void bc1t(Label* L, uint16_t cc = 0) { 757 bc1t(shifted_branch_offset(L), cc); 758 } 759 void fcmp(FPURegister src1, const double src2, FPUCondition cond); 760 761 // MSA instructions 762 void bz_v(MSARegister wt, int16_t offset); 763 inline void bz_v(MSARegister wt, Label* L) { 764 bz_v(wt, shifted_branch_offset(L)); 765 } 766 void bz_b(MSARegister wt, int16_t offset); 767 inline void bz_b(MSARegister wt, Label* L) { 768 bz_b(wt, shifted_branch_offset(L)); 769 } 770 void bz_h(MSARegister wt, int16_t offset); 771 inline void bz_h(MSARegister wt, Label* L) { 772 bz_h(wt, shifted_branch_offset(L)); 773 } 774 void bz_w(MSARegister wt, int16_t offset); 775 inline void bz_w(MSARegister wt, Label* L) { 776 bz_w(wt, shifted_branch_offset(L)); 777 } 778 void bz_d(MSARegister wt, int16_t offset); 779 inline void bz_d(MSARegister wt, Label* L) { 780 bz_d(wt, shifted_branch_offset(L)); 781 } 782 void bnz_v(MSARegister wt, int16_t offset); 783 inline void bnz_v(MSARegister wt, Label* L) { 784 bnz_v(wt, shifted_branch_offset(L)); 785 } 786 void bnz_b(MSARegister wt, int16_t offset); 787 inline void bnz_b(MSARegister wt, Label* L) { 788 bnz_b(wt, shifted_branch_offset(L)); 789 } 790 void bnz_h(MSARegister wt, int16_t offset); 791 inline void bnz_h(MSARegister wt, Label* L) { 792 bnz_h(wt, shifted_branch_offset(L)); 793 } 794 void bnz_w(MSARegister wt, int16_t offset); 795 inline void bnz_w(MSARegister wt, Label* L) { 796 bnz_w(wt, shifted_branch_offset(L)); 797 } 798 void bnz_d(MSARegister wt, int16_t offset); 799 inline void bnz_d(MSARegister wt, Label* L) { 800 bnz_d(wt, shifted_branch_offset(L)); 801 } 802 803 void ld_b(MSARegister wd, const MemOperand& rs); 804 void ld_h(MSARegister wd, const MemOperand& rs); 805 void ld_w(MSARegister wd, const MemOperand& rs); 806 void ld_d(MSARegister wd, const MemOperand& rs); 807 void st_b(MSARegister wd, const MemOperand& rs); 808 void st_h(MSARegister wd, const MemOperand& rs); 809 void st_w(MSARegister wd, const MemOperand& rs); 810 void st_d(MSARegister wd, const MemOperand& rs); 811 812 void ldi_b(MSARegister wd, int32_t imm10); 813 void ldi_h(MSARegister wd, int32_t imm10); 814 void ldi_w(MSARegister wd, int32_t imm10); 815 void ldi_d(MSARegister wd, int32_t imm10); 816 817 void addvi_b(MSARegister wd, MSARegister ws, uint32_t imm5); 818 void addvi_h(MSARegister wd, MSARegister ws, uint32_t imm5); 819 void addvi_w(MSARegister wd, MSARegister ws, uint32_t imm5); 820 void addvi_d(MSARegister wd, MSARegister ws, uint32_t imm5); 821 void subvi_b(MSARegister wd, MSARegister ws, uint32_t imm5); 822 void subvi_h(MSARegister wd, MSARegister ws, uint32_t imm5); 823 void subvi_w(MSARegister wd, MSARegister ws, uint32_t imm5); 824 void subvi_d(MSARegister wd, MSARegister ws, uint32_t imm5); 825 void maxi_s_b(MSARegister wd, MSARegister ws, uint32_t imm5); 826 void maxi_s_h(MSARegister wd, MSARegister ws, uint32_t imm5); 827 void maxi_s_w(MSARegister wd, MSARegister ws, uint32_t imm5); 828 void maxi_s_d(MSARegister wd, MSARegister ws, uint32_t imm5); 829 void maxi_u_b(MSARegister wd, MSARegister ws, uint32_t imm5); 830 void maxi_u_h(MSARegister wd, MSARegister ws, uint32_t imm5); 831 void maxi_u_w(MSARegister wd, MSARegister ws, uint32_t imm5); 832 void maxi_u_d(MSARegister wd, MSARegister ws, uint32_t imm5); 833 void mini_s_b(MSARegister wd, MSARegister ws, uint32_t imm5); 834 void mini_s_h(MSARegister wd, MSARegister ws, uint32_t imm5); 835 void mini_s_w(MSARegister wd, MSARegister ws, uint32_t imm5); 836 void mini_s_d(MSARegister wd, MSARegister ws, uint32_t imm5); 837 void mini_u_b(MSARegister wd, MSARegister ws, uint32_t imm5); 838 void mini_u_h(MSARegister wd, MSARegister ws, uint32_t imm5); 839 void mini_u_w(MSARegister wd, MSARegister ws, uint32_t imm5); 840 void mini_u_d(MSARegister wd, MSARegister ws, uint32_t imm5); 841 void ceqi_b(MSARegister wd, MSARegister ws, uint32_t imm5); 842 void ceqi_h(MSARegister wd, MSARegister ws, uint32_t imm5); 843 void ceqi_w(MSARegister wd, MSARegister ws, uint32_t imm5); 844 void ceqi_d(MSARegister wd, MSARegister ws, uint32_t imm5); 845 void clti_s_b(MSARegister wd, MSARegister ws, uint32_t imm5); 846 void clti_s_h(MSARegister wd, MSARegister ws, uint32_t imm5); 847 void clti_s_w(MSARegister wd, MSARegister ws, uint32_t imm5); 848 void clti_s_d(MSARegister wd, MSARegister ws, uint32_t imm5); 849 void clti_u_b(MSARegister wd, MSARegister ws, uint32_t imm5); 850 void clti_u_h(MSARegister wd, MSARegister ws, uint32_t imm5); 851 void clti_u_w(MSARegister wd, MSARegister ws, uint32_t imm5); 852 void clti_u_d(MSARegister wd, MSARegister ws, uint32_t imm5); 853 void clei_s_b(MSARegister wd, MSARegister ws, uint32_t imm5); 854 void clei_s_h(MSARegister wd, MSARegister ws, uint32_t imm5); 855 void clei_s_w(MSARegister wd, MSARegister ws, uint32_t imm5); 856 void clei_s_d(MSARegister wd, MSARegister ws, uint32_t imm5); 857 void clei_u_b(MSARegister wd, MSARegister ws, uint32_t imm5); 858 void clei_u_h(MSARegister wd, MSARegister ws, uint32_t imm5); 859 void clei_u_w(MSARegister wd, MSARegister ws, uint32_t imm5); 860 void clei_u_d(MSARegister wd, MSARegister ws, uint32_t imm5); 861 862 void andi_b(MSARegister wd, MSARegister ws, uint32_t imm8); 863 void ori_b(MSARegister wd, MSARegister ws, uint32_t imm8); 864 void nori_b(MSARegister wd, MSARegister ws, uint32_t imm8); 865 void xori_b(MSARegister wd, MSARegister ws, uint32_t imm8); 866 void bmnzi_b(MSARegister wd, MSARegister ws, uint32_t imm8); 867 void bmzi_b(MSARegister wd, MSARegister ws, uint32_t imm8); 868 void bseli_b(MSARegister wd, MSARegister ws, uint32_t imm8); 869 void shf_b(MSARegister wd, MSARegister ws, uint32_t imm8); 870 void shf_h(MSARegister wd, MSARegister ws, uint32_t imm8); 871 void shf_w(MSARegister wd, MSARegister ws, uint32_t imm8); 872 873 void and_v(MSARegister wd, MSARegister ws, MSARegister wt); 874 void or_v(MSARegister wd, MSARegister ws, MSARegister wt); 875 void nor_v(MSARegister wd, MSARegister ws, MSARegister wt); 876 void xor_v(MSARegister wd, MSARegister ws, MSARegister wt); 877 void bmnz_v(MSARegister wd, MSARegister ws, MSARegister wt); 878 void bmz_v(MSARegister wd, MSARegister ws, MSARegister wt); 879 void bsel_v(MSARegister wd, MSARegister ws, MSARegister wt); 880 881 void fill_b(MSARegister wd, Register rs); 882 void fill_h(MSARegister wd, Register rs); 883 void fill_w(MSARegister wd, Register rs); 884 void pcnt_b(MSARegister wd, MSARegister ws); 885 void pcnt_h(MSARegister wd, MSARegister ws); 886 void pcnt_w(MSARegister wd, MSARegister ws); 887 void pcnt_d(MSARegister wd, MSARegister ws); 888 void nloc_b(MSARegister wd, MSARegister ws); 889 void nloc_h(MSARegister wd, MSARegister ws); 890 void nloc_w(MSARegister wd, MSARegister ws); 891 void nloc_d(MSARegister wd, MSARegister ws); 892 void nlzc_b(MSARegister wd, MSARegister ws); 893 void nlzc_h(MSARegister wd, MSARegister ws); 894 void nlzc_w(MSARegister wd, MSARegister ws); 895 void nlzc_d(MSARegister wd, MSARegister ws); 896 897 void fclass_w(MSARegister wd, MSARegister ws); 898 void fclass_d(MSARegister wd, MSARegister ws); 899 void ftrunc_s_w(MSARegister wd, MSARegister ws); 900 void ftrunc_s_d(MSARegister wd, MSARegister ws); 901 void ftrunc_u_w(MSARegister wd, MSARegister ws); 902 void ftrunc_u_d(MSARegister wd, MSARegister ws); 903 void fsqrt_w(MSARegister wd, MSARegister ws); 904 void fsqrt_d(MSARegister wd, MSARegister ws); 905 void frsqrt_w(MSARegister wd, MSARegister ws); 906 void frsqrt_d(MSARegister wd, MSARegister ws); 907 void frcp_w(MSARegister wd, MSARegister ws); 908 void frcp_d(MSARegister wd, MSARegister ws); 909 void frint_w(MSARegister wd, MSARegister ws); 910 void frint_d(MSARegister wd, MSARegister ws); 911 void flog2_w(MSARegister wd, MSARegister ws); 912 void flog2_d(MSARegister wd, MSARegister ws); 913 void fexupl_w(MSARegister wd, MSARegister ws); 914 void fexupl_d(MSARegister wd, MSARegister ws); 915 void fexupr_w(MSARegister wd, MSARegister ws); 916 void fexupr_d(MSARegister wd, MSARegister ws); 917 void ffql_w(MSARegister wd, MSARegister ws); 918 void ffql_d(MSARegister wd, MSARegister ws); 919 void ffqr_w(MSARegister wd, MSARegister ws); 920 void ffqr_d(MSARegister wd, MSARegister ws); 921 void ftint_s_w(MSARegister wd, MSARegister ws); 922 void ftint_s_d(MSARegister wd, MSARegister ws); 923 void ftint_u_w(MSARegister wd, MSARegister ws); 924 void ftint_u_d(MSARegister wd, MSARegister ws); 925 void ffint_s_w(MSARegister wd, MSARegister ws); 926 void ffint_s_d(MSARegister wd, MSARegister ws); 927 void ffint_u_w(MSARegister wd, MSARegister ws); 928 void ffint_u_d(MSARegister wd, MSARegister ws); 929 930 void sll_b(MSARegister wd, MSARegister ws, MSARegister wt); 931 void sll_h(MSARegister wd, MSARegister ws, MSARegister wt); 932 void sll_w(MSARegister wd, MSARegister ws, MSARegister wt); 933 void sll_d(MSARegister wd, MSARegister ws, MSARegister wt); 934 void sra_b(MSARegister wd, MSARegister ws, MSARegister wt); 935 void sra_h(MSARegister wd, MSARegister ws, MSARegister wt); 936 void sra_w(MSARegister wd, MSARegister ws, MSARegister wt); 937 void sra_d(MSARegister wd, MSARegister ws, MSARegister wt); 938 void srl_b(MSARegister wd, MSARegister ws, MSARegister wt); 939 void srl_h(MSARegister wd, MSARegister ws, MSARegister wt); 940 void srl_w(MSARegister wd, MSARegister ws, MSARegister wt); 941 void srl_d(MSARegister wd, MSARegister ws, MSARegister wt); 942 void bclr_b(MSARegister wd, MSARegister ws, MSARegister wt); 943 void bclr_h(MSARegister wd, MSARegister ws, MSARegister wt); 944 void bclr_w(MSARegister wd, MSARegister ws, MSARegister wt); 945 void bclr_d(MSARegister wd, MSARegister ws, MSARegister wt); 946 void bset_b(MSARegister wd, MSARegister ws, MSARegister wt); 947 void bset_h(MSARegister wd, MSARegister ws, MSARegister wt); 948 void bset_w(MSARegister wd, MSARegister ws, MSARegister wt); 949 void bset_d(MSARegister wd, MSARegister ws, MSARegister wt); 950 void bneg_b(MSARegister wd, MSARegister ws, MSARegister wt); 951 void bneg_h(MSARegister wd, MSARegister ws, MSARegister wt); 952 void bneg_w(MSARegister wd, MSARegister ws, MSARegister wt); 953 void bneg_d(MSARegister wd, MSARegister ws, MSARegister wt); 954 void binsl_b(MSARegister wd, MSARegister ws, MSARegister wt); 955 void binsl_h(MSARegister wd, MSARegister ws, MSARegister wt); 956 void binsl_w(MSARegister wd, MSARegister ws, MSARegister wt); 957 void binsl_d(MSARegister wd, MSARegister ws, MSARegister wt); 958 void binsr_b(MSARegister wd, MSARegister ws, MSARegister wt); 959 void binsr_h(MSARegister wd, MSARegister ws, MSARegister wt); 960 void binsr_w(MSARegister wd, MSARegister ws, MSARegister wt); 961 void binsr_d(MSARegister wd, MSARegister ws, MSARegister wt); 962 void addv_b(MSARegister wd, MSARegister ws, MSARegister wt); 963 void addv_h(MSARegister wd, MSARegister ws, MSARegister wt); 964 void addv_w(MSARegister wd, MSARegister ws, MSARegister wt); 965 void addv_d(MSARegister wd, MSARegister ws, MSARegister wt); 966 void subv_b(MSARegister wd, MSARegister ws, MSARegister wt); 967 void subv_h(MSARegister wd, MSARegister ws, MSARegister wt); 968 void subv_w(MSARegister wd, MSARegister ws, MSARegister wt); 969 void subv_d(MSARegister wd, MSARegister ws, MSARegister wt); 970 void max_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 971 void max_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 972 void max_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 973 void max_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 974 void max_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 975 void max_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 976 void max_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 977 void max_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 978 void min_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 979 void min_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 980 void min_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 981 void min_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 982 void min_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 983 void min_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 984 void min_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 985 void min_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 986 void max_a_b(MSARegister wd, MSARegister ws, MSARegister wt); 987 void max_a_h(MSARegister wd, MSARegister ws, MSARegister wt); 988 void max_a_w(MSARegister wd, MSARegister ws, MSARegister wt); 989 void max_a_d(MSARegister wd, MSARegister ws, MSARegister wt); 990 void min_a_b(MSARegister wd, MSARegister ws, MSARegister wt); 991 void min_a_h(MSARegister wd, MSARegister ws, MSARegister wt); 992 void min_a_w(MSARegister wd, MSARegister ws, MSARegister wt); 993 void min_a_d(MSARegister wd, MSARegister ws, MSARegister wt); 994 void ceq_b(MSARegister wd, MSARegister ws, MSARegister wt); 995 void ceq_h(MSARegister wd, MSARegister ws, MSARegister wt); 996 void ceq_w(MSARegister wd, MSARegister ws, MSARegister wt); 997 void ceq_d(MSARegister wd, MSARegister ws, MSARegister wt); 998 void clt_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 999 void clt_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1000 void clt_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1001 void clt_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1002 void clt_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1003 void clt_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1004 void clt_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1005 void clt_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1006 void cle_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1007 void cle_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1008 void cle_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1009 void cle_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1010 void cle_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1011 void cle_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1012 void cle_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1013 void cle_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1014 void add_a_b(MSARegister wd, MSARegister ws, MSARegister wt); 1015 void add_a_h(MSARegister wd, MSARegister ws, MSARegister wt); 1016 void add_a_w(MSARegister wd, MSARegister ws, MSARegister wt); 1017 void add_a_d(MSARegister wd, MSARegister ws, MSARegister wt); 1018 void adds_a_b(MSARegister wd, MSARegister ws, MSARegister wt); 1019 void adds_a_h(MSARegister wd, MSARegister ws, MSARegister wt); 1020 void adds_a_w(MSARegister wd, MSARegister ws, MSARegister wt); 1021 void adds_a_d(MSARegister wd, MSARegister ws, MSARegister wt); 1022 void adds_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1023 void adds_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1024 void adds_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1025 void adds_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1026 void adds_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1027 void adds_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1028 void adds_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1029 void adds_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1030 void ave_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1031 void ave_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1032 void ave_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1033 void ave_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1034 void ave_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1035 void ave_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1036 void ave_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1037 void ave_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1038 void aver_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1039 void aver_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1040 void aver_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1041 void aver_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1042 void aver_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1043 void aver_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1044 void aver_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1045 void aver_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1046 void subs_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1047 void subs_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1048 void subs_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1049 void subs_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1050 void subs_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1051 void subs_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1052 void subs_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1053 void subs_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1054 void subsus_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1055 void subsus_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1056 void subsus_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1057 void subsus_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1058 void subsus_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1059 void subsus_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1060 void subsus_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1061 void subsus_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1062 void subsuu_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1063 void subsuu_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1064 void subsuu_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1065 void subsuu_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1066 void subsuu_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1067 void subsuu_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1068 void subsuu_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1069 void subsuu_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1070 void asub_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1071 void asub_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1072 void asub_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1073 void asub_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1074 void asub_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1075 void asub_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1076 void asub_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1077 void asub_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1078 void mulv_b(MSARegister wd, MSARegister ws, MSARegister wt); 1079 void mulv_h(MSARegister wd, MSARegister ws, MSARegister wt); 1080 void mulv_w(MSARegister wd, MSARegister ws, MSARegister wt); 1081 void mulv_d(MSARegister wd, MSARegister ws, MSARegister wt); 1082 void maddv_b(MSARegister wd, MSARegister ws, MSARegister wt); 1083 void maddv_h(MSARegister wd, MSARegister ws, MSARegister wt); 1084 void maddv_w(MSARegister wd, MSARegister ws, MSARegister wt); 1085 void maddv_d(MSARegister wd, MSARegister ws, MSARegister wt); 1086 void msubv_b(MSARegister wd, MSARegister ws, MSARegister wt); 1087 void msubv_h(MSARegister wd, MSARegister ws, MSARegister wt); 1088 void msubv_w(MSARegister wd, MSARegister ws, MSARegister wt); 1089 void msubv_d(MSARegister wd, MSARegister ws, MSARegister wt); 1090 void div_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1091 void div_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1092 void div_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1093 void div_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1094 void div_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1095 void div_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1096 void div_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1097 void div_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1098 void mod_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1099 void mod_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1100 void mod_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1101 void mod_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1102 void mod_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1103 void mod_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1104 void mod_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1105 void mod_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1106 void dotp_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1107 void dotp_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1108 void dotp_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1109 void dotp_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1110 void dotp_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1111 void dotp_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1112 void dotp_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1113 void dotp_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1114 void dpadd_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1115 void dpadd_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1116 void dpadd_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1117 void dpadd_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1118 void dpadd_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1119 void dpadd_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1120 void dpadd_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1121 void dpadd_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1122 void dpsub_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1123 void dpsub_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1124 void dpsub_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1125 void dpsub_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1126 void dpsub_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1127 void dpsub_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1128 void dpsub_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1129 void dpsub_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1130 void sld_b(MSARegister wd, MSARegister ws, Register rt); 1131 void sld_h(MSARegister wd, MSARegister ws, Register rt); 1132 void sld_w(MSARegister wd, MSARegister ws, Register rt); 1133 void sld_d(MSARegister wd, MSARegister ws, Register rt); 1134 void splat_b(MSARegister wd, MSARegister ws, Register rt); 1135 void splat_h(MSARegister wd, MSARegister ws, Register rt); 1136 void splat_w(MSARegister wd, MSARegister ws, Register rt); 1137 void splat_d(MSARegister wd, MSARegister ws, Register rt); 1138 void pckev_b(MSARegister wd, MSARegister ws, MSARegister wt); 1139 void pckev_h(MSARegister wd, MSARegister ws, MSARegister wt); 1140 void pckev_w(MSARegister wd, MSARegister ws, MSARegister wt); 1141 void pckev_d(MSARegister wd, MSARegister ws, MSARegister wt); 1142 void pckod_b(MSARegister wd, MSARegister ws, MSARegister wt); 1143 void pckod_h(MSARegister wd, MSARegister ws, MSARegister wt); 1144 void pckod_w(MSARegister wd, MSARegister ws, MSARegister wt); 1145 void pckod_d(MSARegister wd, MSARegister ws, MSARegister wt); 1146 void ilvl_b(MSARegister wd, MSARegister ws, MSARegister wt); 1147 void ilvl_h(MSARegister wd, MSARegister ws, MSARegister wt); 1148 void ilvl_w(MSARegister wd, MSARegister ws, MSARegister wt); 1149 void ilvl_d(MSARegister wd, MSARegister ws, MSARegister wt); 1150 void ilvr_b(MSARegister wd, MSARegister ws, MSARegister wt); 1151 void ilvr_h(MSARegister wd, MSARegister ws, MSARegister wt); 1152 void ilvr_w(MSARegister wd, MSARegister ws, MSARegister wt); 1153 void ilvr_d(MSARegister wd, MSARegister ws, MSARegister wt); 1154 void ilvev_b(MSARegister wd, MSARegister ws, MSARegister wt); 1155 void ilvev_h(MSARegister wd, MSARegister ws, MSARegister wt); 1156 void ilvev_w(MSARegister wd, MSARegister ws, MSARegister wt); 1157 void ilvev_d(MSARegister wd, MSARegister ws, MSARegister wt); 1158 void ilvod_b(MSARegister wd, MSARegister ws, MSARegister wt); 1159 void ilvod_h(MSARegister wd, MSARegister ws, MSARegister wt); 1160 void ilvod_w(MSARegister wd, MSARegister ws, MSARegister wt); 1161 void ilvod_d(MSARegister wd, MSARegister ws, MSARegister wt); 1162 void vshf_b(MSARegister wd, MSARegister ws, MSARegister wt); 1163 void vshf_h(MSARegister wd, MSARegister ws, MSARegister wt); 1164 void vshf_w(MSARegister wd, MSARegister ws, MSARegister wt); 1165 void vshf_d(MSARegister wd, MSARegister ws, MSARegister wt); 1166 void srar_b(MSARegister wd, MSARegister ws, MSARegister wt); 1167 void srar_h(MSARegister wd, MSARegister ws, MSARegister wt); 1168 void srar_w(MSARegister wd, MSARegister ws, MSARegister wt); 1169 void srar_d(MSARegister wd, MSARegister ws, MSARegister wt); 1170 void srlr_b(MSARegister wd, MSARegister ws, MSARegister wt); 1171 void srlr_h(MSARegister wd, MSARegister ws, MSARegister wt); 1172 void srlr_w(MSARegister wd, MSARegister ws, MSARegister wt); 1173 void srlr_d(MSARegister wd, MSARegister ws, MSARegister wt); 1174 void hadd_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1175 void hadd_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1176 void hadd_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1177 void hadd_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1178 void hadd_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1179 void hadd_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1180 void hadd_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1181 void hadd_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1182 void hsub_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1183 void hsub_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1184 void hsub_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1185 void hsub_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1186 void hsub_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1187 void hsub_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1188 void hsub_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1189 void hsub_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1190 1191 void fcaf_w(MSARegister wd, MSARegister ws, MSARegister wt); 1192 void fcaf_d(MSARegister wd, MSARegister ws, MSARegister wt); 1193 void fcun_w(MSARegister wd, MSARegister ws, MSARegister wt); 1194 void fcun_d(MSARegister wd, MSARegister ws, MSARegister wt); 1195 void fceq_w(MSARegister wd, MSARegister ws, MSARegister wt); 1196 void fceq_d(MSARegister wd, MSARegister ws, MSARegister wt); 1197 void fcueq_w(MSARegister wd, MSARegister ws, MSARegister wt); 1198 void fcueq_d(MSARegister wd, MSARegister ws, MSARegister wt); 1199 void fclt_w(MSARegister wd, MSARegister ws, MSARegister wt); 1200 void fclt_d(MSARegister wd, MSARegister ws, MSARegister wt); 1201 void fcult_w(MSARegister wd, MSARegister ws, MSARegister wt); 1202 void fcult_d(MSARegister wd, MSARegister ws, MSARegister wt); 1203 void fcle_w(MSARegister wd, MSARegister ws, MSARegister wt); 1204 void fcle_d(MSARegister wd, MSARegister ws, MSARegister wt); 1205 void fcule_w(MSARegister wd, MSARegister ws, MSARegister wt); 1206 void fcule_d(MSARegister wd, MSARegister ws, MSARegister wt); 1207 void fsaf_w(MSARegister wd, MSARegister ws, MSARegister wt); 1208 void fsaf_d(MSARegister wd, MSARegister ws, MSARegister wt); 1209 void fsun_w(MSARegister wd, MSARegister ws, MSARegister wt); 1210 void fsun_d(MSARegister wd, MSARegister ws, MSARegister wt); 1211 void fseq_w(MSARegister wd, MSARegister ws, MSARegister wt); 1212 void fseq_d(MSARegister wd, MSARegister ws, MSARegister wt); 1213 void fsueq_w(MSARegister wd, MSARegister ws, MSARegister wt); 1214 void fsueq_d(MSARegister wd, MSARegister ws, MSARegister wt); 1215 void fslt_w(MSARegister wd, MSARegister ws, MSARegister wt); 1216 void fslt_d(MSARegister wd, MSARegister ws, MSARegister wt); 1217 void fsult_w(MSARegister wd, MSARegister ws, MSARegister wt); 1218 void fsult_d(MSARegister wd, MSARegister ws, MSARegister wt); 1219 void fsle_w(MSARegister wd, MSARegister ws, MSARegister wt); 1220 void fsle_d(MSARegister wd, MSARegister ws, MSARegister wt); 1221 void fsule_w(MSARegister wd, MSARegister ws, MSARegister wt); 1222 void fsule_d(MSARegister wd, MSARegister ws, MSARegister wt); 1223 void fadd_w(MSARegister wd, MSARegister ws, MSARegister wt); 1224 void fadd_d(MSARegister wd, MSARegister ws, MSARegister wt); 1225 void fsub_w(MSARegister wd, MSARegister ws, MSARegister wt); 1226 void fsub_d(MSARegister wd, MSARegister ws, MSARegister wt); 1227 void fmul_w(MSARegister wd, MSARegister ws, MSARegister wt); 1228 void fmul_d(MSARegister wd, MSARegister ws, MSARegister wt); 1229 void fdiv_w(MSARegister wd, MSARegister ws, MSARegister wt); 1230 void fdiv_d(MSARegister wd, MSARegister ws, MSARegister wt); 1231 void fmadd_w(MSARegister wd, MSARegister ws, MSARegister wt); 1232 void fmadd_d(MSARegister wd, MSARegister ws, MSARegister wt); 1233 void fmsub_w(MSARegister wd, MSARegister ws, MSARegister wt); 1234 void fmsub_d(MSARegister wd, MSARegister ws, MSARegister wt); 1235 void fexp2_w(MSARegister wd, MSARegister ws, MSARegister wt); 1236 void fexp2_d(MSARegister wd, MSARegister ws, MSARegister wt); 1237 void fexdo_h(MSARegister wd, MSARegister ws, MSARegister wt); 1238 void fexdo_w(MSARegister wd, MSARegister ws, MSARegister wt); 1239 void ftq_h(MSARegister wd, MSARegister ws, MSARegister wt); 1240 void ftq_w(MSARegister wd, MSARegister ws, MSARegister wt); 1241 void fmin_w(MSARegister wd, MSARegister ws, MSARegister wt); 1242 void fmin_d(MSARegister wd, MSARegister ws, MSARegister wt); 1243 void fmin_a_w(MSARegister wd, MSARegister ws, MSARegister wt); 1244 void fmin_a_d(MSARegister wd, MSARegister ws, MSARegister wt); 1245 void fmax_w(MSARegister wd, MSARegister ws, MSARegister wt); 1246 void fmax_d(MSARegister wd, MSARegister ws, MSARegister wt); 1247 void fmax_a_w(MSARegister wd, MSARegister ws, MSARegister wt); 1248 void fmax_a_d(MSARegister wd, MSARegister ws, MSARegister wt); 1249 void fcor_w(MSARegister wd, MSARegister ws, MSARegister wt); 1250 void fcor_d(MSARegister wd, MSARegister ws, MSARegister wt); 1251 void fcune_w(MSARegister wd, MSARegister ws, MSARegister wt); 1252 void fcune_d(MSARegister wd, MSARegister ws, MSARegister wt); 1253 void fcne_w(MSARegister wd, MSARegister ws, MSARegister wt); 1254 void fcne_d(MSARegister wd, MSARegister ws, MSARegister wt); 1255 void mul_q_h(MSARegister wd, MSARegister ws, MSARegister wt); 1256 void mul_q_w(MSARegister wd, MSARegister ws, MSARegister wt); 1257 void madd_q_h(MSARegister wd, MSARegister ws, MSARegister wt); 1258 void madd_q_w(MSARegister wd, MSARegister ws, MSARegister wt); 1259 void msub_q_h(MSARegister wd, MSARegister ws, MSARegister wt); 1260 void msub_q_w(MSARegister wd, MSARegister ws, MSARegister wt); 1261 void fsor_w(MSARegister wd, MSARegister ws, MSARegister wt); 1262 void fsor_d(MSARegister wd, MSARegister ws, MSARegister wt); 1263 void fsune_w(MSARegister wd, MSARegister ws, MSARegister wt); 1264 void fsune_d(MSARegister wd, MSARegister ws, MSARegister wt); 1265 void fsne_w(MSARegister wd, MSARegister ws, MSARegister wt); 1266 void fsne_d(MSARegister wd, MSARegister ws, MSARegister wt); 1267 void mulr_q_h(MSARegister wd, MSARegister ws, MSARegister wt); 1268 void mulr_q_w(MSARegister wd, MSARegister ws, MSARegister wt); 1269 void maddr_q_h(MSARegister wd, MSARegister ws, MSARegister wt); 1270 void maddr_q_w(MSARegister wd, MSARegister ws, MSARegister wt); 1271 void msubr_q_h(MSARegister wd, MSARegister ws, MSARegister wt); 1272 void msubr_q_w(MSARegister wd, MSARegister ws, MSARegister wt); 1273 1274 void sldi_b(MSARegister wd, MSARegister ws, uint32_t n); 1275 void sldi_h(MSARegister wd, MSARegister ws, uint32_t n); 1276 void sldi_w(MSARegister wd, MSARegister ws, uint32_t n); 1277 void sldi_d(MSARegister wd, MSARegister ws, uint32_t n); 1278 void splati_b(MSARegister wd, MSARegister ws, uint32_t n); 1279 void splati_h(MSARegister wd, MSARegister ws, uint32_t n); 1280 void splati_w(MSARegister wd, MSARegister ws, uint32_t n); 1281 void splati_d(MSARegister wd, MSARegister ws, uint32_t n); 1282 void copy_s_b(Register rd, MSARegister ws, uint32_t n); 1283 void copy_s_h(Register rd, MSARegister ws, uint32_t n); 1284 void copy_s_w(Register rd, MSARegister ws, uint32_t n); 1285 void copy_u_b(Register rd, MSARegister ws, uint32_t n); 1286 void copy_u_h(Register rd, MSARegister ws, uint32_t n); 1287 void copy_u_w(Register rd, MSARegister ws, uint32_t n); 1288 void insert_b(MSARegister wd, uint32_t n, Register rs); 1289 void insert_h(MSARegister wd, uint32_t n, Register rs); 1290 void insert_w(MSARegister wd, uint32_t n, Register rs); 1291 void insve_b(MSARegister wd, uint32_t n, MSARegister ws); 1292 void insve_h(MSARegister wd, uint32_t n, MSARegister ws); 1293 void insve_w(MSARegister wd, uint32_t n, MSARegister ws); 1294 void insve_d(MSARegister wd, uint32_t n, MSARegister ws); 1295 void move_v(MSARegister wd, MSARegister ws); 1296 void ctcmsa(MSAControlRegister cd, Register rs); 1297 void cfcmsa(Register rd, MSAControlRegister cs); 1298 1299 void slli_b(MSARegister wd, MSARegister ws, uint32_t m); 1300 void slli_h(MSARegister wd, MSARegister ws, uint32_t m); 1301 void slli_w(MSARegister wd, MSARegister ws, uint32_t m); 1302 void slli_d(MSARegister wd, MSARegister ws, uint32_t m); 1303 void srai_b(MSARegister wd, MSARegister ws, uint32_t m); 1304 void srai_h(MSARegister wd, MSARegister ws, uint32_t m); 1305 void srai_w(MSARegister wd, MSARegister ws, uint32_t m); 1306 void srai_d(MSARegister wd, MSARegister ws, uint32_t m); 1307 void srli_b(MSARegister wd, MSARegister ws, uint32_t m); 1308 void srli_h(MSARegister wd, MSARegister ws, uint32_t m); 1309 void srli_w(MSARegister wd, MSARegister ws, uint32_t m); 1310 void srli_d(MSARegister wd, MSARegister ws, uint32_t m); 1311 void bclri_b(MSARegister wd, MSARegister ws, uint32_t m); 1312 void bclri_h(MSARegister wd, MSARegister ws, uint32_t m); 1313 void bclri_w(MSARegister wd, MSARegister ws, uint32_t m); 1314 void bclri_d(MSARegister wd, MSARegister ws, uint32_t m); 1315 void bseti_b(MSARegister wd, MSARegister ws, uint32_t m); 1316 void bseti_h(MSARegister wd, MSARegister ws, uint32_t m); 1317 void bseti_w(MSARegister wd, MSARegister ws, uint32_t m); 1318 void bseti_d(MSARegister wd, MSARegister ws, uint32_t m); 1319 void bnegi_b(MSARegister wd, MSARegister ws, uint32_t m); 1320 void bnegi_h(MSARegister wd, MSARegister ws, uint32_t m); 1321 void bnegi_w(MSARegister wd, MSARegister ws, uint32_t m); 1322 void bnegi_d(MSARegister wd, MSARegister ws, uint32_t m); 1323 void binsli_b(MSARegister wd, MSARegister ws, uint32_t m); 1324 void binsli_h(MSARegister wd, MSARegister ws, uint32_t m); 1325 void binsli_w(MSARegister wd, MSARegister ws, uint32_t m); 1326 void binsli_d(MSARegister wd, MSARegister ws, uint32_t m); 1327 void binsri_b(MSARegister wd, MSARegister ws, uint32_t m); 1328 void binsri_h(MSARegister wd, MSARegister ws, uint32_t m); 1329 void binsri_w(MSARegister wd, MSARegister ws, uint32_t m); 1330 void binsri_d(MSARegister wd, MSARegister ws, uint32_t m); 1331 void sat_s_b(MSARegister wd, MSARegister ws, uint32_t m); 1332 void sat_s_h(MSARegister wd, MSARegister ws, uint32_t m); 1333 void sat_s_w(MSARegister wd, MSARegister ws, uint32_t m); 1334 void sat_s_d(MSARegister wd, MSARegister ws, uint32_t m); 1335 void sat_u_b(MSARegister wd, MSARegister ws, uint32_t m); 1336 void sat_u_h(MSARegister wd, MSARegister ws, uint32_t m); 1337 void sat_u_w(MSARegister wd, MSARegister ws, uint32_t m); 1338 void sat_u_d(MSARegister wd, MSARegister ws, uint32_t m); 1339 void srari_b(MSARegister wd, MSARegister ws, uint32_t m); 1340 void srari_h(MSARegister wd, MSARegister ws, uint32_t m); 1341 void srari_w(MSARegister wd, MSARegister ws, uint32_t m); 1342 void srari_d(MSARegister wd, MSARegister ws, uint32_t m); 1343 void srlri_b(MSARegister wd, MSARegister ws, uint32_t m); 1344 void srlri_h(MSARegister wd, MSARegister ws, uint32_t m); 1345 void srlri_w(MSARegister wd, MSARegister ws, uint32_t m); 1346 void srlri_d(MSARegister wd, MSARegister ws, uint32_t m); 1347 1348 // Check the code size generated from label to here. 1349 int SizeOfCodeGeneratedSince(Label* label) { 1350 return pc_offset() - label->pos(); 1351 } 1352 1353 // Check the number of instructions generated from label to here. 1354 int InstructionsGeneratedSince(Label* label) { 1355 return SizeOfCodeGeneratedSince(label) / kInstrSize; 1356 } 1357 1358 // Class for scoping postponing the trampoline pool generation. 1359 class V8_NODISCARD BlockTrampolinePoolScope { 1360 public: 1361 explicit BlockTrampolinePoolScope(Assembler* assem) : assem_(assem) { 1362 assem_->StartBlockTrampolinePool(); 1363 } 1364 ~BlockTrampolinePoolScope() { assem_->EndBlockTrampolinePool(); } 1365 1366 private: 1367 Assembler* assem_; 1368 1369 DISALLOW_IMPLICIT_CONSTRUCTORS(BlockTrampolinePoolScope); 1370 }; 1371 1372 // Class for postponing the assembly buffer growth. Typically used for 1373 // sequences of instructions that must be emitted as a unit, before 1374 // buffer growth (and relocation) can occur. 1375 // This blocking scope is not nestable. 1376 class V8_NODISCARD BlockGrowBufferScope { 1377 public: 1378 explicit BlockGrowBufferScope(Assembler* assem) : assem_(assem) { 1379 assem_->StartBlockGrowBuffer(); 1380 } 1381 ~BlockGrowBufferScope() { assem_->EndBlockGrowBuffer(); } 1382 1383 private: 1384 Assembler* assem_; 1385 1386 DISALLOW_IMPLICIT_CONSTRUCTORS(BlockGrowBufferScope); 1387 }; 1388 1389 // Record a deoptimization reason that can be used by a log or cpu profiler. 1390 // Use --trace-deopt to enable. 1391 void RecordDeoptReason(DeoptimizeReason reason, uint32_t node_id, 1392 SourcePosition position, int id); 1393 1394 static int RelocateInternalReference(RelocInfo::Mode rmode, Address pc, 1395 intptr_t pc_delta); 1396 1397 static void RelocateRelativeReference(RelocInfo::Mode rmode, Address pc, 1398 intptr_t pc_delta); 1399 1400 // Writes a single byte or word of data in the code stream. Used for 1401 // inline tables, e.g., jump-tables. 1402 void db(uint8_t data); 1403 void dd(uint32_t data, RelocInfo::Mode rmode = RelocInfo::NO_INFO); 1404 void dq(uint64_t data, RelocInfo::Mode rmode = RelocInfo::NO_INFO); 1405 void dp(uintptr_t data, RelocInfo::Mode rmode = RelocInfo::NO_INFO) { 1406 dd(data, rmode); 1407 } 1408 void dd(Label* label); 1409 1410 // Postpone the generation of the trampoline pool for the specified number of 1411 // instructions. 1412 void BlockTrampolinePoolFor(int instructions); 1413 1414 // Check if there is less than kGap bytes available in the buffer. 1415 // If this is the case, we need to grow the buffer before emitting 1416 // an instruction or relocation information. 1417 inline bool overflow() const { return pc_ >= reloc_info_writer.pos() - kGap; } 1418 1419 // Get the number of bytes available in the buffer. 1420 inline int available_space() const { return reloc_info_writer.pos() - pc_; } 1421 1422 // Read/patch instructions. 1423 static Instr instr_at(Address pc) { return *reinterpret_cast<Instr*>(pc); } 1424 static void instr_at_put(Address pc, Instr instr) { 1425 *reinterpret_cast<Instr*>(pc) = instr; 1426 } 1427 Instr instr_at(int pos) { 1428 return *reinterpret_cast<Instr*>(buffer_start_ + pos); 1429 } 1430 void instr_at_put(int pos, Instr instr) { 1431 *reinterpret_cast<Instr*>(buffer_start_ + pos) = instr; 1432 } 1433 1434 // Check if an instruction is a branch of some kind. 1435 static bool IsBranch(Instr instr); 1436 static bool IsMsaBranch(Instr instr); 1437 static bool IsBc(Instr instr); 1438 static bool IsNal(Instr instr); 1439 static bool IsBzc(Instr instr); 1440 static bool IsBeq(Instr instr); 1441 static bool IsBne(Instr instr); 1442 static bool IsBeqzc(Instr instr); 1443 static bool IsBnezc(Instr instr); 1444 static bool IsBeqc(Instr instr); 1445 static bool IsBnec(Instr instr); 1446 static bool IsJicOrJialc(Instr instr); 1447 static bool IsMov(Instr instr, Register rd, Register rs); 1448 1449 static bool IsJump(Instr instr); 1450 static bool IsJ(Instr instr); 1451 static bool IsLui(Instr instr); 1452 static bool IsOri(Instr instr); 1453 static bool IsAddu(Instr instr, Register rd, Register rs, Register rt); 1454 1455 static bool IsJal(Instr instr); 1456 static bool IsJr(Instr instr); 1457 static bool IsJalr(Instr instr); 1458 1459 static bool IsNop(Instr instr, unsigned int type); 1460 static bool IsPop(Instr instr); 1461 static bool IsPush(Instr instr); 1462 static bool IsLwRegFpOffset(Instr instr); 1463 static bool IsSwRegFpOffset(Instr instr); 1464 static bool IsLwRegFpNegOffset(Instr instr); 1465 static bool IsSwRegFpNegOffset(Instr instr); 1466 1467 static Register GetRtReg(Instr instr); 1468 static Register GetRsReg(Instr instr); 1469 static Register GetRdReg(Instr instr); 1470 1471 static uint32_t GetRt(Instr instr); 1472 static uint32_t GetRtField(Instr instr); 1473 static uint32_t GetRs(Instr instr); 1474 static uint32_t GetRsField(Instr instr); 1475 static uint32_t GetRd(Instr instr); 1476 static uint32_t GetRdField(Instr instr); 1477 static uint32_t GetSa(Instr instr); 1478 static uint32_t GetSaField(Instr instr); 1479 static uint32_t GetOpcodeField(Instr instr); 1480 static uint32_t GetFunction(Instr instr); 1481 static uint32_t GetFunctionField(Instr instr); 1482 static uint32_t GetImmediate16(Instr instr); 1483 static uint32_t GetLabelConst(Instr instr); 1484 1485 static int32_t GetBranchOffset(Instr instr); 1486 static bool IsLw(Instr instr); 1487 static int16_t GetLwOffset(Instr instr); 1488 static int16_t GetJicOrJialcOffset(Instr instr); 1489 static int16_t GetLuiOffset(Instr instr); 1490 static Instr SetLwOffset(Instr instr, int16_t offset); 1491 1492 static bool IsSw(Instr instr); 1493 static Instr SetSwOffset(Instr instr, int16_t offset); 1494 static bool IsAddImmediate(Instr instr); 1495 static Instr SetAddImmediateOffset(Instr instr, int16_t offset); 1496 static uint32_t CreateTargetAddress(Instr instr_lui, Instr instr_jic); 1497 static void UnpackTargetAddress(uint32_t address, int16_t* lui_offset, 1498 int16_t* jic_offset); 1499 static void UnpackTargetAddressUnsigned(uint32_t address, 1500 uint32_t* lui_offset, 1501 uint32_t* jic_offset); 1502 1503 static bool IsAndImmediate(Instr instr); 1504 static bool IsEmittedConstant(Instr instr); 1505 1506 void CheckTrampolinePool(); 1507 1508 bool IsPrevInstrCompactBranch() { return prev_instr_compact_branch_; } 1509 static bool IsCompactBranchSupported() { 1510 return IsMipsArchVariant(kMips32r6); 1511 } 1512 1513 // Get the code target object for a pc-relative call or jump. 1514 V8_INLINE Handle<Code> relative_code_target_object_handle_at( 1515 Address pc_) const; 1516 1517 inline int UnboundLabelsCount() { return unbound_labels_count_; } 1518 1519 bool is_trampoline_emitted() const { return trampoline_emitted_; } 1520 1521 protected: 1522 // Load Scaled Address instruction. 1523 void lsa(Register rd, Register rt, Register rs, uint8_t sa); 1524 1525 // Readable constants for base and offset adjustment helper, these indicate if 1526 // aside from offset, another value like offset + 4 should fit into int16. 1527 enum class OffsetAccessType : bool { 1528 SINGLE_ACCESS = false, 1529 TWO_ACCESSES = true 1530 }; 1531 1532 // Helper function for memory load/store using base register and offset. 1533 void AdjustBaseAndOffset( 1534 MemOperand* src, 1535 OffsetAccessType access_type = OffsetAccessType::SINGLE_ACCESS, 1536 int second_access_add_to_offset = 4); 1537 1538 int32_t buffer_space() const { return reloc_info_writer.pos() - pc_; } 1539 1540 // Decode branch instruction at pos and return branch target pos. 1541 int target_at(int pos, bool is_internal); 1542 1543 // Patch branch instruction at pos to branch to given branch target pos. 1544 void target_at_put(int pos, int target_pos, bool is_internal); 1545 1546 // Say if we need to relocate with this mode. 1547 bool MustUseReg(RelocInfo::Mode rmode); 1548 1549 // Record reloc info for current pc_. 1550 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0); 1551 1552 // Read 32-bit immediate from lui, ori pair that is used to load immediate. 1553 static int32_t GetLuiOriImmediate(Instr instr1, Instr instr2); 1554 1555 // Block the emission of the trampoline pool before pc_offset. 1556 void BlockTrampolinePoolBefore(int pc_offset) { 1557 if (no_trampoline_pool_before_ < pc_offset) 1558 no_trampoline_pool_before_ = pc_offset; 1559 } 1560 1561 void StartBlockTrampolinePool() { trampoline_pool_blocked_nesting_++; } 1562 1563 void EndBlockTrampolinePool() { 1564 trampoline_pool_blocked_nesting_--; 1565 if (trampoline_pool_blocked_nesting_ == 0) { 1566 CheckTrampolinePoolQuick(1); 1567 } 1568 } 1569 1570 bool is_trampoline_pool_blocked() const { 1571 return trampoline_pool_blocked_nesting_ > 0; 1572 } 1573 1574 bool has_exception() const { return internal_trampoline_exception_; } 1575 1576 // Temporarily block automatic assembly buffer growth. 1577 void StartBlockGrowBuffer() { 1578 DCHECK(!block_buffer_growth_); 1579 block_buffer_growth_ = true; 1580 } 1581 1582 void EndBlockGrowBuffer() { 1583 DCHECK(block_buffer_growth_); 1584 block_buffer_growth_ = false; 1585 } 1586 1587 bool is_buffer_growth_blocked() const { return block_buffer_growth_; } 1588 1589 void EmitForbiddenSlotInstruction() { 1590 if (IsPrevInstrCompactBranch()) { 1591 nop(); 1592 } 1593 } 1594 1595 inline void CheckTrampolinePoolQuick(int extra_instructions = 0) { 1596 if (pc_offset() >= next_buffer_check_ - extra_instructions * kInstrSize) { 1597 CheckTrampolinePool(); 1598 } 1599 } 1600 1601 inline void CheckBuffer(); 1602 1603 RegList scratch_register_list_; 1604 1605 // Generate common instruction sequence. 1606 void GenPCRelativeJump(Register tf, Register ts, int32_t imm32, 1607 RelocInfo::Mode rmode, BranchDelaySlot bdslot); 1608 void GenPCRelativeJumpAndLink(Register t, int32_t imm32, 1609 RelocInfo::Mode rmode, BranchDelaySlot bdslot); 1610 1611 void set_pc_for_safepoint() { pc_for_safepoint_ = pc_; } 1612 1613 private: 1614 // Avoid overflows for displacements etc. 1615 static const int kMaximalBufferSize = 512 * MB; 1616 1617 inline static void set_target_internal_reference_encoded_at(Address pc, 1618 Address target); 1619 1620 // Buffer size and constant pool distance are checked together at regular 1621 // intervals of kBufferCheckInterval emitted bytes. 1622 static constexpr int kBufferCheckInterval = 1 * KB / 2; 1623 1624 // Code generation. 1625 // The relocation writer's position is at least kGap bytes below the end of 1626 // the generated instructions. This is so that multi-instruction sequences do 1627 // not have to check for overflow. The same is true for writes of large 1628 // relocation info entries. 1629 static constexpr int kGap = 32; 1630 STATIC_ASSERT(AssemblerBase::kMinimalBufferSize >= 2 * kGap); 1631 1632 // Repeated checking whether the trampoline pool should be emitted is rather 1633 // expensive. By default we only check again once a number of instructions 1634 // has been generated. 1635 static constexpr int kCheckConstIntervalInst = 32; 1636 static constexpr int kCheckConstInterval = 1637 kCheckConstIntervalInst * kInstrSize; 1638 1639 int next_buffer_check_; // pc offset of next buffer check. 1640 1641 // Emission of the trampoline pool may be blocked in some code sequences. 1642 int trampoline_pool_blocked_nesting_; // Block emission if this is not zero. 1643 int no_trampoline_pool_before_; // Block emission before this pc offset. 1644 1645 // Keep track of the last emitted pool to guarantee a maximal distance. 1646 int last_trampoline_pool_end_; // pc offset of the end of the last pool. 1647 1648 // Automatic growth of the assembly buffer may be blocked for some sequences. 1649 bool block_buffer_growth_; // Block growth when true. 1650 1651 // Relocation information generation. 1652 // Each relocation is encoded as a variable size value. 1653 static constexpr int kMaxRelocSize = RelocInfoWriter::kMaxSize; 1654 RelocInfoWriter reloc_info_writer; 1655 1656 // The bound position, before this we cannot do instruction elimination. 1657 int last_bound_pos_; 1658 1659 // Readable constants for compact branch handling in emit() 1660 enum class CompactBranchType : bool { NO = false, COMPACT_BRANCH = true }; 1661 1662 // Code emission. 1663 void GrowBuffer(); 1664 inline void emit(Instr x, 1665 CompactBranchType is_compact_branch = CompactBranchType::NO); 1666 inline void emit(uint64_t x); 1667 inline void CheckForEmitInForbiddenSlot(); 1668 template <typename T> 1669 inline void EmitHelper(T x); 1670 inline void EmitHelper(Instr x, CompactBranchType is_compact_branch); 1671 1672 // Instruction generation. 1673 // We have 3 different kind of encoding layout on MIPS. 1674 // However due to many different types of objects encoded in the same fields 1675 // we have quite a few aliases for each mode. 1676 // Using the same structure to refer to Register and FPURegister would spare a 1677 // few aliases, but mixing both does not look clean to me. 1678 // Anyway we could surely implement this differently. 1679 1680 void GenInstrRegister(Opcode opcode, Register rs, Register rt, Register rd, 1681 uint16_t sa = 0, SecondaryField func = nullptrSF); 1682 1683 void GenInstrRegister(Opcode opcode, Register rs, Register rt, uint16_t msb, 1684 uint16_t lsb, SecondaryField func); 1685 1686 void GenInstrRegister(Opcode opcode, SecondaryField fmt, FPURegister ft, 1687 FPURegister fs, FPURegister fd, 1688 SecondaryField func = nullptrSF); 1689 1690 void GenInstrRegister(Opcode opcode, FPURegister fr, FPURegister ft, 1691 FPURegister fs, FPURegister fd, 1692 SecondaryField func = nullptrSF); 1693 1694 void GenInstrRegister(Opcode opcode, SecondaryField fmt, Register rt, 1695 FPURegister fs, FPURegister fd, 1696 SecondaryField func = nullptrSF); 1697 1698 void GenInstrRegister(Opcode opcode, SecondaryField fmt, Register rt, 1699 FPUControlRegister fs, SecondaryField func = nullptrSF); 1700 1701 void GenInstrImmediate( 1702 Opcode opcode, Register rs, Register rt, int32_t j, 1703 CompactBranchType is_compact_branch = CompactBranchType::NO); 1704 void GenInstrImmediate( 1705 Opcode opcode, Register rs, SecondaryField SF, int32_t j, 1706 CompactBranchType is_compact_branch = CompactBranchType::NO); 1707 void GenInstrImmediate( 1708 Opcode opcode, Register r1, FPURegister r2, int32_t j, 1709 CompactBranchType is_compact_branch = CompactBranchType::NO); 1710 void GenInstrImmediate(Opcode opcode, Register base, Register rt, 1711 int32_t offset9, int bit6, SecondaryField func); 1712 void GenInstrImmediate( 1713 Opcode opcode, Register rs, int32_t offset21, 1714 CompactBranchType is_compact_branch = CompactBranchType::NO); 1715 void GenInstrImmediate(Opcode opcode, Register rs, uint32_t offset21); 1716 void GenInstrImmediate( 1717 Opcode opcode, int32_t offset26, 1718 CompactBranchType is_compact_branch = CompactBranchType::NO); 1719 1720 void GenInstrJump(Opcode opcode, uint32_t address); 1721 1722 // MSA 1723 void GenInstrMsaI8(SecondaryField operation, uint32_t imm8, MSARegister ws, 1724 MSARegister wd); 1725 1726 void GenInstrMsaI5(SecondaryField operation, SecondaryField df, int32_t imm5, 1727 MSARegister ws, MSARegister wd); 1728 1729 void GenInstrMsaBit(SecondaryField operation, SecondaryField df, uint32_t m, 1730 MSARegister ws, MSARegister wd); 1731 1732 void GenInstrMsaI10(SecondaryField operation, SecondaryField df, 1733 int32_t imm10, MSARegister wd); 1734 1735 template <typename RegType> 1736 void GenInstrMsa3R(SecondaryField operation, SecondaryField df, RegType t, 1737 MSARegister ws, MSARegister wd); 1738 1739 template <typename DstType, typename SrcType> 1740 void GenInstrMsaElm(SecondaryField operation, SecondaryField df, uint32_t n, 1741 SrcType src, DstType dst); 1742 1743 void GenInstrMsa3RF(SecondaryField operation, uint32_t df, MSARegister wt, 1744 MSARegister ws, MSARegister wd); 1745 1746 void GenInstrMsaVec(SecondaryField operation, MSARegister wt, MSARegister ws, 1747 MSARegister wd); 1748 1749 void GenInstrMsaMI10(SecondaryField operation, int32_t s10, Register rs, 1750 MSARegister wd); 1751 1752 void GenInstrMsa2R(SecondaryField operation, SecondaryField df, 1753 MSARegister ws, MSARegister wd); 1754 1755 void GenInstrMsa2RF(SecondaryField operation, SecondaryField df, 1756 MSARegister ws, MSARegister wd); 1757 1758 void GenInstrMsaBranch(SecondaryField operation, MSARegister wt, 1759 int32_t offset16); 1760 1761 inline bool is_valid_msa_df_m(SecondaryField bit_df, uint32_t m) { 1762 switch (bit_df) { 1763 case BIT_DF_b: 1764 return is_uint3(m); 1765 case BIT_DF_h: 1766 return is_uint4(m); 1767 case BIT_DF_w: 1768 return is_uint5(m); 1769 case BIT_DF_d: 1770 return is_uint6(m); 1771 default: 1772 return false; 1773 } 1774 } 1775 1776 inline bool is_valid_msa_df_n(SecondaryField elm_df, uint32_t n) { 1777 switch (elm_df) { 1778 case ELM_DF_B: 1779 return is_uint4(n); 1780 case ELM_DF_H: 1781 return is_uint3(n); 1782 case ELM_DF_W: 1783 return is_uint2(n); 1784 case ELM_DF_D: 1785 return is_uint1(n); 1786 default: 1787 return false; 1788 } 1789 } 1790 1791 // Labels. 1792 void print(const Label* L); 1793 void bind_to(Label* L, int pos); 1794 void next(Label* L, bool is_internal); 1795 1796 // Patching lui/ori pair which is commonly used for loading constants. 1797 static void PatchLuiOriImmediate(Address pc, int32_t imm, Instr instr1, 1798 Address offset_lui, Instr instr2, 1799 Address offset_ori); 1800 void PatchLuiOriImmediate(int pc, int32_t imm, Instr instr1, 1801 Address offset_lui, Instr instr2, 1802 Address offset_ori); 1803 1804 // One trampoline consists of: 1805 // - space for trampoline slots, 1806 // - space for labels. 1807 // 1808 // Space for trampoline slots is equal to slot_count * 2 * kInstrSize. 1809 // Space for trampoline slots precedes space for labels. Each label is of one 1810 // instruction size, so total amount for labels is equal to 1811 // label_count * kInstrSize. 1812 class Trampoline { 1813 public: 1814 Trampoline() { 1815 start_ = 0; 1816 next_slot_ = 0; 1817 free_slot_count_ = 0; 1818 end_ = 0; 1819 } 1820 Trampoline(int start, int slot_count) { 1821 start_ = start; 1822 next_slot_ = start; 1823 free_slot_count_ = slot_count; 1824 end_ = start + slot_count * kTrampolineSlotsSize; 1825 } 1826 int start() { return start_; } 1827 int end() { return end_; } 1828 int take_slot() { 1829 int trampoline_slot = kInvalidSlotPos; 1830 if (free_slot_count_ <= 0) { 1831 // We have run out of space on trampolines. 1832 // Make sure we fail in debug mode, so we become aware of each case 1833 // when this happens. 1834 DCHECK(0); 1835 // Internal exception will be caught. 1836 } else { 1837 trampoline_slot = next_slot_; 1838 free_slot_count_--; 1839 next_slot_ += kTrampolineSlotsSize; 1840 } 1841 return trampoline_slot; 1842 } 1843 1844 private: 1845 int start_; 1846 int end_; 1847 int next_slot_; 1848 int free_slot_count_; 1849 }; 1850 1851 int32_t get_trampoline_entry(int32_t pos); 1852 int unbound_labels_count_; 1853 // If trampoline is emitted, generated code is becoming large. As this is 1854 // already a slow case which can possibly break our code generation for the 1855 // extreme case, we use this information to trigger different mode of 1856 // branch instruction generation, where we use jump instructions rather 1857 // than regular branch instructions. 1858 bool trampoline_emitted_; 1859 static constexpr int kInvalidSlotPos = -1; 1860 1861 // Internal reference positions, required for unbounded internal reference 1862 // labels. 1863 std::set<int> internal_reference_positions_; 1864 bool is_internal_reference(Label* L) { 1865 return internal_reference_positions_.find(L->pos()) != 1866 internal_reference_positions_.end(); 1867 } 1868 1869 void EmittedCompactBranchInstruction() { prev_instr_compact_branch_ = true; } 1870 void ClearCompactBranchState() { prev_instr_compact_branch_ = false; } 1871 bool prev_instr_compact_branch_ = false; 1872 1873 Trampoline trampoline_; 1874 bool internal_trampoline_exception_; 1875 1876 // Keep track of the last Call's position to ensure that safepoint can get the 1877 // correct information even if there is a trampoline immediately after the 1878 // Call. 1879 byte* pc_for_safepoint_; 1880 1881 private: 1882 void AllocateAndInstallRequestedHeapObjects(Isolate* isolate); 1883 1884 int WriteCodeComments(); 1885 1886 friend class RegExpMacroAssemblerMIPS; 1887 friend class RelocInfo; 1888 friend class BlockTrampolinePoolScope; 1889 friend class EnsureSpace; 1890}; 1891 1892class EnsureSpace { 1893 public: 1894 explicit V8_INLINE EnsureSpace(Assembler* assembler); 1895}; 1896 1897class V8_EXPORT_PRIVATE V8_NODISCARD UseScratchRegisterScope { 1898 public: 1899 explicit UseScratchRegisterScope(Assembler* assembler); 1900 ~UseScratchRegisterScope(); 1901 1902 Register Acquire(); 1903 bool hasAvailable() const; 1904 1905 void Include(const RegList& list) { *available_ |= list; } 1906 void Exclude(const RegList& list) { available_->clear(list); } 1907 void Include(const Register& reg1, const Register& reg2 = no_reg) { 1908 RegList list({reg1, reg2}); 1909 Include(list); 1910 } 1911 void Exclude(const Register& reg1, const Register& reg2 = no_reg) { 1912 RegList list({reg1, reg2}); 1913 Exclude(list); 1914 } 1915 1916 private: 1917 RegList* available_; 1918 RegList old_available_; 1919}; 1920 1921} // namespace internal 1922} // namespace v8 1923 1924#endif // V8_CODEGEN_MIPS_ASSEMBLER_MIPS_H_ 1925