1bf215546Sopenharmony_ciFADD.f32 r0, r1
2bf215546Sopenharmony_ciTEX.computed.2d.slot0 @r2, @r4:r5:r6:r7
3bf215546Sopenharmony_ciBRANCH
4bf215546Sopenharmony_ciBRANCH #0
5bf215546Sopenharmony_ciBRANCH #0, offset:
6bf215546Sopenharmony_ciBRANCH u0, offset:-123456789
7bf215546Sopenharmony_ciBRANCH u0, offset:123456789
8bf215546Sopenharmony_ciIADD_IMM.i32 r3, #12345
9bf215546Sopenharmony_ciFADD.v2f16 r0, r1, r0.h0
10bf215546Sopenharmony_ciMOV.i32.wait01.wait1 r0, r1
11bf215546Sopenharmony_ciMOV.i32.wait01.return r0, r1
12bf215546Sopenharmony_ciMOV.i32.reconverge.return r0, r1
13bf215546Sopenharmony_ciFROUND.f32.rtn.clamp_m1_1 r2, `r2.neg
14bf215546Sopenharmony_ci
15bf215546Sopenharmony_ci# An instruction may access no more than a single 64-bit uniform slot.
16bf215546Sopenharmony_ciFADD.f32 r0, u0, u4
17bf215546Sopenharmony_ciFADD.f32 r0, u5, u3
18bf215546Sopenharmony_ciFADD.f32 r0, u5, u6
19bf215546Sopenharmony_ci
20bf215546Sopenharmony_ci# An instruction may access no more than 64-bits of combined uniforms and constants.
21bf215546Sopenharmony_ciFMA.f32 r0, u0, u1, 0x0
22bf215546Sopenharmony_ciFMA.f32 r0, u0, 0x40490FDB, 0x0
23bf215546Sopenharmony_ciFMA.f32 r0, 0x3F317218, 0x40490FDB, 0x0
24bf215546Sopenharmony_ci
25bf215546Sopenharmony_ci# An instruction may access no more than a single special immediate (e.g. lane_id).
26bf215546Sopenharmony_ciIADD.u32 r0, lane_id, core_id
27bf215546Sopenharmony_ciIADD.u32 r0, lane_id, core_id
28bf215546Sopenharmony_ciIADD.u32 r0, tls_ptr, wls_ptr
29bf215546Sopenharmony_ci
30bf215546Sopenharmony_ci# If an instruction accesses multiple staging registers, they must be aligned
31bf215546Sopenharmony_ci# to a register pair.
32bf215546Sopenharmony_ciLOAD.i32.unsigned.slot0.wait0 @r1:r2, `r0, offset:0
33bf215546Sopenharmony_ciSTORE.i32.slot0.reconverge @r3:r4:r5, `r2, offset:0
34bf215546Sopenharmony_ciSTORE.i96.vary.slot0.return @r1:r2:r3:r4, `r4, offset:0
35