1/*
2 * Copyright 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24#include "isl_priv.h"
25#include "compiler/brw_compiler.h"
26
27bool
28isl_is_storage_image_format(enum isl_format format)
29{
30   /* XXX: Maybe we should put this in the CSV? */
31
32   switch (format) {
33   case ISL_FORMAT_R32G32B32A32_UINT:
34   case ISL_FORMAT_R32G32B32A32_SINT:
35   case ISL_FORMAT_R32G32B32A32_FLOAT:
36   case ISL_FORMAT_R32_UINT:
37   case ISL_FORMAT_R32_SINT:
38   case ISL_FORMAT_R32_FLOAT:
39   case ISL_FORMAT_R16G16B16A16_UINT:
40   case ISL_FORMAT_R16G16B16A16_SINT:
41   case ISL_FORMAT_R16G16B16A16_FLOAT:
42   case ISL_FORMAT_R32G32_UINT:
43   case ISL_FORMAT_R32G32_SINT:
44   case ISL_FORMAT_R32G32_FLOAT:
45   case ISL_FORMAT_R8G8B8A8_UINT:
46   case ISL_FORMAT_R8G8B8A8_SINT:
47   case ISL_FORMAT_R16G16_UINT:
48   case ISL_FORMAT_R16G16_SINT:
49   case ISL_FORMAT_R16G16_FLOAT:
50   case ISL_FORMAT_R8G8_UINT:
51   case ISL_FORMAT_R8G8_SINT:
52   case ISL_FORMAT_R16_UINT:
53   case ISL_FORMAT_R16_FLOAT:
54   case ISL_FORMAT_R16_SINT:
55   case ISL_FORMAT_R8_UINT:
56   case ISL_FORMAT_R8_SINT:
57   case ISL_FORMAT_R10G10B10A2_UINT:
58   case ISL_FORMAT_R10G10B10A2_UNORM:
59   case ISL_FORMAT_R11G11B10_FLOAT:
60   case ISL_FORMAT_R16G16B16A16_UNORM:
61   case ISL_FORMAT_R16G16B16A16_SNORM:
62   case ISL_FORMAT_R8G8B8A8_UNORM:
63   case ISL_FORMAT_R8G8B8A8_SNORM:
64   case ISL_FORMAT_R16G16_UNORM:
65   case ISL_FORMAT_R16G16_SNORM:
66   case ISL_FORMAT_R8G8_UNORM:
67   case ISL_FORMAT_R8G8_SNORM:
68   case ISL_FORMAT_R16_UNORM:
69   case ISL_FORMAT_R16_SNORM:
70   case ISL_FORMAT_R8_UNORM:
71   case ISL_FORMAT_R8_SNORM:
72      return true;
73   default:
74      return false;
75   }
76}
77
78enum isl_format
79isl_lower_storage_image_format(const struct intel_device_info *devinfo,
80                               enum isl_format format)
81{
82   switch (format) {
83   /* These are never lowered.  Up to BDW we'll have to fall back to untyped
84    * surface access for 128bpp formats.
85    */
86   case ISL_FORMAT_R32G32B32A32_UINT:
87   case ISL_FORMAT_R32G32B32A32_SINT:
88   case ISL_FORMAT_R32G32B32A32_FLOAT:
89   case ISL_FORMAT_R32_UINT:
90   case ISL_FORMAT_R32_SINT:
91      return format;
92
93   /* The Skylake PRM's "Surface Formats" section says:
94    *
95    *   "The surface format for the typed atomic integer operations must
96    *    be R32_UINT or R32_SINT."
97    */
98   case ISL_FORMAT_R32_FLOAT:
99      return ISL_FORMAT_R32_UINT;
100
101   /* From HSW to BDW the only 64bpp format supported for typed access is
102    * RGBA_UINT16.  IVB falls back to untyped.
103    */
104   case ISL_FORMAT_R16G16B16A16_UINT:
105   case ISL_FORMAT_R16G16B16A16_SINT:
106   case ISL_FORMAT_R16G16B16A16_FLOAT:
107   case ISL_FORMAT_R32G32_UINT:
108   case ISL_FORMAT_R32G32_SINT:
109   case ISL_FORMAT_R32G32_FLOAT:
110      return (devinfo->ver >= 9 ? format :
111              devinfo->verx10 >= 75 ?
112              ISL_FORMAT_R16G16B16A16_UINT :
113              ISL_FORMAT_R32G32_UINT);
114
115   /* Up to BDW no SINT or FLOAT formats of less than 32 bits per component
116    * are supported.  IVB doesn't support formats with more than one component
117    * for typed access.  For 8 and 16 bpp formats IVB relies on the
118    * undocumented behavior that typed reads from R_UINT8 and R_UINT16
119    * surfaces actually do a 32-bit misaligned read.  The alternative would be
120    * to use two surface state entries with different formats for each image,
121    * one for reading (using R_UINT32) and another one for writing (using
122    * R_UINT8 or R_UINT16), but that would complicate the shaders we generate
123    * even more.
124    */
125   case ISL_FORMAT_R8G8B8A8_UINT:
126   case ISL_FORMAT_R8G8B8A8_SINT:
127      return (devinfo->ver >= 9 ? format :
128              devinfo->verx10 >= 75 ?
129              ISL_FORMAT_R8G8B8A8_UINT : ISL_FORMAT_R32_UINT);
130
131   case ISL_FORMAT_R16G16_UINT:
132   case ISL_FORMAT_R16G16_SINT:
133   case ISL_FORMAT_R16G16_FLOAT:
134      return (devinfo->ver >= 9 ? format :
135              devinfo->verx10 >= 75 ?
136              ISL_FORMAT_R16G16_UINT : ISL_FORMAT_R32_UINT);
137
138   case ISL_FORMAT_R8G8_UINT:
139   case ISL_FORMAT_R8G8_SINT:
140      return (devinfo->ver >= 9 ? format :
141              devinfo->verx10 >= 75 ?
142              ISL_FORMAT_R8G8_UINT : ISL_FORMAT_R16_UINT);
143
144   case ISL_FORMAT_R16_UINT:
145   case ISL_FORMAT_R16_FLOAT:
146   case ISL_FORMAT_R16_SINT:
147      return (devinfo->ver >= 9 ? format : ISL_FORMAT_R16_UINT);
148
149   case ISL_FORMAT_R8_UINT:
150   case ISL_FORMAT_R8_SINT:
151      return (devinfo->ver >= 9 ? format : ISL_FORMAT_R8_UINT);
152
153   /* Neither the 2/10/10/10 nor the 11/11/10 packed formats are supported
154    * by the hardware.
155    */
156   case ISL_FORMAT_R10G10B10A2_UINT:
157   case ISL_FORMAT_R10G10B10A2_UNORM:
158   case ISL_FORMAT_R11G11B10_FLOAT:
159      return ISL_FORMAT_R32_UINT;
160
161   /* No normalized fixed-point formats are supported by the hardware. */
162   case ISL_FORMAT_R16G16B16A16_UNORM:
163   case ISL_FORMAT_R16G16B16A16_SNORM:
164      return (devinfo->ver >= 11 ? format :
165              devinfo->verx10 >= 75 ?
166              ISL_FORMAT_R16G16B16A16_UINT :
167              ISL_FORMAT_R32G32_UINT);
168
169   case ISL_FORMAT_R8G8B8A8_UNORM:
170   case ISL_FORMAT_R8G8B8A8_SNORM:
171      return (devinfo->ver >= 11 ? format :
172              devinfo->verx10 >= 75 ?
173              ISL_FORMAT_R8G8B8A8_UINT : ISL_FORMAT_R32_UINT);
174
175   case ISL_FORMAT_R16G16_UNORM:
176   case ISL_FORMAT_R16G16_SNORM:
177      return (devinfo->ver >= 11 ? format :
178              devinfo->verx10 >= 75 ?
179              ISL_FORMAT_R16G16_UINT : ISL_FORMAT_R32_UINT);
180
181   case ISL_FORMAT_R8G8_UNORM:
182   case ISL_FORMAT_R8G8_SNORM:
183      return (devinfo->ver >= 11 ? format :
184              devinfo->verx10 >= 75 ?
185              ISL_FORMAT_R8G8_UINT : ISL_FORMAT_R16_UINT);
186
187   case ISL_FORMAT_R16_UNORM:
188   case ISL_FORMAT_R16_SNORM:
189      return (devinfo->ver >= 11 ? format : ISL_FORMAT_R16_UINT);
190
191   case ISL_FORMAT_R8_UNORM:
192   case ISL_FORMAT_R8_SNORM:
193      return (devinfo->ver >= 11 ? format : ISL_FORMAT_R8_UINT);
194
195   default:
196      assert(!"Unknown image format");
197      return ISL_FORMAT_UNSUPPORTED;
198   }
199}
200
201bool
202isl_has_matching_typed_storage_image_format(const struct intel_device_info *devinfo,
203                                            enum isl_format fmt)
204{
205   if (devinfo->ver >= 9) {
206      return true;
207   } else if (devinfo->verx10 >= 75) {
208      return isl_format_get_layout(fmt)->bpb <= 64;
209   } else {
210      return isl_format_get_layout(fmt)->bpb <= 32;
211   }
212}
213
214static const struct brw_image_param image_param_defaults = {
215   /* Set the swizzling shifts to all-ones to effectively disable
216    * swizzling -- See emit_address_calculation() in
217    * brw_fs_surface_builder.cpp for a more detailed explanation of
218    * these parameters.
219    */
220   .swizzling = { 0xff, 0xff },
221};
222
223void
224isl_surf_fill_image_param(const struct isl_device *dev,
225                          struct brw_image_param *param,
226                          const struct isl_surf *surf,
227                          const struct isl_view *view)
228{
229   *param = image_param_defaults;
230
231   if (surf->dim != ISL_SURF_DIM_3D) {
232      assert(view->base_array_layer + view->array_len <=
233             surf->logical_level0_px.array_len);
234   }
235   param->size[0] = isl_minify(surf->logical_level0_px.w, view->base_level);
236   param->size[1] = surf->dim == ISL_SURF_DIM_1D ?
237                    view->array_len :
238                    isl_minify(surf->logical_level0_px.h, view->base_level);
239   param->size[2] = surf->dim == ISL_SURF_DIM_2D ?
240                    view->array_len :
241                    isl_minify(surf->logical_level0_px.d, view->base_level);
242
243   uint32_t tile_z_el, phys_array_layer;
244   isl_surf_get_image_offset_el(surf, view->base_level,
245                                surf->dim == ISL_SURF_DIM_3D ?
246                                   0 : view->base_array_layer,
247                                surf->dim == ISL_SURF_DIM_3D ?
248                                   view->base_array_layer : 0,
249                                &param->offset[0],  &param->offset[1],
250                                &tile_z_el, &phys_array_layer);
251   assert(tile_z_el == 0);
252   assert(phys_array_layer == 0);
253
254   const int cpp = isl_format_get_layout(surf->format)->bpb / 8;
255   param->stride[0] = cpp;
256   param->stride[1] = surf->row_pitch_B / cpp;
257
258   const struct isl_extent3d image_align_sa =
259      isl_surf_get_image_alignment_sa(surf);
260   if (ISL_GFX_VER(dev) < 9 && surf->dim == ISL_SURF_DIM_3D) {
261      param->stride[2] = isl_align_npot(param->size[0], image_align_sa.w);
262      param->stride[3] = isl_align_npot(param->size[1], image_align_sa.h);
263   } else {
264      param->stride[2] = 0;
265      param->stride[3] = isl_surf_get_array_pitch_el_rows(surf);
266   }
267
268   switch (surf->tiling) {
269   case ISL_TILING_LINEAR:
270      /* image_param_defaults is good enough */
271      break;
272
273   case ISL_TILING_X:
274      /* An X tile is a rectangular block of 512x8 bytes. */
275      param->tiling[0] = isl_log2u(512 / cpp);
276      param->tiling[1] = isl_log2u(8);
277
278      if (dev->has_bit6_swizzling) {
279         /* Right shifts required to swizzle bits 9 and 10 of the memory
280          * address with bit 6.
281          */
282         param->swizzling[0] = 3;
283         param->swizzling[1] = 4;
284      }
285      break;
286
287   case ISL_TILING_Y0:
288      /* The layout of a Y-tiled surface in memory isn't really fundamentally
289       * different to the layout of an X-tiled surface, we simply pretend that
290       * the surface is broken up in a number of smaller 16Bx32 tiles, each
291       * one arranged in X-major order just like is the case for X-tiling.
292       */
293      param->tiling[0] = isl_log2u(16 / cpp);
294      param->tiling[1] = isl_log2u(32);
295
296      if (dev->has_bit6_swizzling) {
297         /* Right shift required to swizzle bit 9 of the memory address with
298          * bit 6.
299          */
300         param->swizzling[0] = 3;
301         param->swizzling[1] = 0xff;
302      }
303      break;
304
305   default:
306      assert(!"Unhandled storage image tiling");
307   }
308
309   /* 3D textures are arranged in 2D in memory with 2^lod slices per row.  The
310    * address calculation algorithm (emit_address_calculation() in
311    * brw_fs_surface_builder.cpp) handles this as a sort of tiling with
312    * modulus equal to the LOD.
313    */
314   param->tiling[2] = (ISL_GFX_VER(dev) < 9 && surf->dim == ISL_SURF_DIM_3D ?
315                       view->base_level : 0);
316}
317
318void
319isl_buffer_fill_image_param(const struct isl_device *dev,
320                            struct brw_image_param *param,
321                            enum isl_format format,
322                            uint64_t size)
323{
324   *param = image_param_defaults;
325
326   param->stride[0] = isl_format_get_layout(format)->bpb / 8;
327   param->size[0] = size / param->stride[0];
328}
329