xref: /third_party/mesa3d/src/intel/isl/isl_gfx4.c (revision bf215546) 
1/*
2 * Copyright 2015 Intel Corporation
3 *
4 *  Permission is hereby granted, free of charge, to any person obtaining a
5 *  copy of this software and associated documentation files (the "Software"),
6 *  to deal in the Software without restriction, including without limitation
7 *  the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 *  and/or sell copies of the Software, and to permit persons to whom the
9 *  Software is furnished to do so, subject to the following conditions:
10 *
11 *  The above copyright notice and this permission notice (including the next
12 *  paragraph) shall be included in all copies or substantial portions of the
13 *  Software.
14 *
15 *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 *  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 *  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 *  THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 *  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 *  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 *  IN THE SOFTWARE.
22 */
23
24#include "isl_gfx4.h"
25#include "isl_priv.h"
26
27bool
28isl_gfx4_choose_msaa_layout(const struct isl_device *dev,
29                            const struct isl_surf_init_info *info,
30                            enum isl_tiling tiling,
31                            enum isl_msaa_layout *msaa_layout)
32{
33   /* Gfx4 and Gfx5 do not support MSAA */
34   assert(info->samples >= 1);
35
36   *msaa_layout = ISL_MSAA_LAYOUT_NONE;
37   return true;
38}
39
40void
41isl_gfx4_filter_tiling(const struct isl_device *dev,
42                       const struct isl_surf_init_info *restrict info,
43                       isl_tiling_flags_t *flags)
44{
45   /* Gfx4-5 only support linear, X, and Y-tiling. */
46   *flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT | ISL_TILING_Y0_BIT);
47
48   if (isl_surf_usage_is_depth_or_stencil(info->usage)) {
49      assert(!ISL_DEV_USE_SEPARATE_STENCIL(dev));
50
51      /* From the g35 PRM Vol. 2, 3DSTATE_DEPTH_BUFFER::Tile Walk:
52       *
53       *    "The Depth Buffer, if tiled, must use Y-Major tiling"
54       *
55       *    Errata   Description    Project
56       *    BWT014   The Depth Buffer Must be Tiled, it cannot be linear. This
57       *    field must be set to 1 on DevBW-A.  [DevBW -A,B]
58       *
59       * In testing, the linear configuration doesn't seem to work on I965. We
60       * choose to be consistent and require tiling for gfx4-5.
61       */
62      *flags &= ISL_TILING_Y0_BIT;
63   }
64
65   if (info->usage & ISL_SURF_USAGE_DISPLAY_BIT) {
66      /* Before Skylake, the display engine does not accept Y */
67      *flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT);
68   }
69
70   assert(info->samples == 1);
71
72   /* From the g35 PRM, Volume 1, 11.5.5, "Per-Stream Tile Format Support":
73    *
74    *    "NOTE: 128BPE Format Color buffer ( render target ) MUST be either
75    *    TileX or Linear."
76    *
77    * This is required all the way up to Sandy Bridge.
78    */
79   if (isl_format_get_layout(info->format)->bpb >= 128)
80      *flags &= ~ISL_TILING_Y0_BIT;
81}
82
83void
84isl_gfx4_choose_image_alignment_el(const struct isl_device *dev,
85                                   const struct isl_surf_init_info *restrict info,
86                                   enum isl_tiling tiling,
87                                   enum isl_dim_layout dim_layout,
88                                   enum isl_msaa_layout msaa_layout,
89                                   struct isl_extent3d *image_align_el)
90{
91   assert(info->samples == 1);
92   assert(msaa_layout == ISL_MSAA_LAYOUT_NONE);
93   assert(!isl_tiling_is_std_y(tiling));
94
95   /* Note that neither the surface's horizontal nor vertical image alignment
96    * is programmable on gfx4 nor gfx5.
97    *
98    * From the G35 PRM (2008-01), Volume 1 Graphics Core, Section 6.17.3.4
99    * Alignment Unit Size:
100    *
101    *    Note that the compressed formats are padded to a full compression
102    *    cell.
103    *
104    *    +------------------------+--------+--------+
105    *    | format                 | halign | valign |
106    *    +------------------------+--------+--------+
107    *    | YUV 4:2:2 formats      |      4 |      2 |
108    *    | uncompressed formats   |      4 |      2 |
109    *    +------------------------+--------+--------+
110    */
111
112   if (isl_format_is_compressed(info->format)) {
113      *image_align_el = isl_extent3d(1, 1, 1);
114      return;
115   }
116
117   *image_align_el = isl_extent3d(4, 2, 1);
118}
119