1/*
2 * Copyright 2016 Intel Corporation
3 *
4 *  Permission is hereby granted, free of charge, to any person obtaining a
5 *  copy of this software and associated documentation files (the "Software"),
6 *  to deal in the Software without restriction, including without limitation
7 *  the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 *  and/or sell copies of the Software, and to permit persons to whom the
9 *  Software is furnished to do so, subject to the following conditions:
10 *
11 *  The above copyright notice and this permission notice (including the next
12 *  paragraph) shall be included in all copies or substantial portions of the
13 *  Software.
14 *
15 *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 *  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 *  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 *  THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 *  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 *  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 *  IN THE SOFTWARE.
22 */
23
24#include <stdint.h>
25
26#define __gen_address_type uint64_t
27#define __gen_user_data void
28
29static uint64_t
30__gen_combine_address(__attribute__((unused)) void *data,
31                      __attribute__((unused)) void *loc, uint64_t addr,
32                      uint32_t delta)
33{
34   return addr + delta;
35}
36
37#include "genxml/gen_macros.h"
38#include "genxml/genX_pack.h"
39
40#include "isl_priv.h"
41
42static const uint32_t isl_encode_ds_surftype[] = {
43#if GFX_VER >= 9
44   /* From the SKL PRM, "3DSTATE_DEPTH_STENCIL::SurfaceType":
45    *
46    *    "If depth/stencil is enabled with 1D render target, depth/stencil
47    *    surface type needs to be set to 2D surface type and height set to 1.
48    *    Depth will use (legacy) TileY and stencil will use TileW. For this
49    *    case only, the Surface Type of the depth buffer can be 2D while the
50    *    Surface Type of the render target(s) are 1D, representing an
51    *    exception to a programming note above.
52    */
53   [ISL_SURF_DIM_1D] = SURFTYPE_2D,
54#else
55   [ISL_SURF_DIM_1D] = SURFTYPE_1D,
56#endif
57   [ISL_SURF_DIM_2D] = SURFTYPE_2D,
58   [ISL_SURF_DIM_3D] = SURFTYPE_3D,
59};
60
61#if GFX_VERx10 >= 125
62static const uint8_t isl_encode_tiling[] = {
63   [ISL_TILING_4]  = TILE4,
64   [ISL_TILING_64] = TILE64,
65};
66#endif
67
68void
69isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
70                                   const struct isl_depth_stencil_hiz_emit_info *restrict info)
71{
72   struct GENX(3DSTATE_DEPTH_BUFFER) db = {
73      GENX(3DSTATE_DEPTH_BUFFER_header),
74#if GFX_VER >= 6
75      .MOCS = info->mocs,
76#endif
77   };
78
79   if (info->depth_surf) {
80      db.SurfaceType = isl_encode_ds_surftype[info->depth_surf->dim];
81      db.SurfaceFormat = isl_surf_get_depth_format(dev, info->depth_surf);
82      db.Width = info->depth_surf->logical_level0_px.width - 1;
83      db.Height = info->depth_surf->logical_level0_px.height - 1;
84      if (db.SurfaceType == SURFTYPE_3D)
85         db.Depth = info->depth_surf->logical_level0_px.depth - 1;
86   } else if (info->stencil_surf) {
87      db.SurfaceType = isl_encode_ds_surftype[info->stencil_surf->dim];
88      db.SurfaceFormat = D32_FLOAT;
89      db.Width = info->stencil_surf->logical_level0_px.width - 1;
90      db.Height = info->stencil_surf->logical_level0_px.height - 1;
91      if (db.SurfaceType == SURFTYPE_3D)
92         db.Depth = info->stencil_surf->logical_level0_px.depth - 1;
93   } else {
94      db.SurfaceType = SURFTYPE_NULL;
95      db.SurfaceFormat = D32_FLOAT;
96   }
97
98   if (info->depth_surf || info->stencil_surf) {
99      /* These are based entirely on the view */
100      db.RenderTargetViewExtent = info->view->array_len - 1;
101      db.LOD                  = info->view->base_level;
102      db.MinimumArrayElement  = info->view->base_array_layer;
103
104      /* From the Haswell PRM docs for 3DSTATE_DEPTH_BUFFER::Depth
105       *
106       *    "This field specifies the total number of levels for a volume
107       *    texture or the number of array elements allowed to be accessed
108       *    starting at the Minimum Array Element for arrayed surfaces. If the
109       *    volume texture is MIP-mapped, this field specifies the depth of
110       *    the base MIP level."
111       *
112       * For 3D surfaces, we set it to the correct depth above.  For non-3D
113       * surfaces, this is the same as RenderTargetViewExtent.
114       */
115      if (db.SurfaceType != SURFTYPE_3D)
116         db.Depth = db.RenderTargetViewExtent;
117   }
118
119   if (info->depth_surf) {
120#if GFX_VER >= 7
121      db.DepthWriteEnable = true;
122#endif
123      db.SurfaceBaseAddress = info->depth_address;
124
125#if GFX_VERx10 >= 125
126      db.TiledMode = isl_encode_tiling[info->depth_surf->tiling];
127      db.MipTailStartLOD = 15;
128      db.CompressionMode = isl_aux_usage_has_ccs(info->hiz_usage);
129      db.RenderCompressionFormat =
130         isl_get_render_compression_format(info->depth_surf->format);
131#elif GFX_VER <= 6
132      assert(info->depth_surf->tiling == ISL_TILING_Y0);
133      db.TiledSurface = true;
134      db.TileWalk = TILEWALK_YMAJOR;
135      db.MIPMapLayoutMode = MIPLAYOUT_BELOW;
136#endif
137
138      db.SurfacePitch = info->depth_surf->row_pitch_B - 1;
139#if GFX_VER >= 8
140      db.SurfaceQPitch =
141         isl_surf_get_array_pitch_el_rows(info->depth_surf) >> 2;
142#endif
143
144#if GFX_VER >= 12
145      db.ControlSurfaceEnable = db.DepthBufferCompressionEnable =
146         isl_aux_usage_has_ccs(info->hiz_usage);
147#endif
148   }
149
150#if GFX_VER == 5 || GFX_VER == 6
151   const bool separate_stencil =
152      info->stencil_surf && info->stencil_surf->format == ISL_FORMAT_R8_UINT;
153   if (separate_stencil || info->hiz_usage == ISL_AUX_USAGE_HIZ) {
154      assert(ISL_DEV_USE_SEPARATE_STENCIL(dev));
155      /* From the IronLake PRM, Vol 2 Part 1:
156       *
157       *    3DSTATE_DEPTH_BUFFER::Separate Stencil Buffer Enable
158       *    If this field is enabled, Hierarchical Depth Buffer Enable must
159       *    also be enabled.
160       *
161       *    3DSTATE_DEPTH_BUFFER::Tiled Surface
162       *    When Hierarchical Depth Buffer is enabled, this bit must be set.
163       */
164      db.SeparateStencilBufferEnable = true;
165      db.HierarchicalDepthBufferEnable = true;
166      db.TiledSurface = true;
167   }
168#endif
169
170#if GFX_VER >= 6
171   struct GENX(3DSTATE_STENCIL_BUFFER) sb = {
172      GENX(3DSTATE_STENCIL_BUFFER_header),
173      .MOCS = info->mocs,
174   };
175#else
176#  define sb db
177#endif
178
179   if (info->stencil_surf) {
180#if GFX_VER >= 7 && GFX_VER < 12
181      db.StencilWriteEnable = true;
182#endif
183#if GFX_VERx10 >= 125
184      sb.TiledMode = isl_encode_tiling[info->stencil_surf->tiling];
185      sb.MipTailStartLOD = 15;
186      sb.CompressionMode = isl_aux_usage_has_ccs(info->stencil_aux_usage);
187      sb.RenderCompressionFormat =
188         isl_get_render_compression_format(info->stencil_surf->format);
189#endif
190#if GFX_VER >= 12
191      sb.StencilWriteEnable = true;
192      sb.SurfaceType = SURFTYPE_2D;
193      sb.Width = info->stencil_surf->logical_level0_px.width - 1;
194      sb.Height = info->stencil_surf->logical_level0_px.height - 1;
195      sb.Depth = sb.RenderTargetViewExtent = info->view->array_len - 1;
196      sb.SurfLOD = info->view->base_level;
197      sb.MinimumArrayElement = info->view->base_array_layer;
198      assert(info->stencil_aux_usage == ISL_AUX_USAGE_NONE ||
199             info->stencil_aux_usage == ISL_AUX_USAGE_STC_CCS);
200      sb.StencilCompressionEnable =
201         info->stencil_aux_usage == ISL_AUX_USAGE_STC_CCS;
202      sb.ControlSurfaceEnable = sb.StencilCompressionEnable;
203#elif GFX_VERx10 >= 75
204      sb.StencilBufferEnable = true;
205#endif
206      sb.SurfaceBaseAddress = info->stencil_address;
207      sb.SurfacePitch = info->stencil_surf->row_pitch_B - 1;
208#if GFX_VER >= 8
209      sb.SurfaceQPitch =
210         isl_surf_get_array_pitch_el_rows(info->stencil_surf) >> 2;
211#endif
212   } else {
213#if GFX_VER >= 12
214      sb.SurfaceType = SURFTYPE_NULL;
215
216      /* The docs seem to indicate that if surf-type is null, then we may need
217       * to match the depth-buffer value for `Depth`. It may be a
218       * documentation bug, since the other fields don't require this.
219       *
220       * TODO: Confirm documentation and remove setting of `Depth` if not
221       * required.
222       */
223      sb.Depth = db.Depth;
224#endif
225   }
226
227#if GFX_VER >= 6
228   struct GENX(3DSTATE_HIER_DEPTH_BUFFER) hiz = {
229      GENX(3DSTATE_HIER_DEPTH_BUFFER_header),
230      .MOCS = info->mocs,
231   };
232   struct GENX(3DSTATE_CLEAR_PARAMS) clear = {
233      GENX(3DSTATE_CLEAR_PARAMS_header),
234   };
235
236   assert(info->hiz_usage == ISL_AUX_USAGE_NONE ||
237          isl_aux_usage_has_hiz(info->hiz_usage));
238   if (isl_aux_usage_has_hiz(info->hiz_usage)) {
239      assert(GFX_VER >= 12 || info->hiz_usage == ISL_AUX_USAGE_HIZ);
240      db.HierarchicalDepthBufferEnable = true;
241
242      hiz.SurfaceBaseAddress = info->hiz_address;
243      hiz.SurfacePitch = info->hiz_surf->row_pitch_B - 1;
244
245#if GFX_VERx10 >= 125
246      /* From 3DSTATE_HIER_DEPTH_BUFFER_BODY::TiledMode,
247       *
248       *    HZ buffer only supports Tile4 mode
249       *
250       * and from Bspec 47009, "Hierarchical Depth Buffer",
251       *
252       *    The format of the data in the hierarchical depth buffer is not
253       *    documented here, as this surface needs only to be allocated by
254       *    software.
255       *
256       * We choose to apply the second quote to the first. ISL describes HiZ
257       * with a tiling that has the same extent as Tile4 (128Bx32), but a
258       * different internal layout. This has two benefits: 1) it allows us to
259       * have the correct allocation size and 2) we can continue to use a
260       * tiling that was determined to exist on some prior platforms.
261       */
262      assert(info->hiz_surf->tiling == ISL_TILING_HIZ);
263      hiz.TiledMode = TILE4;
264#endif
265
266#if GFX_VER >= 12
267      hiz.HierarchicalDepthBufferWriteThruEnable =
268         info->hiz_usage == ISL_AUX_USAGE_HIZ_CCS_WT;
269
270      /* The bspec docs for this bit are fairly unclear about exactly what is
271       * and isn't supported with HiZ write-through.  It's fairly clear that
272       * you can't sample from a multisampled depth buffer with CCS.  This
273       * limitation isn't called out explicitly but the docs for the CCS_E
274       * value of RENDER_SURFACE_STATE::AuxiliarySurfaceMode say:
275       *
276       *    "If Number of multisamples > 1, programming this value means MSAA
277       *    compression is enabled for that surface. Auxiliary surface is MSC
278       *    with tile y."
279       *
280       * Since this interpretation ignores whether the surface is
281       * depth/stencil or not and since multisampled depth buffers use
282       * ISL_MSAA_LAYOUT_INTERLEAVED which is incompatible with MCS
283       * compression, this means that we can't even specify MSAA depth CCS in
284       * RENDER_SURFACE_STATE::AuxiliarySurfaceMode.  The BSpec also says, for
285       * 3DSTATE_HIER_DEPTH_BUFFER::HierarchicalDepthBufferWriteThruEnable,
286       *
287       *    "This bit must NOT be set for >1x MSAA modes, since sampler
288       *    doesn't support sampling from >1x MSAA depth buffer."
289       *
290       * Again, this is all focused around what the sampler can do and not
291       * what the depth hardware can do.
292       *
293       * Reading even more internal docs which can't be quoted here makes it
294       * pretty clear that, even if it's not currently called out in the
295       * BSpec, HiZ+CCS write-through isn't intended to work with MSAA and we
296       * shouldn't try to use it.  Treat it as if it's disallowed even if the
297       * BSpec doesn't explicitly document that.
298       */
299      if (hiz.HierarchicalDepthBufferWriteThruEnable)
300         assert(info->depth_surf->samples == 1);
301#endif
302
303#if GFX_VER >= 8
304      /* From the SKL PRM Vol2a:
305       *
306       *    The interpretation of this field is dependent on Surface Type
307       *    as follows:
308       *    - SURFTYPE_1D: distance in pixels between array slices
309       *    - SURFTYPE_2D/CUBE: distance in rows between array slices
310       *    - SURFTYPE_3D: distance in rows between R - slices
311       *
312       * Unfortunately, the docs aren't 100% accurate here.  They fail to
313       * mention that the 1-D rule only applies to linear 1-D images.
314       * Since depth and HiZ buffers are always tiled, they are treated as
315       * 2-D images.  Prior to Sky Lake, this field is always in rows.
316       */
317      hiz.SurfaceQPitch =
318         isl_surf_get_array_pitch_sa_rows(info->hiz_surf) >> 2;
319#endif
320
321      clear.DepthClearValueValid = true;
322#if GFX_VER >= 8
323      clear.DepthClearValue = info->depth_clear_value;
324#else
325      switch (info->depth_surf->format) {
326      case ISL_FORMAT_R32_FLOAT: {
327         union { float f; uint32_t u; } fu;
328         fu.f = info->depth_clear_value;
329         clear.DepthClearValue = fu.u;
330         break;
331      }
332      case ISL_FORMAT_R24_UNORM_X8_TYPELESS:
333         clear.DepthClearValue = info->depth_clear_value * ((1u << 24) - 1);
334         break;
335      case ISL_FORMAT_R16_UNORM:
336         clear.DepthClearValue = info->depth_clear_value * ((1u << 16) - 1);
337         break;
338      default:
339         unreachable("Invalid depth type");
340      }
341#endif
342   }
343#endif /* GFX_VER >= 6 */
344
345   /* Pack everything into the batch */
346   uint32_t *dw = batch;
347   GENX(3DSTATE_DEPTH_BUFFER_pack)(NULL, dw, &db);
348   dw += GENX(3DSTATE_DEPTH_BUFFER_length);
349
350#if GFX_VER >= 6
351   GENX(3DSTATE_STENCIL_BUFFER_pack)(NULL, dw, &sb);
352   dw += GENX(3DSTATE_STENCIL_BUFFER_length);
353
354   GENX(3DSTATE_HIER_DEPTH_BUFFER_pack)(NULL, dw, &hiz);
355   dw += GENX(3DSTATE_HIER_DEPTH_BUFFER_length);
356
357   GENX(3DSTATE_CLEAR_PARAMS_pack)(NULL, dw, &clear);
358   dw += GENX(3DSTATE_CLEAR_PARAMS_length);
359#endif
360}
361