1/* 2 * Copyright 2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24#include <assert.h> 25#include <stdlib.h> 26 27#include "drm-uapi/drm_fourcc.h" 28#include "drm-uapi/i915_drm.h" 29 30#include "isl.h" 31#include "dev/intel_device_info.h" 32#include "dev/intel_debug.h" 33 34uint32_t 35isl_tiling_to_i915_tiling(enum isl_tiling tiling) 36{ 37 switch (tiling) { 38 case ISL_TILING_LINEAR: 39 return I915_TILING_NONE; 40 41 case ISL_TILING_X: 42 return I915_TILING_X; 43 44 case ISL_TILING_Y0: 45 case ISL_TILING_HIZ: 46 case ISL_TILING_CCS: 47 return I915_TILING_Y; 48 49 case ISL_TILING_W: 50 case ISL_TILING_Yf: 51 case ISL_TILING_Ys: 52 case ISL_TILING_4: 53 case ISL_TILING_64: 54 case ISL_TILING_GFX12_CCS: 55 return I915_TILING_NONE; 56 } 57 58 unreachable("Invalid ISL tiling"); 59} 60 61enum isl_tiling 62isl_tiling_from_i915_tiling(uint32_t tiling) 63{ 64 switch (tiling) { 65 case I915_TILING_NONE: 66 return ISL_TILING_LINEAR; 67 68 case I915_TILING_X: 69 return ISL_TILING_X; 70 71 case I915_TILING_Y: 72 return ISL_TILING_Y0; 73 } 74 75 unreachable("Invalid i915 tiling"); 76} 77 78/** Sentinel is DRM_FORMAT_MOD_INVALID. */ 79const struct isl_drm_modifier_info 80isl_drm_modifier_info_list[] = { 81 { 82 .modifier = DRM_FORMAT_MOD_NONE, 83 .name = "DRM_FORMAT_MOD_NONE", 84 .tiling = ISL_TILING_LINEAR, 85 }, 86 { 87 .modifier = I915_FORMAT_MOD_X_TILED, 88 .name = "I915_FORMAT_MOD_X_TILED", 89 .tiling = ISL_TILING_X, 90 }, 91 { 92 .modifier = I915_FORMAT_MOD_Y_TILED, 93 .name = "I915_FORMAT_MOD_Y_TILED", 94 .tiling = ISL_TILING_Y0, 95 }, 96 { 97 .modifier = I915_FORMAT_MOD_Y_TILED_CCS, 98 .name = "I915_FORMAT_MOD_Y_TILED_CCS", 99 .tiling = ISL_TILING_Y0, 100 .aux_usage = ISL_AUX_USAGE_CCS_E, 101 .supports_clear_color = false, 102 }, 103 { 104 .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, 105 .name = "I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS", 106 .tiling = ISL_TILING_Y0, 107 .aux_usage = ISL_AUX_USAGE_GFX12_CCS_E, 108 .supports_clear_color = false, 109 }, 110 { 111 .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, 112 .name = "I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS", 113 .tiling = ISL_TILING_Y0, 114 .aux_usage = ISL_AUX_USAGE_MC, 115 .supports_clear_color = false, 116 }, 117 { 118 .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC, 119 .name = "I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC", 120 .tiling = ISL_TILING_Y0, 121 .aux_usage = ISL_AUX_USAGE_GFX12_CCS_E, 122 .supports_clear_color = true, 123 }, 124 { 125 .modifier = I915_FORMAT_MOD_4_TILED, 126 .name = "I915_FORMAT_MOD_4_TILED", 127 .tiling = ISL_TILING_4, 128 }, 129 { 130 .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS, 131 .name = "I915_FORMAT_MOD_4_TILED_DG2_RC_CCS", 132 .tiling = ISL_TILING_4, 133 .aux_usage = ISL_AUX_USAGE_GFX12_CCS_E, 134 .supports_clear_color = false, 135 }, 136 { 137 .modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS, 138 .name = "I915_FORMAT_MOD_4_TILED_DG2_MC_CCS", 139 .tiling = ISL_TILING_4, 140 .aux_usage = ISL_AUX_USAGE_MC, 141 .supports_clear_color = false, 142 }, 143 { 144 .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC, 145 .name = "I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC", 146 .tiling = ISL_TILING_4, 147 .aux_usage = ISL_AUX_USAGE_GFX12_CCS_E, 148 .supports_clear_color = true, 149 }, 150 { 151 .modifier = DRM_FORMAT_MOD_INVALID, 152 }, 153}; 154 155const struct isl_drm_modifier_info * 156isl_drm_modifier_get_info(uint64_t modifier) 157{ 158 isl_drm_modifier_info_for_each(info) { 159 if (info->modifier == modifier) 160 return info; 161 } 162 163 return NULL; 164} 165 166uint32_t 167isl_drm_modifier_get_score(const struct intel_device_info *devinfo, 168 uint64_t modifier) 169{ 170 /* FINISHME: Add gfx12 modifiers */ 171 switch (modifier) { 172 default: 173 return 0; 174 case DRM_FORMAT_MOD_LINEAR: 175 return 1; 176 case I915_FORMAT_MOD_X_TILED: 177 return 2; 178 case I915_FORMAT_MOD_Y_TILED: 179 /* Gfx12.5 doesn't have Y-tiling. */ 180 if (devinfo->verx10 >= 125) 181 return 0; 182 183 return 3; 184 case I915_FORMAT_MOD_4_TILED: 185 /* Gfx12.5 introduces Tile4. */ 186 if (devinfo->verx10 < 125) 187 return 0; 188 189 return 3; 190 case I915_FORMAT_MOD_Y_TILED_CCS: 191 /* Gfx12's CCS layout differs from Gfx9-11. */ 192 if (devinfo->ver >= 12) 193 return 0; 194 195 if (INTEL_DEBUG(DEBUG_NO_CCS)) 196 return 0; 197 198 return 4; 199 } 200} 201