1/*
2 * Copyright (c) 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24#ifndef INTEL_L3_CONFIG_H
25#define INTEL_L3_CONFIG_H
26
27#include <stdio.h>
28
29#include "dev/intel_device_info.h"
30
31/**
32 * Chunk of L3 cache reserved for some specific purpose.
33 */
34enum intel_l3_partition {
35   /** Shared local memory. */
36   INTEL_L3P_SLM = 0,
37   /** Unified return buffer. */
38   INTEL_L3P_URB,
39   /** Union of DC and RO. */
40   INTEL_L3P_ALL,
41   /** Data cluster RW partition. */
42   INTEL_L3P_DC,
43   /** Union of IS, C and T. */
44   INTEL_L3P_RO,
45   /** Instruction and state cache. */
46   INTEL_L3P_IS,
47   /** Constant cache. */
48   INTEL_L3P_C,
49   /** Texture cache. */
50   INTEL_L3P_T,
51   /** Number of supported L3 partitions. */
52   INTEL_NUM_L3P
53};
54
55/**
56 * L3 configuration represented as the number of ways allocated for each
57 * partition.  \sa get_l3_way_size().
58 */
59struct intel_l3_config {
60   unsigned n[INTEL_NUM_L3P];
61};
62
63/**
64 * L3 configuration represented as a vector of weights giving the desired
65 * relative size of each partition.  The scale is arbitrary, only the ratios
66 * between weights will have an influence on the selection of the closest L3
67 * configuration.
68 */
69struct intel_l3_weights {
70   float w[INTEL_NUM_L3P];
71};
72
73float intel_diff_l3_weights(struct intel_l3_weights w0, struct intel_l3_weights w1);
74
75struct intel_l3_weights
76intel_get_default_l3_weights(const struct intel_device_info *devinfo,
77                             bool needs_dc, bool needs_slm);
78
79struct intel_l3_weights
80intel_get_l3_config_weights(const struct intel_l3_config *cfg);
81
82const struct intel_l3_config *
83intel_get_default_l3_config(const struct intel_device_info *devinfo);
84
85const struct intel_l3_config *
86intel_get_l3_config(const struct intel_device_info *devinfo,
87                    struct intel_l3_weights w0);
88
89unsigned
90intel_get_l3_config_urb_size(const struct intel_device_info *devinfo,
91                             const struct intel_l3_config *cfg);
92
93void intel_dump_l3_config(const struct intel_l3_config *cfg, FILE *fp);
94
95enum intel_urb_deref_block_size {
96   INTEL_URB_DEREF_BLOCK_SIZE_32         = 0,
97   INTEL_URB_DEREF_BLOCK_SIZE_PER_POLY   = 1,
98   INTEL_URB_DEREF_BLOCK_SIZE_8          = 2,
99   INTEL_URB_DEREF_BLOCK_SIZE_MESH       = 3,
100};
101
102void intel_get_urb_config(const struct intel_device_info *devinfo,
103                          const struct intel_l3_config *l3_cfg,
104                          bool tess_present, bool gs_present,
105                          const unsigned entry_size[4],
106                          unsigned entries[4], unsigned start[4],
107                          enum intel_urb_deref_block_size *deref_block_size,
108                          bool *constrained);
109
110struct intel_mesh_urb_allocation {
111   unsigned task_entries;
112   unsigned task_entry_size_64b;
113   unsigned task_starting_address_8kb;
114
115   unsigned mesh_entries;
116   unsigned mesh_entry_size_64b;
117   unsigned mesh_starting_address_8kb;
118
119   enum intel_urb_deref_block_size deref_block_size;
120};
121
122struct intel_mesh_urb_allocation
123intel_get_mesh_urb_config(const struct intel_device_info *devinfo,
124                          const struct intel_l3_config *l3_cfg,
125                          unsigned tue_size_dw, unsigned mue_size_dw);
126
127#endif /* INTEL_L3_CONFIG_H */
128