1/*
2 * Copyright © 2011 Red Hat All Rights Reserved.
3 * Copyright © 2014 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
25 * of the Software.
26 */
27
28#include "amdgpu_winsys.h"
29#include "util/format/u_format.h"
30
31static int amdgpu_surface_sanity(const struct pipe_resource *tex)
32{
33   switch (tex->target) {
34   case PIPE_TEXTURE_1D:
35      if (tex->height0 > 1)
36         return -EINVAL;
37      FALLTHROUGH;
38   case PIPE_TEXTURE_2D:
39   case PIPE_TEXTURE_RECT:
40      if (tex->depth0 > 1 || tex->array_size > 1)
41         return -EINVAL;
42      break;
43   case PIPE_TEXTURE_3D:
44      if (tex->array_size > 1)
45         return -EINVAL;
46      break;
47   case PIPE_TEXTURE_1D_ARRAY:
48      if (tex->height0 > 1)
49         return -EINVAL;
50      FALLTHROUGH;
51   case PIPE_TEXTURE_CUBE:
52   case PIPE_TEXTURE_2D_ARRAY:
53   case PIPE_TEXTURE_CUBE_ARRAY:
54      if (tex->depth0 > 1)
55         return -EINVAL;
56      break;
57   default:
58      return -EINVAL;
59   }
60   return 0;
61}
62
63static int amdgpu_surface_init(struct radeon_winsys *rws,
64                               const struct pipe_resource *tex,
65                               uint64_t flags, unsigned bpe,
66                               enum radeon_surf_mode mode,
67                               struct radeon_surf *surf)
68{
69   struct amdgpu_winsys *ws = amdgpu_winsys(rws);
70   int r;
71
72   r = amdgpu_surface_sanity(tex);
73   if (r)
74      return r;
75
76   surf->blk_w = util_format_get_blockwidth(tex->format);
77   surf->blk_h = util_format_get_blockheight(tex->format);
78   surf->bpe = bpe;
79   surf->flags = flags;
80
81   struct ac_surf_config config;
82
83   config.info.width = tex->width0;
84   config.info.height = tex->height0;
85   config.info.depth = tex->depth0;
86   config.info.array_size = tex->array_size;
87   config.info.samples = tex->nr_samples;
88   config.info.storage_samples = tex->nr_storage_samples;
89   config.info.levels = tex->last_level + 1;
90   config.info.num_channels = util_format_get_nr_components(tex->format);
91   config.is_1d = tex->target == PIPE_TEXTURE_1D ||
92                  tex->target == PIPE_TEXTURE_1D_ARRAY;
93   config.is_3d = tex->target == PIPE_TEXTURE_3D;
94   config.is_cube = tex->target == PIPE_TEXTURE_CUBE;
95
96   /* Use different surface counters for color and FMASK, so that MSAA MRTs
97    * always use consecutive surface indices when FMASK is allocated between
98    * them.
99    */
100   config.info.surf_index = &ws->surf_index_color;
101   config.info.fmask_surf_index = &ws->surf_index_fmask;
102
103   if (flags & RADEON_SURF_Z_OR_SBUFFER)
104      config.info.surf_index = NULL;
105
106   return ac_compute_surface(ws->addrlib, &ws->info, &config, mode, surf);
107}
108
109void amdgpu_surface_init_functions(struct amdgpu_screen_winsys *ws)
110{
111   ws->base.surface_init = amdgpu_surface_init;
112}
113