1/*
2 * Copyright 2011 Joakim Sindholt <opensource@zhasha.com>
3 * Copyright 2013 Christoph Bumiller
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24#include "device9.h"
25#include "nine_pipe.h"
26
27#include "cso_cache/cso_context.h"
28
29void
30nine_convert_dsa_state(struct pipe_depth_stencil_alpha_state *dsa_state,
31                       const DWORD *rs)
32{
33    struct pipe_depth_stencil_alpha_state dsa;
34
35    memset(&dsa, 0, sizeof(dsa)); /* memcmp safety */
36
37    if (rs[D3DRS_ZENABLE]) {
38        dsa.depth_enabled = 1;
39        dsa.depth_func = d3dcmpfunc_to_pipe_func(rs[D3DRS_ZFUNC]);
40        /* Disable depth write if no change can occur */
41        dsa.depth_writemask = !!rs[D3DRS_ZWRITEENABLE] &&
42            dsa.depth_func != PIPE_FUNC_EQUAL &&
43            dsa.depth_func != PIPE_FUNC_NEVER;
44    }
45
46    if (rs[D3DRS_STENCILENABLE]) {
47        dsa.stencil[0].enabled = 1;
48        dsa.stencil[0].func = d3dcmpfunc_to_pipe_func(rs[D3DRS_STENCILFUNC]);
49        dsa.stencil[0].fail_op = d3dstencilop_to_pipe_stencil_op(rs[D3DRS_STENCILFAIL]);
50        dsa.stencil[0].zpass_op = d3dstencilop_to_pipe_stencil_op(rs[D3DRS_STENCILPASS]);
51        dsa.stencil[0].zfail_op = d3dstencilop_to_pipe_stencil_op(rs[D3DRS_STENCILZFAIL]);
52        dsa.stencil[0].valuemask = rs[D3DRS_STENCILMASK];
53        dsa.stencil[0].writemask = rs[D3DRS_STENCILWRITEMASK];
54
55        if (rs[D3DRS_TWOSIDEDSTENCILMODE]) {
56            dsa.stencil[1].enabled = 1;
57            dsa.stencil[1].func = d3dcmpfunc_to_pipe_func(rs[D3DRS_CCW_STENCILFUNC]);
58            dsa.stencil[1].fail_op = d3dstencilop_to_pipe_stencil_op(rs[D3DRS_CCW_STENCILFAIL]);
59            dsa.stencil[1].zpass_op = d3dstencilop_to_pipe_stencil_op(rs[D3DRS_CCW_STENCILPASS]);
60            dsa.stencil[1].zfail_op = d3dstencilop_to_pipe_stencil_op(rs[D3DRS_CCW_STENCILZFAIL]);
61            dsa.stencil[1].valuemask = dsa.stencil[0].valuemask;
62            dsa.stencil[1].writemask = dsa.stencil[0].writemask;
63        }
64    }
65
66    if (rs[D3DRS_ALPHATESTENABLE]) {
67        dsa.alpha_enabled = 1;
68        dsa.alpha_func = d3dcmpfunc_to_pipe_func(rs[D3DRS_ALPHAFUNC]);
69        dsa.alpha_ref_value = (float)rs[D3DRS_ALPHAREF] / 255.0f;
70    }
71
72    *dsa_state = dsa;
73}
74
75void
76nine_convert_rasterizer_state(struct NineDevice9 *device,
77                              struct pipe_rasterizer_state *rast_state,
78                              const DWORD *rs)
79{
80    struct pipe_rasterizer_state rast;
81
82    memset(&rast, 0, sizeof(rast));
83
84    rast.flatshade = rs[D3DRS_SHADEMODE] == D3DSHADE_FLAT;
85 /* rast.light_twoside = 0; */
86 /* rast.clamp_fragment_color = 0; */
87 /* rast.clamp_vertex_color = 0; */
88 /* rast.front_ccw = 0; */
89    rast.cull_face = d3dcull_to_pipe_face(rs[D3DRS_CULLMODE]);
90    rast.fill_front = d3dfillmode_to_pipe_polygon_mode(rs[D3DRS_FILLMODE]);
91    rast.fill_back = rast.fill_front;
92    rast.offset_tri = !!(rs[D3DRS_DEPTHBIAS] | rs[D3DRS_SLOPESCALEDEPTHBIAS]);
93    rast.offset_line = rast.offset_tri; /* triangles in wireframe mode */
94    rast.offset_point = 0; /* XXX ? */
95    rast.scissor = !!rs[D3DRS_SCISSORTESTENABLE];
96 /* rast.poly_smooth = 0; */
97 /* rast.poly_stipple_enable = 0; */
98 /* rast.point_smooth = 0; */
99    rast.sprite_coord_mode = PIPE_SPRITE_COORD_UPPER_LEFT;
100    rast.point_quad_rasterization = 1;
101    rast.point_size_per_vertex = rs[NINED3DRS_VSPOINTSIZE];
102    rast.multisample = rs[NINED3DRS_MULTISAMPLE];
103    rast.line_smooth = !!rs[D3DRS_ANTIALIASEDLINEENABLE];
104 /* rast.line_stipple_enable = 0; */
105    rast.line_last_pixel = !!rs[D3DRS_LASTPIXEL];
106    rast.flatshade_first = 1;
107 /* rast.half_pixel_center = 0; */
108 /* rast.lower_left_origin = 0; */
109 /* rast.bottom_edge_rule = 0; */
110 /* rast.rasterizer_discard = 0; */
111    rast.depth_clip_near = 1;
112    rast.depth_clip_far = 1;
113    rast.clip_halfz = 1;
114    rast.clip_plane_enable = rs[D3DRS_CLIPPLANEENABLE];
115 /* rast.line_stipple_factor = 0; */
116 /* rast.line_stipple_pattern = 0; */
117    rast.sprite_coord_enable = rs[D3DRS_POINTSPRITEENABLE] ? 0xff : 0x00;
118    rast.line_width = 1.0f;
119    rast.line_rectangular = 0;
120    if (rs[NINED3DRS_VSPOINTSIZE]) {
121        rast.point_size = 1.0f;
122    } else {
123        rast.point_size = CLAMP(asfloat(rs[D3DRS_POINTSIZE]),
124                asfloat(rs[D3DRS_POINTSIZE_MIN]),
125                asfloat(rs[D3DRS_POINTSIZE_MAX]));
126    }
127    /* offset_units has the ogl/d3d11 meaning.
128     * d3d9: offset = scale * dz + bias
129     * ogl/d3d11: offset = scale * dz + r * bias
130     * with r implementation dependent (+ different formula for float depth
131     * buffers). r=2^-23 is often the right value for gallium drivers.
132     * If possible, use offset_units_unscaled, which gives the d3d9
133     * behaviour, else scale by 1 << 23 */
134    rast.offset_units = asfloat(rs[D3DRS_DEPTHBIAS]) * (device->driver_caps.offset_units_unscaled ? 1.0f : (float)(1 << 23));
135    rast.offset_units_unscaled = device->driver_caps.offset_units_unscaled;
136    rast.offset_scale = asfloat(rs[D3DRS_SLOPESCALEDEPTHBIAS]);
137 /* rast.offset_clamp = 0.0f; */
138
139    *rast_state = rast;
140}
141
142static inline void
143nine_convert_blend_state_fixup(struct pipe_blend_state *blend, const DWORD *rs)
144{
145    if (unlikely(rs[D3DRS_SRCBLEND] == D3DBLEND_BOTHSRCALPHA ||
146                 rs[D3DRS_SRCBLEND] == D3DBLEND_BOTHINVSRCALPHA)) {
147        blend->rt[0].rgb_dst_factor = (rs[D3DRS_SRCBLEND] == D3DBLEND_BOTHSRCALPHA) ?
148            PIPE_BLENDFACTOR_INV_SRC_ALPHA : PIPE_BLENDFACTOR_SRC_ALPHA;
149        if (!rs[D3DRS_SEPARATEALPHABLENDENABLE])
150            blend->rt[0].alpha_dst_factor = blend->rt[0].rgb_dst_factor;
151    } else
152    if (unlikely(rs[D3DRS_SEPARATEALPHABLENDENABLE] &&
153                 (rs[D3DRS_SRCBLENDALPHA] == D3DBLEND_BOTHSRCALPHA ||
154                  rs[D3DRS_SRCBLENDALPHA] == D3DBLEND_BOTHINVSRCALPHA))) {
155        blend->rt[0].alpha_dst_factor = (rs[D3DRS_SRCBLENDALPHA] == D3DBLEND_BOTHSRCALPHA) ?
156            PIPE_BLENDFACTOR_INV_SRC_ALPHA : PIPE_BLENDFACTOR_SRC_ALPHA;
157    }
158}
159
160void
161nine_convert_blend_state(struct pipe_blend_state *blend_state, const DWORD *rs)
162{
163    struct pipe_blend_state blend;
164
165    memset(&blend, 0, sizeof(blend)); /* memcmp safety */
166
167    blend.dither = !!rs[D3DRS_DITHERENABLE];
168
169 /* blend.alpha_to_one = 0; */
170    blend.alpha_to_coverage = !!(rs[NINED3DRS_ALPHACOVERAGE] & 5);
171
172    blend.rt[0].blend_enable = !!rs[D3DRS_ALPHABLENDENABLE];
173    if (blend.rt[0].blend_enable) {
174        blend.rt[0].rgb_func = d3dblendop_to_pipe_blend(rs[D3DRS_BLENDOP]);
175        blend.rt[0].rgb_src_factor = d3dblend_color_to_pipe_blendfactor(rs[D3DRS_SRCBLEND]);
176        blend.rt[0].rgb_dst_factor = d3dblend_color_to_pipe_blendfactor(rs[D3DRS_DESTBLEND]);
177        if (rs[D3DRS_SEPARATEALPHABLENDENABLE]) {
178            blend.rt[0].alpha_func = d3dblendop_to_pipe_blend(rs[D3DRS_BLENDOPALPHA]);
179            blend.rt[0].alpha_src_factor = d3dblend_alpha_to_pipe_blendfactor(rs[D3DRS_SRCBLENDALPHA]);
180            blend.rt[0].alpha_dst_factor = d3dblend_alpha_to_pipe_blendfactor(rs[D3DRS_DESTBLENDALPHA]);
181        } else {
182            /* TODO: Just copy the rgb values ? SRC1_x may differ ... */
183            blend.rt[0].alpha_func = blend.rt[0].rgb_func;
184            blend.rt[0].alpha_src_factor = d3dblend_alpha_to_pipe_blendfactor(rs[D3DRS_SRCBLEND]);
185            blend.rt[0].alpha_dst_factor = d3dblend_alpha_to_pipe_blendfactor(rs[D3DRS_DESTBLEND]);
186        }
187        nine_convert_blend_state_fixup(&blend, rs); /* for BOTH[INV]SRCALPHA */
188    }
189
190    blend.max_rt = 3; /* Upper bound. Could be optimized to fb->nr_cbufs for example */
191    blend.rt[0].colormask = rs[D3DRS_COLORWRITEENABLE];
192
193    if (rs[D3DRS_COLORWRITEENABLE1] != rs[D3DRS_COLORWRITEENABLE] ||
194        rs[D3DRS_COLORWRITEENABLE2] != rs[D3DRS_COLORWRITEENABLE] ||
195        rs[D3DRS_COLORWRITEENABLE3] != rs[D3DRS_COLORWRITEENABLE]) {
196        unsigned i;
197        blend.independent_blend_enable = TRUE;
198        for (i = 1; i < 4; ++i)
199            blend.rt[i] = blend.rt[0];
200        blend.rt[1].colormask = rs[D3DRS_COLORWRITEENABLE1];
201        blend.rt[2].colormask = rs[D3DRS_COLORWRITEENABLE2];
202        blend.rt[3].colormask = rs[D3DRS_COLORWRITEENABLE3];
203    }
204
205    /* blend.force_srgb = !!rs[D3DRS_SRGBWRITEENABLE]; */
206
207    *blend_state = blend;
208}
209
210void
211nine_convert_sampler_state(struct cso_context *ctx, int idx, const DWORD *ss)
212{
213    struct pipe_sampler_state samp;
214
215    assert(idx >= 0 &&
216           (idx < NINE_MAX_SAMPLERS_PS || idx >= NINE_SAMPLER_VS(0)) &&
217           (idx < NINE_MAX_SAMPLERS));
218
219    if (ss[D3DSAMP_MIPFILTER] != D3DTEXF_NONE) {
220        samp.lod_bias = asfloat(ss[D3DSAMP_MIPMAPLODBIAS]);
221        samp.min_lod = ss[NINED3DSAMP_MINLOD];
222        samp.min_mip_filter = (ss[D3DSAMP_MIPFILTER] == D3DTEXF_POINT) ? PIPE_TEX_FILTER_NEAREST : PIPE_TEX_FILTER_LINEAR;
223    } else {
224        samp.min_lod = 0.0;
225        samp.lod_bias = 0.0;
226        samp.min_mip_filter = PIPE_TEX_MIPFILTER_NONE;
227    }
228    samp.max_lod = 15.0f;
229
230    if (ss[NINED3DSAMP_CUBETEX]) {
231        /* Cube textures are always clamped to edge on D3D */
232        samp.wrap_s = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
233        samp.wrap_t = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
234        samp.wrap_r = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
235    } else {
236        samp.wrap_s = d3dtextureaddress_to_pipe_tex_wrap(ss[D3DSAMP_ADDRESSU]);
237        samp.wrap_t = d3dtextureaddress_to_pipe_tex_wrap(ss[D3DSAMP_ADDRESSV]);
238        samp.wrap_r = d3dtextureaddress_to_pipe_tex_wrap(ss[D3DSAMP_ADDRESSW]);
239    }
240    samp.min_img_filter = (ss[D3DSAMP_MINFILTER] == D3DTEXF_POINT && !ss[NINED3DSAMP_SHADOW]) ? PIPE_TEX_FILTER_NEAREST : PIPE_TEX_FILTER_LINEAR;
241    samp.mag_img_filter = (ss[D3DSAMP_MAGFILTER] == D3DTEXF_POINT && !ss[NINED3DSAMP_SHADOW]) ? PIPE_TEX_FILTER_NEAREST : PIPE_TEX_FILTER_LINEAR;
242    if (ss[D3DSAMP_MINFILTER] == D3DTEXF_ANISOTROPIC ||
243        ss[D3DSAMP_MAGFILTER] == D3DTEXF_ANISOTROPIC)
244        samp.max_anisotropy = MIN2(16, ss[D3DSAMP_MAXANISOTROPY]);
245    else
246        samp.max_anisotropy = 0;
247    samp.compare_mode = ss[NINED3DSAMP_SHADOW] ? PIPE_TEX_COMPARE_R_TO_TEXTURE : PIPE_TEX_COMPARE_NONE;
248    samp.compare_func = PIPE_FUNC_LEQUAL;
249    samp.normalized_coords = 1;
250    samp.seamless_cube_map = 0;
251    samp.border_color_is_integer = 0;
252    samp.reduction_mode = 0;
253    samp.pad = 0;
254    samp.border_color_format = PIPE_FORMAT_NONE;
255    d3dcolor_to_pipe_color_union(&samp.border_color, ss[D3DSAMP_BORDERCOLOR]);
256
257    /* see nine_state.h */
258    if (idx < NINE_MAX_SAMPLERS_PS)
259        cso_single_sampler(ctx, PIPE_SHADER_FRAGMENT, idx - NINE_SAMPLER_PS(0), &samp);
260    else
261        cso_single_sampler(ctx, PIPE_SHADER_VERTEX, idx - NINE_SAMPLER_VS(0), &samp);
262}
263
264const enum pipe_format nine_d3d9_to_pipe_format_map[120] =
265{
266   [D3DFMT_UNKNOWN]       = PIPE_FORMAT_NONE,
267   [D3DFMT_R8G8B8]        = PIPE_FORMAT_R8G8B8_UNORM,
268   [D3DFMT_A8R8G8B8]      = PIPE_FORMAT_B8G8R8A8_UNORM,
269   [D3DFMT_X8R8G8B8]      = PIPE_FORMAT_B8G8R8X8_UNORM,
270   [D3DFMT_R5G6B5]        = PIPE_FORMAT_B5G6R5_UNORM,
271   [D3DFMT_X1R5G5B5]      = PIPE_FORMAT_B5G5R5X1_UNORM,
272   [D3DFMT_A1R5G5B5]      = PIPE_FORMAT_B5G5R5A1_UNORM,
273   [D3DFMT_A4R4G4B4]      = PIPE_FORMAT_B4G4R4A4_UNORM,
274   [D3DFMT_R3G3B2]        = PIPE_FORMAT_B2G3R3_UNORM,
275   [D3DFMT_A8]            = PIPE_FORMAT_A8_UNORM,
276   [D3DFMT_A8R3G3B2]      = PIPE_FORMAT_NONE,
277   [D3DFMT_X4R4G4B4]      = PIPE_FORMAT_B4G4R4X4_UNORM,
278   [D3DFMT_A2B10G10R10]   = PIPE_FORMAT_R10G10B10A2_UNORM,
279   [D3DFMT_A8B8G8R8]      = PIPE_FORMAT_R8G8B8A8_UNORM,
280   [D3DFMT_X8B8G8R8]      = PIPE_FORMAT_R8G8B8X8_UNORM,
281   [D3DFMT_G16R16]        = PIPE_FORMAT_R16G16_UNORM,
282   [D3DFMT_A2R10G10B10]   = PIPE_FORMAT_B10G10R10A2_UNORM,
283   [D3DFMT_A16B16G16R16]  = PIPE_FORMAT_R16G16B16A16_UNORM,
284   [D3DFMT_A8P8]          = PIPE_FORMAT_NONE,
285   [D3DFMT_P8]            = PIPE_FORMAT_NONE,
286   [D3DFMT_L8]            = PIPE_FORMAT_L8_UNORM,
287   [D3DFMT_A8L8]          = PIPE_FORMAT_L8A8_UNORM,
288   [D3DFMT_A4L4]          = PIPE_FORMAT_L4A4_UNORM,
289   [D3DFMT_V8U8]          = PIPE_FORMAT_R8G8_SNORM,
290   [D3DFMT_L6V5U5]        = PIPE_FORMAT_NONE, /* Should be PIPE_FORMAT_R5SG5SB6U_NORM, but interpretation of the data differs a bit. */
291   [D3DFMT_X8L8V8U8]      = PIPE_FORMAT_R8SG8SB8UX8U_NORM,
292   [D3DFMT_Q8W8V8U8]      = PIPE_FORMAT_R8G8B8A8_SNORM,
293   [D3DFMT_V16U16]        = PIPE_FORMAT_R16G16_SNORM,
294   [D3DFMT_A2W10V10U10]   = PIPE_FORMAT_R10SG10SB10SA2U_NORM,
295   [D3DFMT_D16_LOCKABLE]  = PIPE_FORMAT_Z16_UNORM,
296   [D3DFMT_D32]           = PIPE_FORMAT_Z32_UNORM,
297   [D3DFMT_D15S1]         = PIPE_FORMAT_NONE,
298   [D3DFMT_D24S8]         = PIPE_FORMAT_S8_UINT_Z24_UNORM,
299   [D3DFMT_D24X8]         = PIPE_FORMAT_X8Z24_UNORM,
300   [D3DFMT_D24X4S4]       = PIPE_FORMAT_NONE,
301   [D3DFMT_D16]           = PIPE_FORMAT_Z16_UNORM,
302   [D3DFMT_D32F_LOCKABLE] = PIPE_FORMAT_Z32_FLOAT,
303   [D3DFMT_D24FS8]        = PIPE_FORMAT_Z32_FLOAT_S8X24_UINT,
304   [D3DFMT_D32_LOCKABLE]  = PIPE_FORMAT_NONE,
305   [D3DFMT_S8_LOCKABLE]   = PIPE_FORMAT_NONE,
306   [D3DFMT_L16]           = PIPE_FORMAT_L16_UNORM,
307   [D3DFMT_VERTEXDATA]    = PIPE_FORMAT_NONE,
308   [D3DFMT_INDEX16]       = PIPE_FORMAT_R16_UINT,
309   [D3DFMT_INDEX32]       = PIPE_FORMAT_R32_UINT,
310   [D3DFMT_Q16W16V16U16]  = PIPE_FORMAT_R16G16B16A16_SNORM,
311   [D3DFMT_R16F]          = PIPE_FORMAT_R16_FLOAT,
312   [D3DFMT_G16R16F]       = PIPE_FORMAT_R16G16_FLOAT,
313   [D3DFMT_A16B16G16R16F] = PIPE_FORMAT_R16G16B16A16_FLOAT,
314   [D3DFMT_R32F]          = PIPE_FORMAT_R32_FLOAT,
315   [D3DFMT_G32R32F]       = PIPE_FORMAT_R32G32_FLOAT,
316   [D3DFMT_A32B32G32R32F] = PIPE_FORMAT_R32G32B32A32_FLOAT,
317   [D3DFMT_CxV8U8]        = PIPE_FORMAT_NONE,
318   [D3DFMT_A1]            = PIPE_FORMAT_NONE,
319   [D3DFMT_A2B10G10R10_XR_BIAS] = PIPE_FORMAT_NONE,
320};
321
322const D3DFORMAT nine_pipe_to_d3d9_format_map[PIPE_FORMAT_COUNT] =
323{
324   [PIPE_FORMAT_NONE]               = D3DFMT_UNKNOWN,
325   /* TODO: rename PIPE_FORMAT_R8G8B8_UNORM to PIPE_FORMAT_B8G8R8_UNORM */
326   [PIPE_FORMAT_R8G8B8_UNORM]       = D3DFMT_R8G8B8,
327   [PIPE_FORMAT_B8G8R8A8_UNORM]     = D3DFMT_A8R8G8B8,
328   [PIPE_FORMAT_B8G8R8X8_UNORM]     = D3DFMT_X8R8G8B8,
329   [PIPE_FORMAT_B5G6R5_UNORM]       = D3DFMT_R5G6B5,
330   [PIPE_FORMAT_B5G5R5X1_UNORM]     = D3DFMT_X1R5G5B5,
331   [PIPE_FORMAT_B5G5R5A1_UNORM]     = D3DFMT_A1R5G5B5,
332   [PIPE_FORMAT_B4G4R4A4_UNORM]     = D3DFMT_A4R4G4B4,
333   [PIPE_FORMAT_B2G3R3_UNORM]       = D3DFMT_R3G3B2,
334   [PIPE_FORMAT_A8_UNORM]           = D3DFMT_A8,
335/* [PIPE_FORMAT_B2G3R3A8_UNORM]     = D3DFMT_A8R3G3B2, */
336   [PIPE_FORMAT_B4G4R4X4_UNORM]     = D3DFMT_X4R4G4B4,
337   [PIPE_FORMAT_R10G10B10A2_UNORM]  = D3DFMT_A2B10G10R10,
338   [PIPE_FORMAT_R8G8B8A8_UNORM]     = D3DFMT_A8B8G8R8,
339   [PIPE_FORMAT_R8G8B8X8_UNORM]     = D3DFMT_X8B8G8R8,
340   [PIPE_FORMAT_R16G16_UNORM]       = D3DFMT_G16R16,
341   [PIPE_FORMAT_B10G10R10A2_UNORM]  = D3DFMT_A2R10G10B10,
342   [PIPE_FORMAT_R16G16B16A16_UNORM] = D3DFMT_A16B16G16R16,
343
344   [PIPE_FORMAT_R8_UINT]            = D3DFMT_P8,
345   [PIPE_FORMAT_R8A8_UINT]          = D3DFMT_A8P8,
346
347   [PIPE_FORMAT_L8_UNORM]           = D3DFMT_L8,
348   [PIPE_FORMAT_L8A8_UNORM]         = D3DFMT_A8L8,
349   [PIPE_FORMAT_L4A4_UNORM]         = D3DFMT_A4L4,
350
351   [PIPE_FORMAT_R8G8_SNORM]           = D3DFMT_V8U8,
352/* [PIPE_FORMAT_?]                    = D3DFMT_L6V5U5, */
353/* [PIPE_FORMAT_?]                    = D3DFMT_X8L8V8U8, */
354   [PIPE_FORMAT_R8G8B8A8_SNORM]       = D3DFMT_Q8W8V8U8,
355   [PIPE_FORMAT_R16G16_SNORM]         = D3DFMT_V16U16,
356   [PIPE_FORMAT_R10SG10SB10SA2U_NORM] = D3DFMT_A2W10V10U10,
357
358   [PIPE_FORMAT_YUYV]               = D3DFMT_UYVY,
359/* [PIPE_FORMAT_YUY2]               = D3DFMT_YUY2, */
360   [PIPE_FORMAT_DXT1_RGBA]          = D3DFMT_DXT1,
361/* [PIPE_FORMAT_DXT2_RGBA]          = D3DFMT_DXT2, */
362   [PIPE_FORMAT_DXT3_RGBA]          = D3DFMT_DXT3,
363/* [PIPE_FORMAT_DXT4_RGBA]          = D3DFMT_DXT4, */
364   [PIPE_FORMAT_DXT5_RGBA]          = D3DFMT_DXT5,
365/* [PIPE_FORMAT_?]                  = D3DFMT_MULTI2_ARGB8, (MET) */
366   [PIPE_FORMAT_R8G8_B8G8_UNORM]    = D3DFMT_R8G8_B8G8, /* XXX: order */
367   [PIPE_FORMAT_G8R8_G8B8_UNORM]    = D3DFMT_G8R8_G8B8,
368
369   [PIPE_FORMAT_Z16_UNORM]          = D3DFMT_D16_LOCKABLE,
370   [PIPE_FORMAT_Z32_UNORM]          = D3DFMT_D32,
371/* [PIPE_FORMAT_Z15_UNORM_S1_UINT]  = D3DFMT_D15S1, */
372   [PIPE_FORMAT_S8_UINT_Z24_UNORM]  = D3DFMT_D24S8,
373   [PIPE_FORMAT_X8Z24_UNORM]        = D3DFMT_D24X8,
374   [PIPE_FORMAT_L16_UNORM]          = D3DFMT_L16,
375   [PIPE_FORMAT_Z32_FLOAT]          = D3DFMT_D32F_LOCKABLE,
376/* [PIPE_FORMAT_Z24_FLOAT_S8_UINT]  = D3DFMT_D24FS8, */
377
378   [PIPE_FORMAT_R16_UINT]           = D3DFMT_INDEX16,
379   [PIPE_FORMAT_R32_UINT]           = D3DFMT_INDEX32,
380   [PIPE_FORMAT_R16G16B16A16_SNORM] = D3DFMT_Q16W16V16U16,
381
382   [PIPE_FORMAT_R16_FLOAT]          = D3DFMT_R16F,
383   [PIPE_FORMAT_R32_FLOAT]          = D3DFMT_R32F,
384   [PIPE_FORMAT_R16G16_FLOAT]       = D3DFMT_G16R16F,
385   [PIPE_FORMAT_R32G32_FLOAT]       = D3DFMT_G32R32F,
386   [PIPE_FORMAT_R16G16B16A16_FLOAT] = D3DFMT_A16B16G16R16F,
387   [PIPE_FORMAT_R32G32B32A32_FLOAT] = D3DFMT_A32B32G32R32F,
388
389/* [PIPE_FORMAT_?]                  = D3DFMT_CxV8U8, */
390};
391