1/* 2 * Copyright 2014, 2015 Red Hat. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23#include "util/u_memory.h" 24#include "util/format/u_format.h" 25#include "util/format/u_format_s3tc.h" 26#include "util/u_screen.h" 27#include "util/u_video.h" 28#include "util/u_math.h" 29#include "util/u_inlines.h" 30#include "util/os_time.h" 31#include "util/xmlconfig.h" 32#include "pipe/p_defines.h" 33#include "pipe/p_screen.h" 34#include "nir/nir_to_tgsi.h" 35 36#include "tgsi/tgsi_exec.h" 37 38#include "virgl_screen.h" 39#include "virgl_resource.h" 40#include "virgl_public.h" 41#include "virgl_context.h" 42#include "virtio-gpu/virgl_protocol.h" 43#include "virgl_encode.h" 44 45int virgl_debug = 0; 46static const struct debug_named_value virgl_debug_options[] = { 47 { "verbose", VIRGL_DEBUG_VERBOSE, NULL }, 48 { "tgsi", VIRGL_DEBUG_TGSI, NULL }, 49 { "use_tgsi", VIRGL_DEBUG_USE_TGSI, NULL }, 50 { "noemubgra", VIRGL_DEBUG_NO_EMULATE_BGRA, "Disable tweak to emulate BGRA as RGBA on GLES hosts"}, 51 { "nobgraswz", VIRGL_DEBUG_NO_BGRA_DEST_SWIZZLE,"Disable tweak to swizzle emulated BGRA on GLES hosts" }, 52 { "sync", VIRGL_DEBUG_SYNC, "Sync after every flush" }, 53 { "xfer", VIRGL_DEBUG_XFER, "Do not optimize for transfers" }, 54 { "r8srgb-readback", VIRGL_DEBUG_L8_SRGB_ENABLE_READBACK, "Enable redaback for L8 sRGB textures" }, 55 { "nocoherent", VIRGL_DEBUG_NO_COHERENT, "Disable coherent memory"}, 56 DEBUG_NAMED_VALUE_END 57}; 58DEBUG_GET_ONCE_FLAGS_OPTION(virgl_debug, "VIRGL_DEBUG", virgl_debug_options, 0) 59 60static const char * 61virgl_get_vendor(struct pipe_screen *screen) 62{ 63 return "Mesa/X.org"; 64} 65 66 67static const char * 68virgl_get_name(struct pipe_screen *screen) 69{ 70 struct virgl_screen *vscreen = virgl_screen(screen); 71 if (vscreen->caps.caps.v2.host_feature_check_version >= 5) 72 return vscreen->caps.caps.v2.renderer; 73 74 return "virgl"; 75} 76 77static int 78virgl_get_param(struct pipe_screen *screen, enum pipe_cap param) 79{ 80 struct virgl_screen *vscreen = virgl_screen(screen); 81 switch (param) { 82 case PIPE_CAP_NPOT_TEXTURES: 83 return 1; 84 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD: 85 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES: 86 return 1; 87 case PIPE_CAP_ANISOTROPIC_FILTER: 88 return vscreen->caps.caps.v2.max_anisotropy > 1.0; 89 case PIPE_CAP_POINT_SPRITE: 90 return 1; 91 case PIPE_CAP_MAX_RENDER_TARGETS: 92 return vscreen->caps.caps.v1.max_render_targets; 93 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: 94 return vscreen->caps.caps.v1.max_dual_source_render_targets; 95 case PIPE_CAP_OCCLUSION_QUERY: 96 return vscreen->caps.caps.v1.bset.occlusion_query; 97 case PIPE_CAP_TEXTURE_MIRROR_CLAMP: 98 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE: 99 return vscreen->caps.caps.v1.bset.mirror_clamp; 100 case PIPE_CAP_TEXTURE_SWIZZLE: 101 return 1; 102 case PIPE_CAP_MAX_TEXTURE_2D_SIZE: 103 if (vscreen->caps.caps.v2.max_texture_2d_size) 104 return vscreen->caps.caps.v2.max_texture_2d_size; 105 return 16384; 106 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: 107 if (vscreen->caps.caps.v2.max_texture_3d_size) 108 return 1 + util_logbase2(vscreen->caps.caps.v2.max_texture_3d_size); 109 return 9; /* 256 x 256 x 256 */ 110 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: 111 if (vscreen->caps.caps.v2.max_texture_cube_size) 112 return 1 + util_logbase2(vscreen->caps.caps.v2.max_texture_cube_size); 113 return 13; /* 4K x 4K */ 114 case PIPE_CAP_BLEND_EQUATION_SEPARATE: 115 return 1; 116 case PIPE_CAP_INDEP_BLEND_ENABLE: 117 return vscreen->caps.caps.v1.bset.indep_blend_enable; 118 case PIPE_CAP_INDEP_BLEND_FUNC: 119 return vscreen->caps.caps.v1.bset.indep_blend_func; 120 case PIPE_CAP_FS_COORD_ORIGIN_UPPER_LEFT: 121 case PIPE_CAP_FS_COORD_PIXEL_CENTER_HALF_INTEGER: 122 case PIPE_CAP_FS_COORD_PIXEL_CENTER_INTEGER: 123 return 1; 124 case PIPE_CAP_FS_COORD_ORIGIN_LOWER_LEFT: 125 return vscreen->caps.caps.v1.bset.fragment_coord_conventions; 126 case PIPE_CAP_DEPTH_CLIP_DISABLE: 127 if (vscreen->caps.caps.v1.bset.depth_clip_disable) 128 return 1; 129 return 0; 130 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: 131 return vscreen->caps.caps.v1.max_streamout_buffers; 132 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: 133 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: 134 return 16*4; 135 case PIPE_CAP_SUPPORTED_PRIM_MODES: 136 return BITFIELD_MASK(PIPE_PRIM_MAX) & 137 ~BITFIELD_BIT(PIPE_PRIM_QUADS) & 138 ~BITFIELD_BIT(PIPE_PRIM_QUAD_STRIP); 139 case PIPE_CAP_PRIMITIVE_RESTART: 140 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX: 141 return vscreen->caps.caps.v1.bset.primitive_restart; 142 case PIPE_CAP_SHADER_STENCIL_EXPORT: 143 return vscreen->caps.caps.v1.bset.shader_stencil_export; 144 case PIPE_CAP_VS_INSTANCEID: 145 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: 146 return 1; 147 case PIPE_CAP_SEAMLESS_CUBE_MAP: 148 return vscreen->caps.caps.v1.bset.seamless_cube_map; 149 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: 150 return vscreen->caps.caps.v1.bset.seamless_cube_map_per_texture; 151 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: 152 return vscreen->caps.caps.v1.max_texture_array_layers; 153 case PIPE_CAP_MIN_TEXEL_OFFSET: 154 return vscreen->caps.caps.v2.min_texel_offset; 155 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET: 156 return vscreen->caps.caps.v2.min_texture_gather_offset; 157 case PIPE_CAP_MAX_TEXEL_OFFSET: 158 return vscreen->caps.caps.v2.max_texel_offset; 159 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET: 160 return vscreen->caps.caps.v2.max_texture_gather_offset; 161 case PIPE_CAP_CONDITIONAL_RENDER: 162 return vscreen->caps.caps.v1.bset.conditional_render; 163 case PIPE_CAP_TEXTURE_BARRIER: 164 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TEXTURE_BARRIER; 165 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: 166 return 1; 167 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: 168 case PIPE_CAP_VERTEX_COLOR_CLAMPED: 169 return vscreen->caps.caps.v1.bset.color_clamping; 170 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: 171 return (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_FBO_MIXED_COLOR_FORMATS) || 172 (vscreen->caps.caps.v2.host_feature_check_version < 1); 173 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY: 174 if (vscreen->caps.caps.v2.host_feature_check_version < 6) 175 return MIN2(vscreen->caps.caps.v1.glsl_level, 140); 176 FALLTHROUGH; 177 case PIPE_CAP_GLSL_FEATURE_LEVEL: 178 return vscreen->caps.caps.v1.glsl_level; 179 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION: 180 return 1; 181 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE: 182 return 0; 183 case PIPE_CAP_COMPUTE: 184 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER; 185 case PIPE_CAP_USER_VERTEX_BUFFERS: 186 return 0; 187 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: 188 return vscreen->caps.caps.v2.uniform_buffer_offset_alignment; 189 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME: 190 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS: 191 return vscreen->caps.caps.v1.bset.streamout_pause_resume; 192 case PIPE_CAP_START_INSTANCE: 193 return vscreen->caps.caps.v1.bset.start_instance; 194 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: 195 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: 196 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: 197 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: 198 case PIPE_CAP_TEXTURE_TRANSFER_MODES: 199 case PIPE_CAP_NIR_IMAGES_AS_DEREF: 200 return 0; 201 case PIPE_CAP_QUERY_TIMESTAMP: 202 return 1; 203 case PIPE_CAP_QUERY_TIME_ELAPSED: 204 return 1; 205 case PIPE_CAP_TGSI_TEXCOORD: 206 return vscreen->caps.caps.v2.host_feature_check_version >= 10; 207 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT: 208 return VIRGL_MAP_BUFFER_ALIGNMENT; 209 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS: 210 return vscreen->caps.caps.v1.max_tbo_size > 0; 211 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: 212 return vscreen->caps.caps.v2.texture_buffer_offset_alignment; 213 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY: 214 return 0; 215 case PIPE_CAP_CUBE_MAP_ARRAY: 216 return vscreen->caps.caps.v1.bset.cube_map_array; 217 case PIPE_CAP_TEXTURE_MULTISAMPLE: 218 return vscreen->caps.caps.v1.bset.texture_multisample; 219 case PIPE_CAP_MAX_VIEWPORTS: 220 return vscreen->caps.caps.v1.max_viewports; 221 case PIPE_CAP_MAX_TEXEL_BUFFER_ELEMENTS_UINT: 222 return vscreen->caps.caps.v1.max_tbo_size; 223 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: 224 case PIPE_CAP_QUERY_PIPELINE_STATISTICS: 225 case PIPE_CAP_ENDIANNESS: 226 return 0; 227 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: 228 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS: 229 return 1; 230 case PIPE_CAP_VS_LAYER_VIEWPORT: 231 return 0; 232 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES: 233 return vscreen->caps.caps.v2.max_geom_output_vertices; 234 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS: 235 return vscreen->caps.caps.v2.max_geom_total_output_components; 236 case PIPE_CAP_TEXTURE_QUERY_LOD: 237 return vscreen->caps.caps.v1.bset.texture_query_lod; 238 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS: 239 return vscreen->caps.caps.v1.max_texture_gather_components; 240 case PIPE_CAP_DRAW_INDIRECT: 241 return vscreen->caps.caps.v1.bset.has_indirect_draw; 242 case PIPE_CAP_SAMPLE_SHADING: 243 case PIPE_CAP_FORCE_PERSAMPLE_INTERP: 244 return vscreen->caps.caps.v1.bset.has_sample_shading; 245 case PIPE_CAP_CULL_DISTANCE: 246 return vscreen->caps.caps.v1.bset.has_cull; 247 case PIPE_CAP_MAX_VERTEX_STREAMS: 248 return ((vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TRANSFORM_FEEDBACK3) || 249 (vscreen->caps.caps.v2.host_feature_check_version < 2)) ? 4 : 1; 250 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED: 251 return vscreen->caps.caps.v1.bset.conditional_render_inverted; 252 case PIPE_CAP_FS_FINE_DERIVATIVE: 253 return vscreen->caps.caps.v1.bset.derivative_control; 254 case PIPE_CAP_POLYGON_OFFSET_CLAMP: 255 return vscreen->caps.caps.v1.bset.polygon_offset_clamp; 256 case PIPE_CAP_QUERY_SO_OVERFLOW: 257 return vscreen->caps.caps.v1.bset.transform_feedback_overflow_query; 258 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT: 259 return vscreen->caps.caps.v2.shader_buffer_offset_alignment; 260 case PIPE_CAP_DOUBLES: 261 return vscreen->caps.caps.v1.bset.has_fp64 || 262 (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_FAKE_FP64); 263 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS: 264 return vscreen->caps.caps.v2.max_shader_patch_varyings; 265 case PIPE_CAP_SAMPLER_VIEW_TARGET: 266 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TEXTURE_VIEW; 267 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE: 268 return vscreen->caps.caps.v2.max_vertex_attrib_stride; 269 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS: 270 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COPY_IMAGE; 271 case PIPE_CAP_TEXTURE_QUERY_SAMPLES: 272 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TXQS; 273 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT: 274 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_FB_NO_ATTACH; 275 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR: 276 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_ROBUST_BUFFER_ACCESS; 277 case PIPE_CAP_FBFETCH: 278 return (vscreen->caps.caps.v2.capability_bits & 279 VIRGL_CAP_TGSI_FBFETCH) ? 1 : 0; 280 case PIPE_CAP_BLEND_EQUATION_ADVANCED: 281 return vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_BLEND_EQUATION; 282 case PIPE_CAP_SHADER_CLOCK: 283 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_SHADER_CLOCK; 284 case PIPE_CAP_SHADER_ARRAY_COMPONENTS: 285 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TGSI_COMPONENTS; 286 case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS: 287 return vscreen->caps.caps.v2.max_combined_shader_buffers; 288 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS: 289 return vscreen->caps.caps.v2.max_combined_atomic_counters; 290 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS: 291 return vscreen->caps.caps.v2.max_combined_atomic_counter_buffers; 292 case PIPE_CAP_TEXTURE_FLOAT_LINEAR: 293 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR: 294 return 1; /* TODO: need to introduce a hw-cap for this */ 295 case PIPE_CAP_QUERY_BUFFER_OBJECT: 296 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_QBO; 297 case PIPE_CAP_MAX_VARYINGS: 298 if (vscreen->caps.caps.v1.glsl_level < 150) 299 return vscreen->caps.caps.v2.max_vertex_attribs; 300 return 32; 301 case PIPE_CAP_FAKE_SW_MSAA: 302 /* If the host supports only one sample (e.g., if it is using softpipe), 303 * fake multisampling to able to advertise higher GL versions. */ 304 return (vscreen->caps.caps.v1.max_samples == 1) ? 1 : 0; 305 case PIPE_CAP_MULTI_DRAW_INDIRECT: 306 return !!(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_MULTI_DRAW_INDIRECT); 307 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS: 308 return !!(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_INDIRECT_PARAMS); 309 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT: 310 return (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_ARB_BUFFER_STORAGE) && 311 (vscreen->caps.caps.v2.host_feature_check_version >= 4) && 312 vscreen->vws->supports_coherent && !vscreen->no_coherent; 313 case PIPE_CAP_PCI_GROUP: 314 case PIPE_CAP_PCI_BUS: 315 case PIPE_CAP_PCI_DEVICE: 316 case PIPE_CAP_PCI_FUNCTION: 317 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION: 318 return 0; 319 case PIPE_CAP_CLEAR_TEXTURE: 320 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_CLEAR_TEXTURE; 321 case PIPE_CAP_CLIP_HALFZ: 322 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_CLIP_HALFZ; 323 case PIPE_CAP_MAX_GS_INVOCATIONS: 324 return 32; 325 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT: 326 return 1 << 27; 327 case PIPE_CAP_VENDOR_ID: 328 return 0x1af4; 329 case PIPE_CAP_DEVICE_ID: 330 return 0x1010; 331 case PIPE_CAP_ACCELERATED: 332 return -1; /* -1 means unknown */ 333 case PIPE_CAP_UMA: 334 case PIPE_CAP_VIDEO_MEMORY: 335 if (vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_VIDEO_MEMORY) 336 return vscreen->caps.caps.v2.max_video_memory; 337 return 0; 338 case PIPE_CAP_NATIVE_FENCE_FD: 339 return vscreen->vws->supports_fences; 340 case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL: 341 return (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_SRGB_WRITE_CONTROL) || 342 (vscreen->caps.caps.v2.host_feature_check_version < 1); 343 case PIPE_CAP_SHAREABLE_SHADERS: 344 /* Shader creation emits the shader through the context's command buffer 345 * in virgl_encode_shader_state(). 346 */ 347 return 0; 348 case PIPE_CAP_QUERY_MEMORY_INFO: 349 return vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_MEMINFO; 350 case PIPE_CAP_STRING_MARKER: 351 return vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_STRING_MARKER; 352 case PIPE_CAP_SURFACE_SAMPLE_COUNT: 353 return vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_IMPLICIT_MSAA; 354 case PIPE_CAP_IMAGE_STORE_FORMATTED: 355 return 1; 356 case PIPE_CAP_MAX_CONSTANT_BUFFER_SIZE_UINT: 357 if (vscreen->caps.caps.v2.host_feature_check_version >= 13) 358 return vscreen->caps.caps.v2.max_uniform_block_size; 359 FALLTHROUGH; 360 default: 361 return u_pipe_screen_get_param_defaults(screen, param); 362 } 363} 364 365static int 366virgl_get_shader_param(struct pipe_screen *screen, 367 enum pipe_shader_type shader, 368 enum pipe_shader_cap param) 369{ 370 struct virgl_screen *vscreen = virgl_screen(screen); 371 372 if ((shader == PIPE_SHADER_TESS_CTRL || shader == PIPE_SHADER_TESS_EVAL) && 373 !vscreen->caps.caps.v1.bset.has_tessellation_shaders) 374 return 0; 375 376 if (shader == PIPE_SHADER_COMPUTE && 377 !(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER)) 378 return 0; 379 380 switch(shader) 381 { 382 case PIPE_SHADER_FRAGMENT: 383 case PIPE_SHADER_VERTEX: 384 case PIPE_SHADER_GEOMETRY: 385 case PIPE_SHADER_TESS_CTRL: 386 case PIPE_SHADER_TESS_EVAL: 387 case PIPE_SHADER_COMPUTE: 388 switch (param) { 389 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: 390 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: 391 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: 392 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: 393 return INT_MAX; 394 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: 395 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: 396 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: 397 return 1; 398 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: 399 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: 400 return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_INDIRECT_INPUT_ADDR; 401 case PIPE_SHADER_CAP_MAX_INPUTS: 402 if (vscreen->caps.caps.v1.glsl_level < 150) 403 return vscreen->caps.caps.v2.max_vertex_attribs; 404 return (shader == PIPE_SHADER_VERTEX || 405 shader == PIPE_SHADER_GEOMETRY) ? vscreen->caps.caps.v2.max_vertex_attribs : 32; 406 case PIPE_SHADER_CAP_MAX_OUTPUTS: 407 if (shader == PIPE_SHADER_FRAGMENT) 408 return vscreen->caps.caps.v1.max_render_targets; 409 return vscreen->caps.caps.v2.max_vertex_outputs; 410 // case PIPE_SHADER_CAP_MAX_CONSTS: 411 // return 4096; 412 case PIPE_SHADER_CAP_MAX_TEMPS: 413 return 256; 414 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: 415 return vscreen->caps.caps.v1.max_uniform_blocks; 416 // case PIPE_SHADER_CAP_MAX_ADDRS: 417 // return 1; 418 case PIPE_SHADER_CAP_SUBROUTINES: 419 return 1; 420 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: 421 return MIN2(vscreen->caps.caps.v2.max_shader_sampler_views, 422 PIPE_MAX_SHADER_SAMPLER_VIEWS); 423 case PIPE_SHADER_CAP_INTEGERS: 424 return vscreen->caps.caps.v1.glsl_level >= 130; 425 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: 426 return 32; 427 case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE: 428 if (vscreen->caps.caps.v2.host_feature_check_version < 12) 429 return 4096 * sizeof(float[4]); 430 return vscreen->caps.caps.v2.max_const_buffer_size[shader]; 431 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: 432 if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE) 433 return vscreen->caps.caps.v2.max_shader_buffer_frag_compute; 434 else 435 return vscreen->caps.caps.v2.max_shader_buffer_other_stages; 436 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: 437 if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE) 438 return vscreen->caps.caps.v2.max_shader_image_frag_compute; 439 else 440 return vscreen->caps.caps.v2.max_shader_image_other_stages; 441 case PIPE_SHADER_CAP_PREFERRED_IR: 442 return (virgl_debug & VIRGL_DEBUG_USE_TGSI) ? PIPE_SHADER_IR_TGSI : PIPE_SHADER_IR_NIR; 443 case PIPE_SHADER_CAP_SUPPORTED_IRS: 444 return (1 << PIPE_SHADER_IR_TGSI) | ((virgl_debug & VIRGL_DEBUG_USE_TGSI) ? 0 : (1 << PIPE_SHADER_IR_NIR)); 445 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: 446 return vscreen->caps.caps.v2.max_atomic_counters[shader]; 447 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: 448 return vscreen->caps.caps.v2.max_atomic_counter_buffers[shader]; 449 case PIPE_SHADER_CAP_INT64_ATOMICS: 450 case PIPE_SHADER_CAP_FP16: 451 case PIPE_SHADER_CAP_FP16_DERIVATIVES: 452 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS: 453 case PIPE_SHADER_CAP_INT16: 454 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS: 455 return 0; 456 default: 457 return 0; 458 } 459 default: 460 return 0; 461 } 462} 463 464static float 465virgl_get_paramf(struct pipe_screen *screen, enum pipe_capf param) 466{ 467 struct virgl_screen *vscreen = virgl_screen(screen); 468 switch (param) { 469 case PIPE_CAPF_MIN_LINE_WIDTH: 470 case PIPE_CAPF_MIN_LINE_WIDTH_AA: 471 case PIPE_CAPF_MIN_POINT_SIZE: 472 case PIPE_CAPF_MIN_POINT_SIZE_AA: 473 return 1; 474 case PIPE_CAPF_POINT_SIZE_GRANULARITY: 475 case PIPE_CAPF_LINE_WIDTH_GRANULARITY: 476 return 0.1; 477 case PIPE_CAPF_MAX_LINE_WIDTH: 478 return vscreen->caps.caps.v2.max_aliased_line_width; 479 case PIPE_CAPF_MAX_LINE_WIDTH_AA: 480 return vscreen->caps.caps.v2.max_smooth_line_width; 481 case PIPE_CAPF_MAX_POINT_SIZE: 482 return vscreen->caps.caps.v2.max_aliased_point_size; 483 case PIPE_CAPF_MAX_POINT_SIZE_AA: 484 return vscreen->caps.caps.v2.max_smooth_point_size; 485 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY: 486 return vscreen->caps.caps.v2.max_anisotropy; 487 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: 488 return vscreen->caps.caps.v2.max_texture_lod_bias; 489 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE: 490 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE: 491 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY: 492 return 0.0f; 493 } 494 /* should only get here on unhandled cases */ 495 debug_printf("Unexpected PIPE_CAPF %d query\n", param); 496 return 0.0; 497} 498 499static int 500virgl_get_compute_param(struct pipe_screen *screen, 501 enum pipe_shader_ir ir_type, 502 enum pipe_compute_cap param, 503 void *ret) 504{ 505 struct virgl_screen *vscreen = virgl_screen(screen); 506 if (!(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER)) 507 return 0; 508 switch (param) { 509 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE: 510 if (ret) { 511 uint64_t *grid_size = ret; 512 grid_size[0] = vscreen->caps.caps.v2.max_compute_grid_size[0]; 513 grid_size[1] = vscreen->caps.caps.v2.max_compute_grid_size[1]; 514 grid_size[2] = vscreen->caps.caps.v2.max_compute_grid_size[2]; 515 } 516 return 3 * sizeof(uint64_t) ; 517 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE: 518 if (ret) { 519 uint64_t *block_size = ret; 520 block_size[0] = vscreen->caps.caps.v2.max_compute_block_size[0]; 521 block_size[1] = vscreen->caps.caps.v2.max_compute_block_size[1]; 522 block_size[2] = vscreen->caps.caps.v2.max_compute_block_size[2]; 523 } 524 return 3 * sizeof(uint64_t); 525 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK: 526 if (ret) { 527 uint64_t *max_threads_per_block = ret; 528 *max_threads_per_block = vscreen->caps.caps.v2.max_compute_work_group_invocations; 529 } 530 return sizeof(uint64_t); 531 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: 532 if (ret) { 533 uint64_t *max_local_size = ret; 534 /* Value reported by the closed source driver. */ 535 *max_local_size = vscreen->caps.caps.v2.max_compute_shared_memory_size; 536 } 537 return sizeof(uint64_t); 538 default: 539 break; 540 } 541 return 0; 542} 543 544static bool 545has_format_bit(struct virgl_supported_format_mask *mask, 546 enum virgl_formats fmt) 547{ 548 assert(fmt < VIRGL_FORMAT_MAX); 549 unsigned val = (unsigned)fmt; 550 unsigned idx = val / 32; 551 unsigned bit = val % 32; 552 assert(idx < ARRAY_SIZE(mask->bitmask)); 553 return (mask->bitmask[idx] & (1u << bit)) != 0; 554} 555 556bool 557virgl_has_readback_format(struct pipe_screen *screen, 558 enum virgl_formats fmt, bool allow_tweak) 559{ 560 struct virgl_screen *vscreen = virgl_screen(screen); 561 if (has_format_bit(&vscreen->caps.caps.v2.supported_readback_formats, 562 fmt)) 563 return true; 564 565 if (allow_tweak && fmt == VIRGL_FORMAT_L8_SRGB && vscreen->tweak_l8_srgb_readback) { 566 return true; 567 } 568 569 return false; 570} 571 572static bool 573virgl_is_vertex_format_supported(struct pipe_screen *screen, 574 enum pipe_format format) 575{ 576 struct virgl_screen *vscreen = virgl_screen(screen); 577 const struct util_format_description *format_desc; 578 int i; 579 580 format_desc = util_format_description(format); 581 582 if (format == PIPE_FORMAT_R11G11B10_FLOAT) { 583 int vformat = VIRGL_FORMAT_R11G11B10_FLOAT; 584 int big = vformat / 32; 585 int small = vformat % 32; 586 if (!(vscreen->caps.caps.v1.vertexbuffer.bitmask[big] & (1 << small))) 587 return false; 588 return true; 589 } 590 591 /* Find the first non-VOID channel. */ 592 for (i = 0; i < 4; i++) { 593 if (format_desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { 594 break; 595 } 596 } 597 598 if (i == 4) 599 return false; 600 601 if (format_desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) 602 return false; 603 604 if (format_desc->channel[i].type == UTIL_FORMAT_TYPE_FIXED) 605 return false; 606 return true; 607} 608 609static bool 610virgl_format_check_bitmask(enum pipe_format format, 611 uint32_t bitmask[16], 612 bool may_emulate_bgra) 613{ 614 enum virgl_formats vformat = pipe_to_virgl_format(format); 615 int big = vformat / 32; 616 int small = vformat % 32; 617 if ((bitmask[big] & (1 << small))) 618 return true; 619 620 /* On GLES hosts we don't advertise BGRx_SRGB, but we may be able 621 * emulate it by using a swizzled RGBx */ 622 if (may_emulate_bgra) { 623 if (format == PIPE_FORMAT_B8G8R8A8_SRGB) 624 format = PIPE_FORMAT_R8G8B8A8_SRGB; 625 else if (format == PIPE_FORMAT_B8G8R8X8_SRGB) 626 format = PIPE_FORMAT_R8G8B8X8_SRGB; 627 else { 628 return false; 629 } 630 631 vformat = pipe_to_virgl_format(format); 632 big = vformat / 32; 633 small = vformat % 32; 634 if (bitmask[big] & (1 << small)) 635 return true; 636 } 637 return false; 638} 639 640bool virgl_has_scanout_format(struct virgl_screen *vscreen, 641 enum pipe_format format, 642 bool may_emulate_bgra) 643{ 644 return virgl_format_check_bitmask(format, 645 vscreen->caps.caps.v2.scanout.bitmask, 646 may_emulate_bgra); 647} 648 649/** 650 * Query format support for creating a texture, drawing surface, etc. 651 * \param format the format to test 652 * \param type one of PIPE_TEXTURE, PIPE_SURFACE 653 */ 654static bool 655virgl_is_format_supported( struct pipe_screen *screen, 656 enum pipe_format format, 657 enum pipe_texture_target target, 658 unsigned sample_count, 659 unsigned storage_sample_count, 660 unsigned bind) 661{ 662 struct virgl_screen *vscreen = virgl_screen(screen); 663 const struct util_format_description *format_desc; 664 int i; 665 666 union virgl_caps *caps = &vscreen->caps.caps; 667 boolean may_emulate_bgra = (caps->v2.capability_bits & 668 VIRGL_CAP_APP_TWEAK_SUPPORT) && 669 vscreen->tweak_gles_emulate_bgra; 670 671 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count)) 672 return false; 673 674 if (!util_is_power_of_two_or_zero(sample_count)) 675 return false; 676 677 assert(target == PIPE_BUFFER || 678 target == PIPE_TEXTURE_1D || 679 target == PIPE_TEXTURE_1D_ARRAY || 680 target == PIPE_TEXTURE_2D || 681 target == PIPE_TEXTURE_2D_ARRAY || 682 target == PIPE_TEXTURE_RECT || 683 target == PIPE_TEXTURE_3D || 684 target == PIPE_TEXTURE_CUBE || 685 target == PIPE_TEXTURE_CUBE_ARRAY); 686 687 format_desc = util_format_description(format); 688 689 if (util_format_is_intensity(format)) 690 return false; 691 692 if (sample_count > 1) { 693 if (!caps->v1.bset.texture_multisample) 694 return false; 695 696 if (bind & PIPE_BIND_SHADER_IMAGE) { 697 if (sample_count > caps->v2.max_image_samples) 698 return false; 699 } 700 701 if (sample_count > caps->v1.max_samples) 702 return false; 703 704 if (caps->v2.host_feature_check_version >= 9 && 705 !has_format_bit(&caps->v2.supported_multisample_formats, 706 pipe_to_virgl_format(format))) 707 return false; 708 } 709 710 if (bind & PIPE_BIND_VERTEX_BUFFER) { 711 return virgl_is_vertex_format_supported(screen, format); 712 } 713 714 if (util_format_is_compressed(format) && target == PIPE_BUFFER) 715 return false; 716 717 /* Allow 3-comp 32 bit textures only for TBOs (needed for ARB_tbo_rgb32) */ 718 if ((format == PIPE_FORMAT_R32G32B32_FLOAT || 719 format == PIPE_FORMAT_R32G32B32_SINT || 720 format == PIPE_FORMAT_R32G32B32_UINT) && 721 target != PIPE_BUFFER) 722 return false; 723 724 if ((format_desc->layout == UTIL_FORMAT_LAYOUT_RGTC || 725 format_desc->layout == UTIL_FORMAT_LAYOUT_ETC || 726 format_desc->layout == UTIL_FORMAT_LAYOUT_S3TC) && 727 target == PIPE_TEXTURE_3D) 728 return false; 729 730 731 if (bind & PIPE_BIND_RENDER_TARGET) { 732 /* For ARB_framebuffer_no_attachments. */ 733 if (format == PIPE_FORMAT_NONE) 734 return TRUE; 735 736 if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) 737 return false; 738 739 /* 740 * Although possible, it is unnatural to render into compressed or YUV 741 * surfaces. So disable these here to avoid going into weird paths 742 * inside gallium frontends. 743 */ 744 if (format_desc->block.width != 1 || 745 format_desc->block.height != 1) 746 return false; 747 748 if (!virgl_format_check_bitmask(format, 749 caps->v1.render.bitmask, 750 may_emulate_bgra)) 751 return false; 752 } 753 754 if (bind & PIPE_BIND_DEPTH_STENCIL) { 755 if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS) 756 return false; 757 } 758 759 if (bind & PIPE_BIND_SCANOUT) { 760 if (!virgl_format_check_bitmask(format, caps->v2.scanout.bitmask, false)) 761 return false; 762 } 763 764 /* 765 * All other operations (sampling, transfer, etc). 766 */ 767 768 if (format_desc->layout == UTIL_FORMAT_LAYOUT_S3TC) { 769 goto out_lookup; 770 } 771 if (format_desc->layout == UTIL_FORMAT_LAYOUT_RGTC) { 772 goto out_lookup; 773 } 774 if (format_desc->layout == UTIL_FORMAT_LAYOUT_BPTC) { 775 goto out_lookup; 776 } 777 if (format_desc->layout == UTIL_FORMAT_LAYOUT_ETC) { 778 goto out_lookup; 779 } 780 781 if (format == PIPE_FORMAT_R11G11B10_FLOAT) { 782 goto out_lookup; 783 } else if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) { 784 goto out_lookup; 785 } 786 787 if (format_desc->layout == UTIL_FORMAT_LAYOUT_ASTC) { 788 goto out_lookup; 789 } 790 791 /* Find the first non-VOID channel. */ 792 for (i = 0; i < 4; i++) { 793 if (format_desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { 794 break; 795 } 796 } 797 798 if (i == 4) 799 return false; 800 801 /* no L4A4 */ 802 if (format_desc->nr_channels < 4 && format_desc->channel[i].size == 4) 803 return false; 804 805 out_lookup: 806 return virgl_format_check_bitmask(format, 807 caps->v1.sampler.bitmask, 808 may_emulate_bgra); 809} 810 811static void virgl_flush_frontbuffer(struct pipe_screen *screen, 812 struct pipe_context *ctx, 813 struct pipe_resource *res, 814 unsigned level, unsigned layer, 815 void *winsys_drawable_handle, struct pipe_box *sub_box) 816{ 817 struct virgl_screen *vscreen = virgl_screen(screen); 818 struct virgl_winsys *vws = vscreen->vws; 819 struct virgl_resource *vres = virgl_resource(res); 820 struct virgl_context *vctx = virgl_context(ctx); 821 822 if (vws->flush_frontbuffer) { 823 virgl_flush_eq(vctx, vctx, NULL); 824 vws->flush_frontbuffer(vws, vres->hw_res, level, layer, winsys_drawable_handle, 825 sub_box); 826 } 827} 828 829static void virgl_fence_reference(struct pipe_screen *screen, 830 struct pipe_fence_handle **ptr, 831 struct pipe_fence_handle *fence) 832{ 833 struct virgl_screen *vscreen = virgl_screen(screen); 834 struct virgl_winsys *vws = vscreen->vws; 835 836 vws->fence_reference(vws, ptr, fence); 837} 838 839static bool virgl_fence_finish(struct pipe_screen *screen, 840 struct pipe_context *ctx, 841 struct pipe_fence_handle *fence, 842 uint64_t timeout) 843{ 844 struct virgl_screen *vscreen = virgl_screen(screen); 845 struct virgl_winsys *vws = vscreen->vws; 846 struct virgl_context *vctx = virgl_context(ctx); 847 848 if (vctx && timeout) 849 virgl_flush_eq(vctx, NULL, NULL); 850 851 return vws->fence_wait(vws, fence, timeout); 852} 853 854static int virgl_fence_get_fd(struct pipe_screen *screen, 855 struct pipe_fence_handle *fence) 856{ 857 struct virgl_screen *vscreen = virgl_screen(screen); 858 struct virgl_winsys *vws = vscreen->vws; 859 860 return vws->fence_get_fd(vws, fence); 861} 862 863static uint64_t 864virgl_get_timestamp(struct pipe_screen *_screen) 865{ 866 return os_time_get_nano(); 867} 868 869static void 870virgl_destroy_screen(struct pipe_screen *screen) 871{ 872 struct virgl_screen *vscreen = virgl_screen(screen); 873 struct virgl_winsys *vws = vscreen->vws; 874 875 slab_destroy_parent(&vscreen->transfer_pool); 876 877 if (vws) 878 vws->destroy(vws); 879 880 disk_cache_destroy(vscreen->disk_cache); 881 882 FREE(vscreen); 883} 884 885static void 886fixup_formats(union virgl_caps *caps, struct virgl_supported_format_mask *mask) 887{ 888 const size_t size = ARRAY_SIZE(mask->bitmask); 889 for (int i = 0; i < size; ++i) { 890 if (mask->bitmask[i] != 0) 891 return; /* we got some formats, we definitely have a new protocol */ 892 } 893 894 /* old protocol used; fall back to considering all sampleable formats valid 895 * readback-formats 896 */ 897 for (int i = 0; i < size; ++i) 898 mask->bitmask[i] = caps->v1.sampler.bitmask[i]; 899} 900 901static void virgl_query_memory_info(struct pipe_screen *screen, struct pipe_memory_info *info) 902{ 903 struct virgl_screen *vscreen = virgl_screen(screen); 904 struct pipe_context *ctx = screen->context_create(screen, NULL, 0); 905 struct virgl_context *vctx = virgl_context(ctx); 906 struct virgl_resource *res; 907 struct virgl_memory_info virgl_info = {0}; 908 const static struct pipe_resource templ = { 909 .target = PIPE_BUFFER, 910 .format = PIPE_FORMAT_R8_UNORM, 911 .bind = PIPE_BIND_CUSTOM, 912 .width0 = sizeof(struct virgl_memory_info), 913 .height0 = 1, 914 .depth0 = 1, 915 .array_size = 1, 916 .last_level = 0, 917 .nr_samples = 0, 918 .flags = 0 919 }; 920 921 res = (struct virgl_resource*) screen->resource_create(screen, &templ); 922 923 virgl_encode_get_memory_info(vctx, res); 924 ctx->flush(ctx, NULL, 0); 925 vscreen->vws->resource_wait(vscreen->vws, res->hw_res); 926 pipe_buffer_read(ctx, &res->b, 0, sizeof(struct virgl_memory_info), &virgl_info); 927 928 info->avail_device_memory = virgl_info.avail_device_memory; 929 info->avail_staging_memory = virgl_info.avail_staging_memory; 930 info->device_memory_evicted = virgl_info.device_memory_evicted; 931 info->nr_device_memory_evictions = virgl_info.nr_device_memory_evictions; 932 info->total_device_memory = virgl_info.total_device_memory; 933 info->total_staging_memory = virgl_info.total_staging_memory; 934 935 screen->resource_destroy(screen, &res->b); 936 ctx->destroy(ctx); 937} 938 939static struct disk_cache *virgl_get_disk_shader_cache (struct pipe_screen *pscreen) 940{ 941 struct virgl_screen *screen = virgl_screen(pscreen); 942 943 return screen->disk_cache; 944} 945 946static void virgl_disk_cache_create(struct virgl_screen *screen) 947{ 948 const struct build_id_note *note = 949 build_id_find_nhdr_for_addr(virgl_disk_cache_create); 950 unsigned build_id_len = build_id_length(note); 951 assert(note && build_id_len == 20); /* sha1 */ 952 953 const uint8_t *id_sha1 = build_id_data(note); 954 assert(id_sha1); 955 956 struct mesa_sha1 sha1_ctx; 957 _mesa_sha1_init(&sha1_ctx); 958 _mesa_sha1_update(&sha1_ctx, id_sha1, build_id_len); 959 960 uint32_t shader_debug_flags = virgl_debug & VIRGL_DEBUG_USE_TGSI; 961 _mesa_sha1_update(&sha1_ctx, &shader_debug_flags, sizeof(shader_debug_flags)); 962 963 /* When we switch the host the caps might change and then we might have to 964 * apply different lowering. */ 965 _mesa_sha1_update(&sha1_ctx, &screen->caps, sizeof(screen->caps)); 966 967 uint8_t sha1[20]; 968 _mesa_sha1_final(&sha1_ctx, sha1); 969 char timestamp[41]; 970 _mesa_sha1_format(timestamp, sha1); 971 972 screen->disk_cache = disk_cache_create("virgl", timestamp, 0); 973} 974 975static bool 976virgl_is_dmabuf_modifier_supported(UNUSED struct pipe_screen *pscreen, 977 UNUSED uint64_t modifier, 978 UNUSED enum pipe_format format, 979 UNUSED bool *external_only) 980{ 981 /* Always advertise support until virgl starts checking against host 982 * virglrenderer or consuming valid non-linear modifiers here. 983 */ 984 return true; 985} 986 987static unsigned int 988virgl_get_dmabuf_modifier_planes(UNUSED struct pipe_screen *pscreen, 989 UNUSED uint64_t modifier, 990 enum pipe_format format) 991{ 992 /* Return the format plane count queried from pipe_format. For virgl, 993 * additional aux planes are entirely resolved on the host side. 994 */ 995 return util_format_get_num_planes(format); 996} 997 998static void 999fixup_renderer(union virgl_caps *caps) 1000{ 1001 if (caps->v2.host_feature_check_version < 5) 1002 return; 1003 1004 char renderer[64]; 1005 int renderer_len = snprintf(renderer, sizeof(renderer), "virgl (%s)", 1006 caps->v2.renderer); 1007 if (renderer_len >= 64) { 1008 memcpy(renderer + 59, "...)", 4); 1009 renderer_len = 63; 1010 } 1011 memcpy(caps->v2.renderer, renderer, renderer_len + 1); 1012} 1013 1014static const void * 1015virgl_get_compiler_options(struct pipe_screen *pscreen, 1016 enum pipe_shader_ir ir, 1017 unsigned shader) 1018{ 1019 struct virgl_screen *vscreen = virgl_screen(pscreen); 1020 1021 return &vscreen->compiler_options; 1022} 1023 1024struct pipe_screen * 1025virgl_create_screen(struct virgl_winsys *vws, const struct pipe_screen_config *config) 1026{ 1027 struct virgl_screen *screen = CALLOC_STRUCT(virgl_screen); 1028 1029 const char *VIRGL_GLES_EMULATE_BGRA = "gles_emulate_bgra"; 1030 const char *VIRGL_GLES_APPLY_BGRA_DEST_SWIZZLE = "gles_apply_bgra_dest_swizzle"; 1031 const char *VIRGL_GLES_SAMPLES_PASSED_VALUE = "gles_samples_passed_value"; 1032 const char *VIRGL_FORMAT_L8_SRGB_ENABLE_READBACK = "format_l8_srgb_enable_readback"; 1033 1034 if (!screen) 1035 return NULL; 1036 1037 virgl_debug = debug_get_option_virgl_debug(); 1038 1039 if (config && config->options) { 1040 driParseConfigFiles(config->options, config->options_info, 0, "virtio_gpu", 1041 NULL, NULL, NULL, 0, NULL, 0); 1042 1043 screen->tweak_gles_emulate_bgra = 1044 driQueryOptionb(config->options, VIRGL_GLES_EMULATE_BGRA); 1045 screen->tweak_gles_apply_bgra_dest_swizzle = 1046 driQueryOptionb(config->options, VIRGL_GLES_APPLY_BGRA_DEST_SWIZZLE); 1047 screen->tweak_gles_tf3_value = 1048 driQueryOptioni(config->options, VIRGL_GLES_SAMPLES_PASSED_VALUE); 1049 screen->tweak_l8_srgb_readback = 1050 driQueryOptionb(config->options, VIRGL_FORMAT_L8_SRGB_ENABLE_READBACK); 1051 } 1052 screen->tweak_gles_emulate_bgra &= !(virgl_debug & VIRGL_DEBUG_NO_EMULATE_BGRA); 1053 screen->tweak_gles_apply_bgra_dest_swizzle &= !(virgl_debug & VIRGL_DEBUG_NO_BGRA_DEST_SWIZZLE); 1054 screen->no_coherent = virgl_debug & VIRGL_DEBUG_NO_COHERENT; 1055 screen->tweak_l8_srgb_readback |= !!(virgl_debug & VIRGL_DEBUG_L8_SRGB_ENABLE_READBACK); 1056 1057 screen->vws = vws; 1058 screen->base.get_name = virgl_get_name; 1059 screen->base.get_vendor = virgl_get_vendor; 1060 screen->base.get_param = virgl_get_param; 1061 screen->base.get_shader_param = virgl_get_shader_param; 1062 screen->base.get_compute_param = virgl_get_compute_param; 1063 screen->base.get_paramf = virgl_get_paramf; 1064 screen->base.get_compiler_options = virgl_get_compiler_options; 1065 screen->base.is_format_supported = virgl_is_format_supported; 1066 screen->base.destroy = virgl_destroy_screen; 1067 screen->base.context_create = virgl_context_create; 1068 screen->base.flush_frontbuffer = virgl_flush_frontbuffer; 1069 screen->base.get_timestamp = virgl_get_timestamp; 1070 screen->base.fence_reference = virgl_fence_reference; 1071 //screen->base.fence_signalled = virgl_fence_signalled; 1072 screen->base.fence_finish = virgl_fence_finish; 1073 screen->base.fence_get_fd = virgl_fence_get_fd; 1074 screen->base.query_memory_info = virgl_query_memory_info; 1075 screen->base.get_disk_shader_cache = virgl_get_disk_shader_cache; 1076 screen->base.is_dmabuf_modifier_supported = virgl_is_dmabuf_modifier_supported; 1077 screen->base.get_dmabuf_modifier_planes = virgl_get_dmabuf_modifier_planes; 1078 1079 virgl_init_screen_resource_functions(&screen->base); 1080 1081 vws->get_caps(vws, &screen->caps); 1082 fixup_formats(&screen->caps.caps, 1083 &screen->caps.caps.v2.supported_readback_formats); 1084 fixup_formats(&screen->caps.caps, &screen->caps.caps.v2.scanout); 1085 fixup_renderer(&screen->caps.caps); 1086 1087 union virgl_caps *caps = &screen->caps.caps; 1088 screen->tweak_gles_emulate_bgra &= !virgl_format_check_bitmask(PIPE_FORMAT_B8G8R8A8_SRGB, caps->v1.render.bitmask, false); 1089 screen->refcnt = 1; 1090 1091 /* Set up the NIR shader compiler options now that we've figured out the caps. */ 1092 screen->compiler_options = *(nir_shader_compiler_options *) 1093 nir_to_tgsi_get_compiler_options(&screen->base, PIPE_SHADER_IR_NIR, PIPE_SHADER_FRAGMENT); 1094 if (virgl_get_param(&screen->base, PIPE_CAP_DOUBLES)) { 1095 /* virglrenderer is missing DFLR support, so avoid turning 64-bit 1096 * ffract+fsub back into ffloor. 1097 */ 1098 screen->compiler_options.lower_ffloor = true; 1099 screen->compiler_options.lower_fneg = true; 1100 } 1101 1102 slab_create_parent(&screen->transfer_pool, sizeof(struct virgl_transfer), 16); 1103 1104 virgl_disk_cache_create(screen); 1105 return &screen->base; 1106} 1107