1/********************************************************** 2 * Copyright 2008-2009 VMware, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person 5 * obtaining a copy of this software and associated documentation 6 * files (the "Software"), to deal in the Software without 7 * restriction, including without limitation the rights to use, copy, 8 * modify, merge, publish, distribute, sublicense, and/or sell copies 9 * of the Software, and to permit persons to whom the Software is 10 * furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be 13 * included in all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 * 24 **********************************************************/ 25 26#include "git_sha1.h" /* For MESA_GIT_SHA1 */ 27#include "compiler/nir/nir.h" 28#include "util/format/u_format.h" 29#include "util/u_memory.h" 30#include "util/u_inlines.h" 31#include "util/u_screen.h" 32#include "util/u_string.h" 33#include "util/u_math.h" 34 35#include "os/os_process.h" 36 37#include "svga_winsys.h" 38#include "svga_public.h" 39#include "svga_context.h" 40#include "svga_format.h" 41#include "svga_screen.h" 42#include "svga_tgsi.h" 43#include "svga_resource_texture.h" 44#include "svga_resource.h" 45#include "svga_debug.h" 46 47#include "svga3d_shaderdefs.h" 48#include "VGPU10ShaderTokens.h" 49 50/* NOTE: this constant may get moved into a svga3d*.h header file */ 51#define SVGA3D_DX_MAX_RESOURCE_SIZE (128 * 1024 * 1024) 52 53#ifndef MESA_GIT_SHA1 54#define MESA_GIT_SHA1 "(unknown git revision)" 55#endif 56 57#ifdef DEBUG 58int SVGA_DEBUG = 0; 59 60static const struct debug_named_value svga_debug_flags[] = { 61 { "dma", DEBUG_DMA, NULL }, 62 { "tgsi", DEBUG_TGSI, NULL }, 63 { "pipe", DEBUG_PIPE, NULL }, 64 { "state", DEBUG_STATE, NULL }, 65 { "screen", DEBUG_SCREEN, NULL }, 66 { "tex", DEBUG_TEX, NULL }, 67 { "swtnl", DEBUG_SWTNL, NULL }, 68 { "const", DEBUG_CONSTS, NULL }, 69 { "viewport", DEBUG_VIEWPORT, NULL }, 70 { "views", DEBUG_VIEWS, NULL }, 71 { "perf", DEBUG_PERF, NULL }, 72 { "flush", DEBUG_FLUSH, NULL }, 73 { "sync", DEBUG_SYNC, NULL }, 74 { "cache", DEBUG_CACHE, NULL }, 75 { "streamout", DEBUG_STREAMOUT, NULL }, 76 { "query", DEBUG_QUERY, NULL }, 77 { "samplers", DEBUG_SAMPLERS, NULL }, 78 { "image", DEBUG_IMAGE, NULL }, 79 { "uav", DEBUG_UAV, NULL }, 80 { "retry", DEBUG_RETRY, NULL }, 81 DEBUG_NAMED_VALUE_END 82}; 83#endif 84 85static const char * 86svga_get_vendor( struct pipe_screen *pscreen ) 87{ 88 return "VMware, Inc."; 89} 90 91 92static const char * 93svga_get_name( struct pipe_screen *pscreen ) 94{ 95 const char *build = "", *llvm = "", *mutex = ""; 96 static char name[100]; 97#ifdef DEBUG 98 /* Only return internal details in the DEBUG version: 99 */ 100 build = "build: DEBUG;"; 101 mutex = "mutex: " PIPE_ATOMIC ";"; 102#else 103 build = "build: RELEASE;"; 104#endif 105#ifdef DRAW_LLVM_AVAILABLE 106 llvm = "LLVM;"; 107#endif 108 109 snprintf(name, sizeof(name), "SVGA3D; %s %s %s", build, mutex, llvm); 110 return name; 111} 112 113 114/** Helper for querying float-valued device cap */ 115static float 116get_float_cap(struct svga_winsys_screen *sws, SVGA3dDevCapIndex cap, 117 float defaultVal) 118{ 119 SVGA3dDevCapResult result; 120 if (sws->get_cap(sws, cap, &result)) 121 return result.f; 122 else 123 return defaultVal; 124} 125 126 127/** Helper for querying uint-valued device cap */ 128static unsigned 129get_uint_cap(struct svga_winsys_screen *sws, SVGA3dDevCapIndex cap, 130 unsigned defaultVal) 131{ 132 SVGA3dDevCapResult result; 133 if (sws->get_cap(sws, cap, &result)) 134 return result.u; 135 else 136 return defaultVal; 137} 138 139 140/** Helper for querying boolean-valued device cap */ 141static boolean 142get_bool_cap(struct svga_winsys_screen *sws, SVGA3dDevCapIndex cap, 143 boolean defaultVal) 144{ 145 SVGA3dDevCapResult result; 146 if (sws->get_cap(sws, cap, &result)) 147 return result.b; 148 else 149 return defaultVal; 150} 151 152 153static float 154svga_get_paramf(struct pipe_screen *screen, enum pipe_capf param) 155{ 156 struct svga_screen *svgascreen = svga_screen(screen); 157 struct svga_winsys_screen *sws = svgascreen->sws; 158 159 switch (param) { 160 case PIPE_CAPF_MIN_LINE_WIDTH: 161 case PIPE_CAPF_MIN_LINE_WIDTH_AA: 162 case PIPE_CAPF_MIN_POINT_SIZE: 163 case PIPE_CAPF_MIN_POINT_SIZE_AA: 164 return 1; 165 case PIPE_CAPF_POINT_SIZE_GRANULARITY: 166 case PIPE_CAPF_LINE_WIDTH_GRANULARITY: 167 return 0.1; 168 case PIPE_CAPF_MAX_LINE_WIDTH: 169 return svgascreen->maxLineWidth; 170 case PIPE_CAPF_MAX_LINE_WIDTH_AA: 171 return svgascreen->maxLineWidthAA; 172 173 case PIPE_CAPF_MAX_POINT_SIZE: 174 FALLTHROUGH; 175 case PIPE_CAPF_MAX_POINT_SIZE_AA: 176 return svgascreen->maxPointSize; 177 178 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY: 179 return (float) get_uint_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY, 4); 180 181 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: 182 return 15.0; 183 184 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE: 185 FALLTHROUGH; 186 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE: 187 FALLTHROUGH; 188 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY: 189 return 0.0f; 190 191 } 192 193 debug_printf("Unexpected PIPE_CAPF_ query %u\n", param); 194 return 0; 195} 196 197 198static int 199svga_get_param(struct pipe_screen *screen, enum pipe_cap param) 200{ 201 struct svga_screen *svgascreen = svga_screen(screen); 202 struct svga_winsys_screen *sws = svgascreen->sws; 203 SVGA3dDevCapResult result; 204 205 switch (param) { 206 case PIPE_CAP_NPOT_TEXTURES: 207 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: 208 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS: 209 return 1; 210 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: 211 /* 212 * "In virtually every OpenGL implementation and hardware, 213 * GL_MAX_DUAL_SOURCE_DRAW_BUFFERS is 1" 214 * http://www.opengl.org/wiki/Blending 215 */ 216 return sws->have_vgpu10 ? 1 : 0; 217 case PIPE_CAP_ANISOTROPIC_FILTER: 218 return 1; 219 case PIPE_CAP_POINT_SPRITE: 220 return 1; 221 case PIPE_CAP_MAX_RENDER_TARGETS: 222 return svgascreen->max_color_buffers; 223 case PIPE_CAP_OCCLUSION_QUERY: 224 return 1; 225 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS: 226 return sws->have_vgpu10; 227 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: 228 return sws->have_vgpu10 ? 16 : 0; 229 230 case PIPE_CAP_TEXTURE_SWIZZLE: 231 return 1; 232 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: 233 return 256; 234 235 case PIPE_CAP_MAX_TEXTURE_2D_SIZE: 236 { 237 unsigned size = 1 << (SVGA_MAX_TEXTURE_LEVELS - 1); 238 if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH, &result)) 239 size = MIN2(result.u, size); 240 else 241 size = 2048; 242 if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT, &result)) 243 size = MIN2(result.u, size); 244 else 245 size = 2048; 246 return size; 247 } 248 249 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: 250 if (!sws->get_cap(sws, SVGA3D_DEVCAP_MAX_VOLUME_EXTENT, &result)) 251 return 8; /* max 128x128x128 */ 252 return MIN2(util_logbase2(result.u) + 1, SVGA_MAX_TEXTURE_LEVELS); 253 254 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: 255 /* 256 * No mechanism to query the host, and at least limited to 2048x2048 on 257 * certain hardware. 258 */ 259 return MIN2(util_last_bit(screen->get_param(screen, PIPE_CAP_MAX_TEXTURE_2D_SIZE)), 260 12 /* 2048x2048 */); 261 262 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: 263 return sws->have_sm5 ? SVGA3D_SM5_MAX_SURFACE_ARRAYSIZE : 264 (sws->have_vgpu10 ? SVGA3D_SM4_MAX_SURFACE_ARRAYSIZE : 0); 265 266 case PIPE_CAP_BLEND_EQUATION_SEPARATE: /* req. for GL 1.5 */ 267 return 1; 268 269 case PIPE_CAP_FS_COORD_ORIGIN_UPPER_LEFT: 270 return 1; 271 case PIPE_CAP_FS_COORD_PIXEL_CENTER_HALF_INTEGER: 272 return sws->have_vgpu10; 273 case PIPE_CAP_FS_COORD_PIXEL_CENTER_INTEGER: 274 return !sws->have_vgpu10; 275 276 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: 277 return 1; /* The color outputs of vertex shaders are not clamped */ 278 case PIPE_CAP_VERTEX_COLOR_CLAMPED: 279 return sws->have_vgpu10; 280 281 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: 282 return 1; /* expected for GL_ARB_framebuffer_object */ 283 284 case PIPE_CAP_GLSL_FEATURE_LEVEL: 285 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY: 286 if (sws->have_gl43) { 287 return 430; 288 } else if (sws->have_sm5) { 289 return 410; 290 } else if (sws->have_vgpu10) { 291 return 330; 292 } else { 293 return 120; 294 } 295 296 case PIPE_CAP_TEXTURE_TRANSFER_MODES: 297 return 0; 298 299 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD: 300 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES: 301 return 1; 302 303 case PIPE_CAP_DEPTH_CLIP_DISABLE: 304 case PIPE_CAP_INDEP_BLEND_ENABLE: 305 case PIPE_CAP_CONDITIONAL_RENDER: 306 case PIPE_CAP_QUERY_TIMESTAMP: 307 case PIPE_CAP_VS_INSTANCEID: 308 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: 309 case PIPE_CAP_SEAMLESS_CUBE_MAP: 310 case PIPE_CAP_FAKE_SW_MSAA: 311 return sws->have_vgpu10; 312 313 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: 314 return sws->have_vgpu10 ? SVGA3D_DX_MAX_SOTARGETS : 0; 315 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: 316 return sws->have_vgpu10 ? 4 : 0; 317 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: 318 return sws->have_sm5 ? SVGA3D_MAX_STREAMOUT_DECLS : 319 (sws->have_vgpu10 ? SVGA3D_MAX_DX10_STREAMOUT_DECLS : 0); 320 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME: 321 return sws->have_sm5; 322 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS: 323 return sws->have_sm5; 324 case PIPE_CAP_TEXTURE_MULTISAMPLE: 325 return svgascreen->ms_samples ? 1 : 0; 326 327 case PIPE_CAP_MAX_TEXEL_BUFFER_ELEMENTS_UINT: 328 /* convert bytes to texels for the case of the largest texel 329 * size: float[4]. 330 */ 331 return SVGA3D_DX_MAX_RESOURCE_SIZE / (4 * sizeof(float)); 332 333 case PIPE_CAP_MIN_TEXEL_OFFSET: 334 return sws->have_vgpu10 ? VGPU10_MIN_TEXEL_FETCH_OFFSET : 0; 335 case PIPE_CAP_MAX_TEXEL_OFFSET: 336 return sws->have_vgpu10 ? VGPU10_MAX_TEXEL_FETCH_OFFSET : 0; 337 338 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET: 339 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET: 340 return 0; 341 342 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES: 343 return sws->have_vgpu10 ? 256 : 0; 344 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS: 345 return sws->have_vgpu10 ? 1024 : 0; 346 347 case PIPE_CAP_PRIMITIVE_RESTART: 348 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX: 349 return 1; /* may be a sw fallback, depending on restart index */ 350 351 case PIPE_CAP_GENERATE_MIPMAP: 352 return sws->have_generate_mipmap_cmd; 353 354 case PIPE_CAP_NATIVE_FENCE_FD: 355 return sws->have_fence_fd; 356 357 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION: 358 return 1; 359 360 case PIPE_CAP_CUBE_MAP_ARRAY: 361 case PIPE_CAP_INDEP_BLEND_FUNC: 362 case PIPE_CAP_SAMPLE_SHADING: 363 case PIPE_CAP_FORCE_PERSAMPLE_INTERP: 364 case PIPE_CAP_TEXTURE_QUERY_LOD: 365 return sws->have_sm4_1; 366 367 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS: 368 /* SM4_1 supports only single-channel textures where as SM5 supports 369 * all four channel textures */ 370 return sws->have_sm5 ? 4 : 371 (sws->have_sm4_1 ? 1 : 0); 372 case PIPE_CAP_DRAW_INDIRECT: 373 return sws->have_sm5; 374 case PIPE_CAP_MAX_VERTEX_STREAMS: 375 return sws->have_sm5 ? 4 : 0; 376 case PIPE_CAP_COMPUTE: 377 return sws->have_gl43; 378 case PIPE_CAP_MAX_VARYINGS: 379 /* According to the spec, max varyings does not include the components 380 * for position, so remove one count from the max for position. 381 */ 382 return sws->have_vgpu10 ? VGPU10_MAX_FS_INPUTS-1 : 10; 383 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT: 384 return sws->have_coherent; 385 386 case PIPE_CAP_START_INSTANCE: 387 return sws->have_sm5; 388 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR: 389 return sws->have_sm5; 390 391 case PIPE_CAP_SAMPLER_VIEW_TARGET: 392 return sws->have_gl43; 393 394 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT: 395 return sws->have_gl43; 396 397 case PIPE_CAP_CLIP_HALFZ: 398 return sws->have_gl43; 399 case PIPE_CAP_SHAREABLE_SHADERS: 400 return 0; 401 402 case PIPE_CAP_PCI_GROUP: 403 case PIPE_CAP_PCI_BUS: 404 case PIPE_CAP_PCI_DEVICE: 405 case PIPE_CAP_PCI_FUNCTION: 406 return 0; 407 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT: 408 return sws->have_gl43 ? 16 : 0; 409 410 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES: 411 case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS: 412 return sws->have_gl43 ? SVGA_MAX_SHADER_BUFFERS : 0; 413 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS: 414 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS: 415 return sws->have_gl43 ? SVGA_MAX_ATOMIC_BUFFERS : 0; 416 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT: 417 return 64; 418 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: 419 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: 420 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: 421 return 1; /* need 4-byte alignment for all offsets and strides */ 422 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE: 423 return 2048; 424 case PIPE_CAP_MAX_VIEWPORTS: 425 assert((!sws->have_vgpu10 && svgascreen->max_viewports == 1) || 426 (sws->have_vgpu10 && 427 svgascreen->max_viewports == SVGA3D_DX_MAX_VIEWPORTS)); 428 return svgascreen->max_viewports; 429 case PIPE_CAP_ENDIANNESS: 430 return PIPE_ENDIAN_LITTLE; 431 432 case PIPE_CAP_VENDOR_ID: 433 return 0x15ad; /* VMware Inc. */ 434 case PIPE_CAP_DEVICE_ID: 435 if (sws->device_id) { 436 return sws->device_id; 437 } else { 438 return 0x0405; /* assume SVGA II */ 439 } 440 case PIPE_CAP_ACCELERATED: 441 return 0; /* XXX: */ 442 case PIPE_CAP_VIDEO_MEMORY: 443 /* XXX: Query the host ? */ 444 return 1; 445 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS: 446 return sws->have_vgpu10; 447 case PIPE_CAP_CLEAR_TEXTURE: 448 return sws->have_vgpu10; 449 case PIPE_CAP_DOUBLES: 450 return sws->have_sm5; 451 case PIPE_CAP_UMA: 452 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION: 453 return 0; 454 case PIPE_CAP_TGSI_DIV: 455 return 1; 456 case PIPE_CAP_MAX_GS_INVOCATIONS: 457 return 32; 458 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT: 459 return 1 << 27; 460 /* Verify this once protocol is finalized. Setting it to minimum value. */ 461 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS: 462 return sws->have_sm5 ? 30 : 0; 463 case PIPE_CAP_TEXTURE_FLOAT_LINEAR: 464 return 1; 465 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR: 466 return 1; 467 case PIPE_CAP_TGSI_TEXCOORD: 468 return sws->have_vgpu10 ? 1 : 0; 469 case PIPE_CAP_IMAGE_STORE_FORMATTED: 470 return sws->have_gl43; 471 default: 472 return u_pipe_screen_get_param_defaults(screen, param); 473 } 474} 475 476 477static int 478vgpu9_get_shader_param(struct pipe_screen *screen, 479 enum pipe_shader_type shader, 480 enum pipe_shader_cap param) 481{ 482 struct svga_screen *svgascreen = svga_screen(screen); 483 struct svga_winsys_screen *sws = svgascreen->sws; 484 unsigned val; 485 486 assert(!sws->have_vgpu10); 487 488 switch (shader) 489 { 490 case PIPE_SHADER_FRAGMENT: 491 switch (param) 492 { 493 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: 494 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: 495 return get_uint_cap(sws, 496 SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS, 497 512); 498 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: 499 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: 500 return 512; 501 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: 502 return SVGA3D_MAX_NESTING_LEVEL; 503 case PIPE_SHADER_CAP_MAX_INPUTS: 504 return 10; 505 case PIPE_SHADER_CAP_MAX_OUTPUTS: 506 return svgascreen->max_color_buffers; 507 case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE: 508 return 224 * sizeof(float[4]); 509 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: 510 return 1; 511 case PIPE_SHADER_CAP_MAX_TEMPS: 512 val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS, 32); 513 return MIN2(val, SVGA3D_TEMPREG_MAX); 514 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: 515 /* 516 * Although PS 3.0 has some addressing abilities it can only represent 517 * loops that can be statically determined and unrolled. Given we can 518 * only handle a subset of the cases that the gallium frontend already 519 * does it is better to defer loop unrolling to the gallium frontend. 520 */ 521 return 0; 522 case PIPE_SHADER_CAP_CONT_SUPPORTED: 523 return 0; 524 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: 525 return 0; 526 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: 527 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: 528 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: 529 return 0; 530 case PIPE_SHADER_CAP_SUBROUTINES: 531 return 0; 532 case PIPE_SHADER_CAP_INT64_ATOMICS: 533 case PIPE_SHADER_CAP_INTEGERS: 534 return 0; 535 case PIPE_SHADER_CAP_FP16: 536 case PIPE_SHADER_CAP_FP16_DERIVATIVES: 537 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS: 538 case PIPE_SHADER_CAP_INT16: 539 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS: 540 return 0; 541 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: 542 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: 543 return 16; 544 case PIPE_SHADER_CAP_PREFERRED_IR: 545 return svgascreen->debug.nir ? PIPE_SHADER_IR_NIR : PIPE_SHADER_IR_TGSI; 546 case PIPE_SHADER_CAP_SUPPORTED_IRS: 547 return (1 << PIPE_SHADER_IR_TGSI) | (svgascreen->debug.nir ? (1 << PIPE_SHADER_IR_NIR) : 0); 548 case PIPE_SHADER_CAP_DROUND_SUPPORTED: 549 case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED: 550 case PIPE_SHADER_CAP_LDEXP_SUPPORTED: 551 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: 552 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: 553 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: 554 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: 555 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: 556 return 0; 557 } 558 /* If we get here, we failed to handle a cap above */ 559 debug_printf("Unexpected fragment shader query %u\n", param); 560 return 0; 561 case PIPE_SHADER_VERTEX: 562 switch (param) 563 { 564 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: 565 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: 566 return get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS, 567 512); 568 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: 569 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: 570 /* XXX: until we have vertex texture support */ 571 return 0; 572 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: 573 return SVGA3D_MAX_NESTING_LEVEL; 574 case PIPE_SHADER_CAP_MAX_INPUTS: 575 return 16; 576 case PIPE_SHADER_CAP_MAX_OUTPUTS: 577 return 10; 578 case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE: 579 return 256 * sizeof(float[4]); 580 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: 581 return 1; 582 case PIPE_SHADER_CAP_MAX_TEMPS: 583 val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS, 32); 584 return MIN2(val, SVGA3D_TEMPREG_MAX); 585 case PIPE_SHADER_CAP_CONT_SUPPORTED: 586 return 0; 587 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: 588 return 0; 589 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: 590 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: 591 return 1; 592 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: 593 return 0; 594 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: 595 return 1; 596 case PIPE_SHADER_CAP_SUBROUTINES: 597 return 0; 598 case PIPE_SHADER_CAP_INT64_ATOMICS: 599 case PIPE_SHADER_CAP_INTEGERS: 600 return 0; 601 case PIPE_SHADER_CAP_FP16: 602 case PIPE_SHADER_CAP_FP16_DERIVATIVES: 603 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS: 604 case PIPE_SHADER_CAP_INT16: 605 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS: 606 return 0; 607 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: 608 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: 609 return 0; 610 case PIPE_SHADER_CAP_PREFERRED_IR: 611 return svgascreen->debug.nir ? PIPE_SHADER_IR_NIR : PIPE_SHADER_IR_TGSI; 612 case PIPE_SHADER_CAP_SUPPORTED_IRS: 613 return (1 << PIPE_SHADER_IR_TGSI) | (svgascreen->debug.nir ? (1 << PIPE_SHADER_IR_NIR) : 0); 614 case PIPE_SHADER_CAP_DROUND_SUPPORTED: 615 case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED: 616 case PIPE_SHADER_CAP_LDEXP_SUPPORTED: 617 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: 618 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: 619 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: 620 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: 621 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: 622 return 0; 623 } 624 /* If we get here, we failed to handle a cap above */ 625 debug_printf("Unexpected vertex shader query %u\n", param); 626 return 0; 627 case PIPE_SHADER_GEOMETRY: 628 case PIPE_SHADER_COMPUTE: 629 case PIPE_SHADER_TESS_CTRL: 630 case PIPE_SHADER_TESS_EVAL: 631 /* no support for geometry, tess or compute shaders at this time */ 632 return 0; 633 default: 634 debug_printf("Unexpected shader type (%u) query\n", shader); 635 return 0; 636 } 637 return 0; 638} 639 640 641static int 642vgpu10_get_shader_param(struct pipe_screen *screen, 643 enum pipe_shader_type shader, 644 enum pipe_shader_cap param) 645{ 646 struct svga_screen *svgascreen = svga_screen(screen); 647 struct svga_winsys_screen *sws = svgascreen->sws; 648 649 assert(sws->have_vgpu10); 650 (void) sws; /* silence unused var warnings in non-debug builds */ 651 652 if ((!sws->have_sm5) && 653 (shader == PIPE_SHADER_TESS_CTRL || shader == PIPE_SHADER_TESS_EVAL)) 654 return 0; 655 656 if ((!sws->have_gl43) && (shader == PIPE_SHADER_COMPUTE)) 657 return 0; 658 659 /* NOTE: we do not query the device for any caps/limits at this time */ 660 661 /* Generally the same limits for vertex, geometry and fragment shaders */ 662 switch (param) { 663 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: 664 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: 665 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: 666 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: 667 return 64 * 1024; 668 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: 669 return 64; 670 case PIPE_SHADER_CAP_MAX_INPUTS: 671 if (shader == PIPE_SHADER_FRAGMENT) 672 return VGPU10_MAX_FS_INPUTS; 673 else if (shader == PIPE_SHADER_GEOMETRY) 674 return svgascreen->max_gs_inputs; 675 else if (shader == PIPE_SHADER_TESS_CTRL) 676 return VGPU11_MAX_HS_INPUT_CONTROL_POINTS; 677 else if (shader == PIPE_SHADER_TESS_EVAL) 678 return VGPU11_MAX_DS_INPUT_CONTROL_POINTS; 679 else 680 return svgascreen->max_vs_inputs; 681 case PIPE_SHADER_CAP_MAX_OUTPUTS: 682 if (shader == PIPE_SHADER_FRAGMENT) 683 return VGPU10_MAX_FS_OUTPUTS; 684 else if (shader == PIPE_SHADER_GEOMETRY) 685 return VGPU10_MAX_GS_OUTPUTS; 686 else if (shader == PIPE_SHADER_TESS_CTRL) 687 return VGPU11_MAX_HS_OUTPUTS; 688 else if (shader == PIPE_SHADER_TESS_EVAL) 689 return VGPU11_MAX_DS_OUTPUTS; 690 else 691 return svgascreen->max_vs_outputs; 692 693 case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE: 694 return VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT * sizeof(float[4]); 695 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: 696 return svgascreen->max_const_buffers; 697 case PIPE_SHADER_CAP_MAX_TEMPS: 698 return VGPU10_MAX_TEMPS; 699 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: 700 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: 701 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: 702 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: 703 return TRUE; /* XXX verify */ 704 case PIPE_SHADER_CAP_CONT_SUPPORTED: 705 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: 706 case PIPE_SHADER_CAP_SUBROUTINES: 707 case PIPE_SHADER_CAP_INTEGERS: 708 return TRUE; 709 case PIPE_SHADER_CAP_FP16: 710 case PIPE_SHADER_CAP_FP16_DERIVATIVES: 711 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS: 712 case PIPE_SHADER_CAP_INT16: 713 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS: 714 return FALSE; 715 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: 716 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: 717 return sws->have_gl43 ? PIPE_MAX_SAMPLERS : SVGA3D_DX_MAX_SAMPLERS; 718 case PIPE_SHADER_CAP_PREFERRED_IR: 719 return svgascreen->debug.nir ? PIPE_SHADER_IR_NIR : PIPE_SHADER_IR_TGSI; 720 case PIPE_SHADER_CAP_SUPPORTED_IRS: 721 if (sws->have_gl43) 722 return (1 << PIPE_SHADER_IR_TGSI) | (svgascreen->debug.nir ? (1 << PIPE_SHADER_IR_NIR) : 0); 723 else 724 return 0; 725 case PIPE_SHADER_CAP_DROUND_SUPPORTED: 726 case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED: 727 case PIPE_SHADER_CAP_LDEXP_SUPPORTED: 728 /* For the above cases, we rely on the GLSL compiler to translate/lower 729 * the TGIS instruction into other instructions we do support. 730 */ 731 return 0; 732 733 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: 734 return sws->have_gl43 ? SVGA_MAX_IMAGES : 0; 735 736 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: 737 return sws->have_gl43 ? SVGA_MAX_SHADER_BUFFERS : 0; 738 739 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: 740 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: 741 return sws->have_gl43 ? SVGA_MAX_ATOMIC_BUFFERS : 0; 742 743 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: 744 case PIPE_SHADER_CAP_INT64_ATOMICS: 745 return 0; 746 default: 747 debug_printf("Unexpected vgpu10 shader query %u\n", param); 748 return 0; 749 } 750 return 0; 751} 752 753#define COMMON_OPTIONS \ 754 .lower_extract_byte = true, \ 755 .lower_extract_word = true, \ 756 .lower_insert_byte = true, \ 757 .lower_insert_word = true, \ 758 .lower_int64_options = nir_lower_imul_2x32_64, \ 759 .lower_fdph = true, \ 760 .lower_flrp64 = true, \ 761 .lower_rotate = true, \ 762 .lower_uniforms_to_ubo = true, \ 763 .lower_vector_cmp = true, \ 764 .max_unroll_iterations = 32, \ 765 .use_interpolated_input_intrinsics = true 766 767#define VGPU10_OPTIONS \ 768 .lower_doubles_options = nir_lower_dfloor, \ 769 .lower_fmod = true, \ 770 .lower_fpow = true 771 772static const nir_shader_compiler_options svga_vgpu9_fragment_compiler_options = { 773 COMMON_OPTIONS, 774 .lower_bitops = true, 775 .force_indirect_unrolling = nir_var_all, 776 .force_indirect_unrolling_sampler = true, 777}; 778 779static const nir_shader_compiler_options svga_vgpu9_vertex_compiler_options = { 780 COMMON_OPTIONS, 781 .lower_bitops = true, 782 .force_indirect_unrolling = nir_var_function_temp, 783 .force_indirect_unrolling_sampler = true, 784}; 785 786static const nir_shader_compiler_options svga_vgpu10_compiler_options = { 787 COMMON_OPTIONS, 788 VGPU10_OPTIONS, 789 .force_indirect_unrolling_sampler = true, 790}; 791 792static const nir_shader_compiler_options svga_gl4_compiler_options = { 793 COMMON_OPTIONS, 794 VGPU10_OPTIONS, 795}; 796 797static const void * 798svga_get_compiler_options(struct pipe_screen *pscreen, 799 enum pipe_shader_ir ir, 800 enum pipe_shader_type shader) 801{ 802 struct svga_screen *svgascreen = svga_screen(pscreen); 803 struct svga_winsys_screen *sws = svgascreen->sws; 804 805 assert(ir == PIPE_SHADER_IR_NIR); 806 807 if (sws->have_gl43 || sws->have_sm5) 808 return &svga_gl4_compiler_options; 809 else if (sws->have_vgpu10) 810 return &svga_vgpu10_compiler_options; 811 else { 812 if (shader == PIPE_SHADER_FRAGMENT) 813 return &svga_vgpu9_fragment_compiler_options; 814 else 815 return &svga_vgpu9_vertex_compiler_options; 816 } 817} 818 819static int 820svga_get_shader_param(struct pipe_screen *screen, enum pipe_shader_type shader, 821 enum pipe_shader_cap param) 822{ 823 struct svga_screen *svgascreen = svga_screen(screen); 824 struct svga_winsys_screen *sws = svgascreen->sws; 825 if (sws->have_vgpu10) { 826 return vgpu10_get_shader_param(screen, shader, param); 827 } 828 else { 829 return vgpu9_get_shader_param(screen, shader, param); 830 } 831} 832 833 834static int 835svga_sm5_get_compute_param(struct pipe_screen *screen, 836 enum pipe_shader_ir ir_type, 837 enum pipe_compute_cap param, 838 void *ret) 839{ 840 ASSERTED struct svga_screen *svgascreen = svga_screen(screen); 841 ASSERTED struct svga_winsys_screen *sws = svgascreen->sws; 842 uint64_t *iret = (uint64_t *)ret; 843 844 assert(sws->have_gl43); 845 assert(ir_type == PIPE_SHADER_IR_TGSI); 846 847 switch (param) { 848 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE: 849 iret[0] = 65535; 850 iret[1] = 65535; 851 iret[2] = 65535; 852 return 3 * sizeof(uint64_t); 853 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE: 854 iret[0] = 1024; 855 iret[1] = 1024; 856 iret[2] = 64; 857 return 3 * sizeof(uint64_t); 858 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK: 859 *iret = 1024; 860 return sizeof(uint64_t); 861 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: 862 *iret = 32768; 863 return sizeof(uint64_t); 864 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK: 865 *iret = 0; 866 return sizeof(uint64_t); 867 default: 868 debug_printf("Unexpected compute param %u\n", param); 869 } 870 return 0; 871} 872 873static void 874svga_fence_reference(struct pipe_screen *screen, 875 struct pipe_fence_handle **ptr, 876 struct pipe_fence_handle *fence) 877{ 878 struct svga_winsys_screen *sws = svga_screen(screen)->sws; 879 sws->fence_reference(sws, ptr, fence); 880} 881 882 883static bool 884svga_fence_finish(struct pipe_screen *screen, 885 struct pipe_context *ctx, 886 struct pipe_fence_handle *fence, 887 uint64_t timeout) 888{ 889 struct svga_winsys_screen *sws = svga_screen(screen)->sws; 890 bool retVal; 891 892 SVGA_STATS_TIME_PUSH(sws, SVGA_STATS_TIME_FENCEFINISH); 893 894 if (!timeout) { 895 retVal = sws->fence_signalled(sws, fence, 0) == 0; 896 } 897 else { 898 SVGA_DBG(DEBUG_DMA|DEBUG_PERF, "%s fence_ptr %p\n", 899 __FUNCTION__, fence); 900 901 retVal = sws->fence_finish(sws, fence, timeout, 0) == 0; 902 } 903 904 SVGA_STATS_TIME_POP(sws); 905 906 return retVal; 907} 908 909 910static int 911svga_fence_get_fd(struct pipe_screen *screen, 912 struct pipe_fence_handle *fence) 913{ 914 struct svga_winsys_screen *sws = svga_screen(screen)->sws; 915 916 return sws->fence_get_fd(sws, fence, TRUE); 917} 918 919 920static int 921svga_get_driver_query_info(struct pipe_screen *screen, 922 unsigned index, 923 struct pipe_driver_query_info *info) 924{ 925#define QUERY(NAME, ENUM, UNITS) \ 926 {NAME, ENUM, {0}, UNITS, PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE, 0, 0x0} 927 928 static const struct pipe_driver_query_info queries[] = { 929 /* per-frame counters */ 930 QUERY("num-draw-calls", SVGA_QUERY_NUM_DRAW_CALLS, 931 PIPE_DRIVER_QUERY_TYPE_UINT64), 932 QUERY("num-fallbacks", SVGA_QUERY_NUM_FALLBACKS, 933 PIPE_DRIVER_QUERY_TYPE_UINT64), 934 QUERY("num-flushes", SVGA_QUERY_NUM_FLUSHES, 935 PIPE_DRIVER_QUERY_TYPE_UINT64), 936 QUERY("num-validations", SVGA_QUERY_NUM_VALIDATIONS, 937 PIPE_DRIVER_QUERY_TYPE_UINT64), 938 QUERY("map-buffer-time", SVGA_QUERY_MAP_BUFFER_TIME, 939 PIPE_DRIVER_QUERY_TYPE_MICROSECONDS), 940 QUERY("num-buffers-mapped", SVGA_QUERY_NUM_BUFFERS_MAPPED, 941 PIPE_DRIVER_QUERY_TYPE_UINT64), 942 QUERY("num-textures-mapped", SVGA_QUERY_NUM_TEXTURES_MAPPED, 943 PIPE_DRIVER_QUERY_TYPE_UINT64), 944 QUERY("num-bytes-uploaded", SVGA_QUERY_NUM_BYTES_UPLOADED, 945 PIPE_DRIVER_QUERY_TYPE_BYTES), 946 QUERY("num-command-buffers", SVGA_QUERY_NUM_COMMAND_BUFFERS, 947 PIPE_DRIVER_QUERY_TYPE_UINT64), 948 QUERY("command-buffer-size", SVGA_QUERY_COMMAND_BUFFER_SIZE, 949 PIPE_DRIVER_QUERY_TYPE_BYTES), 950 QUERY("flush-time", SVGA_QUERY_FLUSH_TIME, 951 PIPE_DRIVER_QUERY_TYPE_MICROSECONDS), 952 QUERY("surface-write-flushes", SVGA_QUERY_SURFACE_WRITE_FLUSHES, 953 PIPE_DRIVER_QUERY_TYPE_UINT64), 954 QUERY("num-readbacks", SVGA_QUERY_NUM_READBACKS, 955 PIPE_DRIVER_QUERY_TYPE_UINT64), 956 QUERY("num-resource-updates", SVGA_QUERY_NUM_RESOURCE_UPDATES, 957 PIPE_DRIVER_QUERY_TYPE_UINT64), 958 QUERY("num-buffer-uploads", SVGA_QUERY_NUM_BUFFER_UPLOADS, 959 PIPE_DRIVER_QUERY_TYPE_UINT64), 960 QUERY("num-const-buf-updates", SVGA_QUERY_NUM_CONST_BUF_UPDATES, 961 PIPE_DRIVER_QUERY_TYPE_UINT64), 962 QUERY("num-const-updates", SVGA_QUERY_NUM_CONST_UPDATES, 963 PIPE_DRIVER_QUERY_TYPE_UINT64), 964 QUERY("num-shader-relocations", SVGA_QUERY_NUM_SHADER_RELOCATIONS, 965 PIPE_DRIVER_QUERY_TYPE_UINT64), 966 QUERY("num-surface-relocations", SVGA_QUERY_NUM_SURFACE_RELOCATIONS, 967 PIPE_DRIVER_QUERY_TYPE_UINT64), 968 969 /* running total counters */ 970 QUERY("memory-used", SVGA_QUERY_MEMORY_USED, 971 PIPE_DRIVER_QUERY_TYPE_BYTES), 972 QUERY("num-shaders", SVGA_QUERY_NUM_SHADERS, 973 PIPE_DRIVER_QUERY_TYPE_UINT64), 974 QUERY("num-resources", SVGA_QUERY_NUM_RESOURCES, 975 PIPE_DRIVER_QUERY_TYPE_UINT64), 976 QUERY("num-state-objects", SVGA_QUERY_NUM_STATE_OBJECTS, 977 PIPE_DRIVER_QUERY_TYPE_UINT64), 978 QUERY("num-surface-views", SVGA_QUERY_NUM_SURFACE_VIEWS, 979 PIPE_DRIVER_QUERY_TYPE_UINT64), 980 QUERY("num-generate-mipmap", SVGA_QUERY_NUM_GENERATE_MIPMAP, 981 PIPE_DRIVER_QUERY_TYPE_UINT64), 982 QUERY("num-failed-allocations", SVGA_QUERY_NUM_FAILED_ALLOCATIONS, 983 PIPE_DRIVER_QUERY_TYPE_UINT64), 984 QUERY("num-commands-per-draw", SVGA_QUERY_NUM_COMMANDS_PER_DRAW, 985 PIPE_DRIVER_QUERY_TYPE_FLOAT), 986 QUERY("shader-mem-used", SVGA_QUERY_SHADER_MEM_USED, 987 PIPE_DRIVER_QUERY_TYPE_UINT64), 988 }; 989#undef QUERY 990 991 if (!info) 992 return ARRAY_SIZE(queries); 993 994 if (index >= ARRAY_SIZE(queries)) 995 return 0; 996 997 *info = queries[index]; 998 return 1; 999} 1000 1001 1002static void 1003init_logging(struct pipe_screen *screen) 1004{ 1005 struct svga_screen *svgascreen = svga_screen(screen); 1006 static const char *log_prefix = "Mesa: "; 1007 char host_log[1000]; 1008 1009 /* Log Version to Host */ 1010 snprintf(host_log, sizeof(host_log) - strlen(log_prefix), 1011 "%s%s\n", log_prefix, svga_get_name(screen)); 1012 svgascreen->sws->host_log(svgascreen->sws, host_log); 1013 1014 snprintf(host_log, sizeof(host_log) - strlen(log_prefix), 1015 "%s" PACKAGE_VERSION MESA_GIT_SHA1, log_prefix); 1016 svgascreen->sws->host_log(svgascreen->sws, host_log); 1017 1018 /* If the SVGA_EXTRA_LOGGING env var is set, log the process's command 1019 * line (program name and arguments). 1020 */ 1021 if (debug_get_bool_option("SVGA_EXTRA_LOGGING", FALSE)) { 1022 char cmdline[1000]; 1023 if (os_get_command_line(cmdline, sizeof(cmdline))) { 1024 snprintf(host_log, sizeof(host_log) - strlen(log_prefix), 1025 "%s%s\n", log_prefix, cmdline); 1026 svgascreen->sws->host_log(svgascreen->sws, host_log); 1027 } 1028 } 1029} 1030 1031 1032/** 1033 * no-op logging function to use when SVGA_NO_LOGGING is set. 1034 */ 1035static void 1036nop_host_log(struct svga_winsys_screen *sws, const char *message) 1037{ 1038 /* nothing */ 1039} 1040 1041 1042static void 1043svga_destroy_screen( struct pipe_screen *screen ) 1044{ 1045 struct svga_screen *svgascreen = svga_screen(screen); 1046 1047 svga_screen_cache_cleanup(svgascreen); 1048 1049 mtx_destroy(&svgascreen->swc_mutex); 1050 mtx_destroy(&svgascreen->tex_mutex); 1051 1052 svgascreen->sws->destroy(svgascreen->sws); 1053 1054 FREE(svgascreen); 1055} 1056 1057 1058/** 1059 * Create a new svga_screen object 1060 */ 1061struct pipe_screen * 1062svga_screen_create(struct svga_winsys_screen *sws) 1063{ 1064 struct svga_screen *svgascreen; 1065 struct pipe_screen *screen; 1066 1067#ifdef DEBUG 1068 SVGA_DEBUG = debug_get_flags_option("SVGA_DEBUG", svga_debug_flags, 0 ); 1069#endif 1070 1071 svgascreen = CALLOC_STRUCT(svga_screen); 1072 if (!svgascreen) 1073 goto error1; 1074 1075 svgascreen->debug.force_level_surface_view = 1076 debug_get_bool_option("SVGA_FORCE_LEVEL_SURFACE_VIEW", FALSE); 1077 svgascreen->debug.force_surface_view = 1078 debug_get_bool_option("SVGA_FORCE_SURFACE_VIEW", FALSE); 1079 svgascreen->debug.force_sampler_view = 1080 debug_get_bool_option("SVGA_FORCE_SAMPLER_VIEW", FALSE); 1081 svgascreen->debug.no_surface_view = 1082 debug_get_bool_option("SVGA_NO_SURFACE_VIEW", FALSE); 1083 svgascreen->debug.no_sampler_view = 1084 debug_get_bool_option("SVGA_NO_SAMPLER_VIEW", FALSE); 1085 svgascreen->debug.no_cache_index_buffers = 1086 debug_get_bool_option("SVGA_NO_CACHE_INDEX_BUFFERS", FALSE); 1087 svgascreen->debug.nir = 1088 debug_get_bool_option("SVGA_NIR", FALSE); 1089 1090 screen = &svgascreen->screen; 1091 1092 screen->destroy = svga_destroy_screen; 1093 screen->get_name = svga_get_name; 1094 screen->get_vendor = svga_get_vendor; 1095 screen->get_device_vendor = svga_get_vendor; // TODO actual device vendor 1096 screen->get_param = svga_get_param; 1097 screen->get_shader_param = svga_get_shader_param; 1098 screen->get_compiler_options = svga_get_compiler_options; 1099 screen->get_paramf = svga_get_paramf; 1100 screen->get_timestamp = NULL; 1101 screen->is_format_supported = svga_is_format_supported; 1102 screen->context_create = svga_context_create; 1103 screen->fence_reference = svga_fence_reference; 1104 screen->fence_finish = svga_fence_finish; 1105 screen->fence_get_fd = svga_fence_get_fd; 1106 1107 screen->get_driver_query_info = svga_get_driver_query_info; 1108 1109 screen->get_compute_param = svga_sm5_get_compute_param; 1110 1111 svgascreen->sws = sws; 1112 1113 svga_init_screen_resource_functions(svgascreen); 1114 1115 if (sws->get_hw_version) { 1116 svgascreen->hw_version = sws->get_hw_version(sws); 1117 } else { 1118 svgascreen->hw_version = SVGA3D_HWVERSION_WS65_B1; 1119 } 1120 1121 if (svgascreen->hw_version < SVGA3D_HWVERSION_WS8_B1) { 1122 /* too old for 3D acceleration */ 1123 debug_printf("Hardware version 0x%x is too old for accerated 3D\n", 1124 svgascreen->hw_version); 1125 goto error2; 1126 } 1127 1128 if (sws->have_gl43) { 1129 svgascreen->forcedSampleCount = 1130 get_uint_cap(sws, SVGA3D_DEVCAP_MAX_FORCED_SAMPLE_COUNT, 0); 1131 1132 sws->have_gl43 = sws->have_gl43 && (svgascreen->forcedSampleCount >= 4); 1133 1134 /* Allow a temporary environment variable to enable/disable GL43 support. 1135 */ 1136 sws->have_gl43 = 1137 debug_get_bool_option("SVGA_GL43", sws->have_gl43); 1138 1139 svgascreen->debug.sampler_state_mapping = 1140 debug_get_bool_option("SVGA_SAMPLER_STATE_MAPPING", FALSE); 1141 } 1142 else { 1143 /* sampler state mapping code is only enabled with GL43 1144 * due to the limitation in SW Renderer. (VMware bug 2825014) 1145 */ 1146 svgascreen->debug.sampler_state_mapping = FALSE; 1147 } 1148 1149 debug_printf("%s enabled\n", 1150 sws->have_gl43 ? "SM5+" : 1151 sws->have_sm5 ? "SM5" : 1152 sws->have_sm4_1 ? "SM4_1" : 1153 sws->have_vgpu10 ? "VGPU10" : "VGPU9"); 1154 1155 debug_printf("Mesa: %s %s (%s)\n", svga_get_name(screen), 1156 PACKAGE_VERSION, MESA_GIT_SHA1); 1157 1158 /* 1159 * The D16, D24X8, and D24S8 formats always do an implicit shadow compare 1160 * when sampled from, where as the DF16, DF24, and D24S8_INT do not. So 1161 * we prefer the later when available. 1162 * 1163 * This mimics hardware vendors extensions for D3D depth sampling. See also 1164 * http://aras-p.info/texts/D3D9GPUHacks.html 1165 */ 1166 1167 { 1168 boolean has_df16, has_df24, has_d24s8_int; 1169 SVGA3dSurfaceFormatCaps caps; 1170 SVGA3dSurfaceFormatCaps mask; 1171 mask.value = 0; 1172 mask.zStencil = 1; 1173 mask.texture = 1; 1174 1175 svgascreen->depth.z16 = SVGA3D_Z_D16; 1176 svgascreen->depth.x8z24 = SVGA3D_Z_D24X8; 1177 svgascreen->depth.s8z24 = SVGA3D_Z_D24S8; 1178 1179 svga_get_format_cap(svgascreen, SVGA3D_Z_DF16, &caps); 1180 has_df16 = (caps.value & mask.value) == mask.value; 1181 1182 svga_get_format_cap(svgascreen, SVGA3D_Z_DF24, &caps); 1183 has_df24 = (caps.value & mask.value) == mask.value; 1184 1185 svga_get_format_cap(svgascreen, SVGA3D_Z_D24S8_INT, &caps); 1186 has_d24s8_int = (caps.value & mask.value) == mask.value; 1187 1188 /* XXX: We might want some other logic here. 1189 * Like if we only have d24s8_int we should 1190 * emulate the other formats with that. 1191 */ 1192 if (has_df16) { 1193 svgascreen->depth.z16 = SVGA3D_Z_DF16; 1194 } 1195 if (has_df24) { 1196 svgascreen->depth.x8z24 = SVGA3D_Z_DF24; 1197 } 1198 if (has_d24s8_int) { 1199 svgascreen->depth.s8z24 = SVGA3D_Z_D24S8_INT; 1200 } 1201 } 1202 1203 /* Query device caps 1204 */ 1205 if (sws->have_vgpu10) { 1206 svgascreen->haveProvokingVertex 1207 = get_bool_cap(sws, SVGA3D_DEVCAP_DX_PROVOKING_VERTEX, FALSE); 1208 svgascreen->haveLineSmooth = TRUE; 1209 svgascreen->maxPointSize = 80.0F; 1210 svgascreen->max_color_buffers = SVGA3D_DX_MAX_RENDER_TARGETS; 1211 1212 /* Multisample samples per pixel */ 1213 if (sws->have_sm4_1 && debug_get_bool_option("SVGA_MSAA", TRUE)) { 1214 if (get_bool_cap(sws, SVGA3D_DEVCAP_MULTISAMPLE_2X, FALSE)) 1215 svgascreen->ms_samples |= 1 << 1; 1216 if (get_bool_cap(sws, SVGA3D_DEVCAP_MULTISAMPLE_4X, FALSE)) 1217 svgascreen->ms_samples |= 1 << 3; 1218 } 1219 1220 if (sws->have_sm5 && debug_get_bool_option("SVGA_MSAA", TRUE)) { 1221 if (get_bool_cap(sws, SVGA3D_DEVCAP_MULTISAMPLE_8X, FALSE)) 1222 svgascreen->ms_samples |= 1 << 7; 1223 } 1224 1225 /* Maximum number of constant buffers */ 1226 if (sws->have_gl43) { 1227 svgascreen->max_const_buffers = SVGA_MAX_CONST_BUFS; 1228 } 1229 else { 1230 svgascreen->max_const_buffers = 1231 get_uint_cap(sws, SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS, 1); 1232 svgascreen->max_const_buffers = MIN2(svgascreen->max_const_buffers, 1233 SVGA_MAX_CONST_BUFS); 1234 } 1235 1236 svgascreen->haveBlendLogicops = 1237 get_bool_cap(sws, SVGA3D_DEVCAP_LOGIC_BLENDOPS, FALSE); 1238 1239 screen->is_format_supported = svga_is_dx_format_supported; 1240 1241 svgascreen->max_viewports = SVGA3D_DX_MAX_VIEWPORTS; 1242 1243 /* Shader limits */ 1244 if (sws->have_sm4_1) { 1245 svgascreen->max_vs_inputs = VGPU10_1_MAX_VS_INPUTS; 1246 svgascreen->max_vs_outputs = VGPU10_1_MAX_VS_OUTPUTS; 1247 svgascreen->max_gs_inputs = VGPU10_1_MAX_GS_INPUTS; 1248 } 1249 else { 1250 svgascreen->max_vs_inputs = VGPU10_MAX_VS_INPUTS; 1251 svgascreen->max_vs_outputs = VGPU10_MAX_VS_OUTPUTS; 1252 svgascreen->max_gs_inputs = VGPU10_MAX_GS_INPUTS; 1253 } 1254 } 1255 else { 1256 /* VGPU9 */ 1257 unsigned vs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_VERTEX_SHADER_VERSION, 1258 SVGA3DVSVERSION_NONE); 1259 unsigned fs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION, 1260 SVGA3DPSVERSION_NONE); 1261 1262 /* we require Shader model 3.0 or later */ 1263 if (fs_ver < SVGA3DPSVERSION_30 || vs_ver < SVGA3DVSVERSION_30) { 1264 goto error2; 1265 } 1266 1267 svgascreen->haveProvokingVertex = FALSE; 1268 1269 svgascreen->haveLineSmooth = 1270 get_bool_cap(sws, SVGA3D_DEVCAP_LINE_AA, FALSE); 1271 1272 svgascreen->maxPointSize = 1273 get_float_cap(sws, SVGA3D_DEVCAP_MAX_POINT_SIZE, 1.0f); 1274 /* Keep this to a reasonable size to avoid failures in conform/pntaa.c */ 1275 svgascreen->maxPointSize = MIN2(svgascreen->maxPointSize, 80.0f); 1276 1277 /* The SVGA3D device always supports 4 targets at this time, regardless 1278 * of what querying SVGA3D_DEVCAP_MAX_RENDER_TARGETS might return. 1279 */ 1280 svgascreen->max_color_buffers = 4; 1281 1282 /* Only support one constant buffer 1283 */ 1284 svgascreen->max_const_buffers = 1; 1285 1286 /* No multisampling */ 1287 svgascreen->ms_samples = 0; 1288 1289 /* Only one viewport */ 1290 svgascreen->max_viewports = 1; 1291 1292 /* Shader limits */ 1293 svgascreen->max_vs_inputs = 16; 1294 svgascreen->max_vs_outputs = 10; 1295 svgascreen->max_gs_inputs = 0; 1296 } 1297 1298 /* common VGPU9 / VGPU10 caps */ 1299 svgascreen->haveLineStipple = 1300 get_bool_cap(sws, SVGA3D_DEVCAP_LINE_STIPPLE, FALSE); 1301 1302 svgascreen->maxLineWidth = 1303 MAX2(1.0, get_float_cap(sws, SVGA3D_DEVCAP_MAX_LINE_WIDTH, 1.0f)); 1304 1305 svgascreen->maxLineWidthAA = 1306 MAX2(1.0, get_float_cap(sws, SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH, 1.0f)); 1307 1308 if (0) { 1309 debug_printf("svga: haveProvokingVertex %u\n", 1310 svgascreen->haveProvokingVertex); 1311 debug_printf("svga: haveLineStip %u " 1312 "haveLineSmooth %u maxLineWidth %.2f maxLineWidthAA %.2f\n", 1313 svgascreen->haveLineStipple, svgascreen->haveLineSmooth, 1314 svgascreen->maxLineWidth, svgascreen->maxLineWidthAA); 1315 debug_printf("svga: maxPointSize %g\n", svgascreen->maxPointSize); 1316 debug_printf("svga: msaa samples mask: 0x%x\n", svgascreen->ms_samples); 1317 } 1318 1319 (void) mtx_init(&svgascreen->tex_mutex, mtx_plain); 1320 (void) mtx_init(&svgascreen->swc_mutex, mtx_recursive); 1321 1322 svga_screen_cache_init(svgascreen); 1323 1324 if (debug_get_bool_option("SVGA_NO_LOGGING", FALSE) == TRUE) { 1325 svgascreen->sws->host_log = nop_host_log; 1326 } else { 1327 init_logging(screen); 1328 } 1329 1330 return screen; 1331error2: 1332 FREE(svgascreen); 1333error1: 1334 return NULL; 1335} 1336 1337 1338struct svga_winsys_screen * 1339svga_winsys_screen(struct pipe_screen *screen) 1340{ 1341 return svga_screen(screen)->sws; 1342} 1343 1344 1345#ifdef DEBUG 1346struct svga_screen * 1347svga_screen(struct pipe_screen *screen) 1348{ 1349 assert(screen); 1350 assert(screen->destroy == svga_destroy_screen); 1351 return (struct svga_screen *)screen; 1352} 1353#endif 1354