1/************************************************************************** 2 * 3 * Copyright 1998-2022 VMware, Inc. 4 * SPDX-License-Identifier: GPL-2.0 OR MIT 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28/* 29 * svga3d_surfacedefs.h -- 30 * 31 * Surface/format/image helper code. 32 */ 33 34#ifndef SVGA3D_SURFACEDEFS_H 35#define SVGA3D_SURFACEDEFS_H 36 37#include "svga3d_reg.h" 38 39#define max_t(type, x, y) ((x) > (y) ? (x) : (y)) 40 41/* 42 * enum svga3d_block_desc describes the active data channels in a block. 43 * 44 * There can be at-most four active channels in a block: 45 * 1. Red, bump W, luminance and depth are stored in the first channel. 46 * 2. Green, bump V and stencil are stored in the second channel. 47 * 3. Blue and bump U are stored in the third channel. 48 * 4. Alpha and bump Q are stored in the fourth channel. 49 * 50 * Block channels can be used to store compressed and buffer data: 51 * 1. For compressed formats, only the data channel is used and its size 52 * is equal to that of a singular block in the compression scheme. 53 * 2. For buffer formats, only the data channel is used and its size is 54 * exactly one byte in length. 55 * 3. In each case the bit depth represent the size of a singular block. 56 * 57 * Note: Compressed and IEEE formats do not use the bitMask structure. 58 */ 59 60enum svga3d_block_desc { 61 62 SVGA3DBLOCKDESC_NONE = 0, /* No channels are active */ 63 SVGA3DBLOCKDESC_BLUE = 1 << 0, /* Block with red channel data */ 64 SVGA3DBLOCKDESC_W = 1 << 0, 65 SVGA3DBLOCKDESC_BUMP_L = 1 << 0, 66 67 /* Format contains Green/V data */ 68 SVGA3DBLOCKDESC_GREEN = 1 << 1, 69 SVGA3DBLOCKDESC_V = 1 << 1, 70 71 /* Format contains Red/W/Luminance data */ 72 SVGA3DBLOCKDESC_RED = 1 << 2, 73 SVGA3DBLOCKDESC_U = 1 << 2, 74 SVGA3DBLOCKDESC_LUMINANCE = 1 << 2, 75 76 SVGA3DBLOCKDESC_ALPHA = 1 << 3, /* Block with an alpha channel */ 77 SVGA3DBLOCKDESC_Q = 1 << 3, /* Block with bump Q channel data */ 78 SVGA3DBLOCKDESC_BUFFER = 1 << 4, /* Block stores 1 byte of data */ 79 SVGA3DBLOCKDESC_COMPRESSED = 1 << 5, /* Block stores n bytes of data depending 80 on the compression method used */ 81 SVGA3DBLOCKDESC_FP = 1 << 6, 82 83 SVGA3DBLOCKDESC_PLANAR_YUV = 1 << 7, 84 SVGA3DBLOCKDESC_2PLANAR_YUV = 1 << 8, 85 SVGA3DBLOCKDESC_3PLANAR_YUV = 1 << 9, 86 SVGA3DBLOCKDESC_STENCIL = 1 << 11, 87 SVGA3DBLOCKDESC_TYPELESS = 1 << 12, 88 SVGA3DBLOCKDESC_SINT = 1 << 13, 89 SVGA3DBLOCKDESC_UINT = 1 << 14, 90 SVGA3DBLOCKDESC_NORM = 1 << 15, 91 SVGA3DBLOCKDESC_SRGB = 1 << 16, 92 SVGA3DBLOCKDESC_EXP = 1 << 17, 93 SVGA3DBLOCKDESC_COLOR = 1 << 18, 94 SVGA3DBLOCKDESC_DEPTH = 1 << 19, 95 SVGA3DBLOCKDESC_BUMP = 1 << 20, 96 SVGA3DBLOCKDESC_YUV_VIDEO = 1 << 21, 97 SVGA3DBLOCKDESC_MIXED = 1 << 22, 98 SVGA3DBLOCKDESC_CX = 1 << 23, 99 100 /* Different compressed format groups. */ 101 SVGA3DBLOCKDESC_BC1 = 1 << 24, 102 SVGA3DBLOCKDESC_BC2 = 1 << 25, 103 SVGA3DBLOCKDESC_BC3 = 1 << 26, 104 SVGA3DBLOCKDESC_BC4 = 1 << 27, 105 SVGA3DBLOCKDESC_BC5 = 1 << 28, 106 SVGA3DBLOCKDESC_BC6H = 1 << 29, 107 SVGA3DBLOCKDESC_BC7 = 1 << 30, 108 SVGA3DBLOCKDESC_COMPRESSED_MASK = SVGA3DBLOCKDESC_BC1 | 109 SVGA3DBLOCKDESC_BC2 | 110 SVGA3DBLOCKDESC_BC3 | 111 SVGA3DBLOCKDESC_BC4 | 112 SVGA3DBLOCKDESC_BC5 | 113 SVGA3DBLOCKDESC_BC6H | 114 SVGA3DBLOCKDESC_BC7, 115 116 SVGA3DBLOCKDESC_A_UINT = SVGA3DBLOCKDESC_ALPHA | 117 SVGA3DBLOCKDESC_UINT | 118 SVGA3DBLOCKDESC_COLOR, 119 SVGA3DBLOCKDESC_A_UNORM = SVGA3DBLOCKDESC_A_UINT | 120 SVGA3DBLOCKDESC_NORM, 121 SVGA3DBLOCKDESC_R_UINT = SVGA3DBLOCKDESC_RED | 122 SVGA3DBLOCKDESC_UINT | 123 SVGA3DBLOCKDESC_COLOR, 124 SVGA3DBLOCKDESC_R_UNORM = SVGA3DBLOCKDESC_R_UINT | 125 SVGA3DBLOCKDESC_NORM, 126 SVGA3DBLOCKDESC_R_SINT = SVGA3DBLOCKDESC_RED | 127 SVGA3DBLOCKDESC_SINT | 128 SVGA3DBLOCKDESC_COLOR, 129 SVGA3DBLOCKDESC_R_SNORM = SVGA3DBLOCKDESC_R_SINT | 130 SVGA3DBLOCKDESC_NORM, 131 SVGA3DBLOCKDESC_G_UINT = SVGA3DBLOCKDESC_GREEN | 132 SVGA3DBLOCKDESC_UINT | 133 SVGA3DBLOCKDESC_COLOR, 134 SVGA3DBLOCKDESC_RG_UINT = SVGA3DBLOCKDESC_RED | 135 SVGA3DBLOCKDESC_GREEN | 136 SVGA3DBLOCKDESC_UINT | 137 SVGA3DBLOCKDESC_COLOR, 138 SVGA3DBLOCKDESC_RG_UNORM = SVGA3DBLOCKDESC_RG_UINT | 139 SVGA3DBLOCKDESC_NORM, 140 SVGA3DBLOCKDESC_RG_SINT = SVGA3DBLOCKDESC_RED | 141 SVGA3DBLOCKDESC_GREEN | 142 SVGA3DBLOCKDESC_SINT | 143 SVGA3DBLOCKDESC_COLOR, 144 SVGA3DBLOCKDESC_RG_SNORM = SVGA3DBLOCKDESC_RG_SINT | 145 SVGA3DBLOCKDESC_NORM, 146 SVGA3DBLOCKDESC_RGB_UINT = SVGA3DBLOCKDESC_RED | 147 SVGA3DBLOCKDESC_GREEN | 148 SVGA3DBLOCKDESC_BLUE | 149 SVGA3DBLOCKDESC_UINT | 150 SVGA3DBLOCKDESC_COLOR, 151 SVGA3DBLOCKDESC_RGB_SINT = SVGA3DBLOCKDESC_RED | 152 SVGA3DBLOCKDESC_GREEN | 153 SVGA3DBLOCKDESC_BLUE | 154 SVGA3DBLOCKDESC_SINT | 155 SVGA3DBLOCKDESC_COLOR, 156 SVGA3DBLOCKDESC_RGB_UNORM = SVGA3DBLOCKDESC_RGB_UINT | 157 SVGA3DBLOCKDESC_NORM, 158 SVGA3DBLOCKDESC_RGB_UNORM_SRGB = SVGA3DBLOCKDESC_RGB_UNORM | 159 SVGA3DBLOCKDESC_SRGB, 160 SVGA3DBLOCKDESC_RGBA_UINT = SVGA3DBLOCKDESC_RED | 161 SVGA3DBLOCKDESC_GREEN | 162 SVGA3DBLOCKDESC_BLUE | 163 SVGA3DBLOCKDESC_ALPHA | 164 SVGA3DBLOCKDESC_UINT | 165 SVGA3DBLOCKDESC_COLOR, 166 SVGA3DBLOCKDESC_RGBA_UNORM = SVGA3DBLOCKDESC_RGBA_UINT | 167 SVGA3DBLOCKDESC_NORM, 168 SVGA3DBLOCKDESC_RGBA_UNORM_SRGB = SVGA3DBLOCKDESC_RGBA_UNORM | 169 SVGA3DBLOCKDESC_SRGB, 170 SVGA3DBLOCKDESC_RGBA_SINT = SVGA3DBLOCKDESC_RED | 171 SVGA3DBLOCKDESC_GREEN | 172 SVGA3DBLOCKDESC_BLUE | 173 SVGA3DBLOCKDESC_ALPHA | 174 SVGA3DBLOCKDESC_SINT | 175 SVGA3DBLOCKDESC_COLOR, 176 SVGA3DBLOCKDESC_RGBA_SNORM = SVGA3DBLOCKDESC_RGBA_SINT | 177 SVGA3DBLOCKDESC_NORM, 178 SVGA3DBLOCKDESC_RGBA_FP = SVGA3DBLOCKDESC_RED | 179 SVGA3DBLOCKDESC_GREEN | 180 SVGA3DBLOCKDESC_BLUE | 181 SVGA3DBLOCKDESC_ALPHA | 182 SVGA3DBLOCKDESC_FP | 183 SVGA3DBLOCKDESC_COLOR, 184 SVGA3DBLOCKDESC_UV = SVGA3DBLOCKDESC_U | 185 SVGA3DBLOCKDESC_V | 186 SVGA3DBLOCKDESC_BUMP, 187 SVGA3DBLOCKDESC_UVL = SVGA3DBLOCKDESC_UV | 188 SVGA3DBLOCKDESC_BUMP_L | 189 SVGA3DBLOCKDESC_MIXED | 190 SVGA3DBLOCKDESC_BUMP, 191 SVGA3DBLOCKDESC_UVW = SVGA3DBLOCKDESC_UV | 192 SVGA3DBLOCKDESC_W | 193 SVGA3DBLOCKDESC_BUMP, 194 SVGA3DBLOCKDESC_UVWA = SVGA3DBLOCKDESC_UVW | 195 SVGA3DBLOCKDESC_ALPHA | 196 SVGA3DBLOCKDESC_MIXED | 197 SVGA3DBLOCKDESC_BUMP, 198 SVGA3DBLOCKDESC_UVWQ = SVGA3DBLOCKDESC_U | 199 SVGA3DBLOCKDESC_V | 200 SVGA3DBLOCKDESC_W | 201 SVGA3DBLOCKDESC_Q | 202 SVGA3DBLOCKDESC_BUMP, 203 SVGA3DBLOCKDESC_L_UNORM = SVGA3DBLOCKDESC_LUMINANCE | 204 SVGA3DBLOCKDESC_UINT | 205 SVGA3DBLOCKDESC_NORM | 206 SVGA3DBLOCKDESC_COLOR, 207 SVGA3DBLOCKDESC_LA_UNORM = SVGA3DBLOCKDESC_LUMINANCE | 208 SVGA3DBLOCKDESC_ALPHA | 209 SVGA3DBLOCKDESC_UINT | 210 SVGA3DBLOCKDESC_NORM | 211 SVGA3DBLOCKDESC_COLOR, 212 SVGA3DBLOCKDESC_R_FP = SVGA3DBLOCKDESC_RED | 213 SVGA3DBLOCKDESC_FP | 214 SVGA3DBLOCKDESC_COLOR, 215 SVGA3DBLOCKDESC_RG_FP = SVGA3DBLOCKDESC_R_FP | 216 SVGA3DBLOCKDESC_GREEN | 217 SVGA3DBLOCKDESC_COLOR, 218 SVGA3DBLOCKDESC_RGB_FP = SVGA3DBLOCKDESC_RG_FP | 219 SVGA3DBLOCKDESC_BLUE | 220 SVGA3DBLOCKDESC_COLOR, 221 SVGA3DBLOCKDESC_YUV = SVGA3DBLOCKDESC_YUV_VIDEO | 222 SVGA3DBLOCKDESC_COLOR, 223 SVGA3DBLOCKDESC_AYUV = SVGA3DBLOCKDESC_ALPHA | 224 SVGA3DBLOCKDESC_YUV_VIDEO | 225 SVGA3DBLOCKDESC_COLOR, 226 SVGA3DBLOCKDESC_RGB_EXP = SVGA3DBLOCKDESC_RED | 227 SVGA3DBLOCKDESC_GREEN | 228 SVGA3DBLOCKDESC_BLUE | 229 SVGA3DBLOCKDESC_EXP | 230 SVGA3DBLOCKDESC_COLOR, 231 232 SVGA3DBLOCKDESC_COMP_TYPELESS = SVGA3DBLOCKDESC_COMPRESSED | 233 SVGA3DBLOCKDESC_TYPELESS, 234 SVGA3DBLOCKDESC_COMP_UNORM = SVGA3DBLOCKDESC_COMPRESSED | 235 SVGA3DBLOCKDESC_UINT | 236 SVGA3DBLOCKDESC_NORM | 237 SVGA3DBLOCKDESC_COLOR, 238 SVGA3DBLOCKDESC_COMP_SNORM = SVGA3DBLOCKDESC_COMPRESSED | 239 SVGA3DBLOCKDESC_SINT | 240 SVGA3DBLOCKDESC_NORM | 241 SVGA3DBLOCKDESC_COLOR, 242 SVGA3DBLOCKDESC_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_COMP_UNORM | 243 SVGA3DBLOCKDESC_SRGB, 244 SVGA3DBLOCKDESC_BC1_COMP_TYPELESS = SVGA3DBLOCKDESC_BC1 | 245 SVGA3DBLOCKDESC_COMP_TYPELESS, 246 SVGA3DBLOCKDESC_BC1_COMP_UNORM = SVGA3DBLOCKDESC_BC1 | 247 SVGA3DBLOCKDESC_COMP_UNORM, 248 SVGA3DBLOCKDESC_BC1_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_BC1_COMP_UNORM | 249 SVGA3DBLOCKDESC_SRGB, 250 SVGA3DBLOCKDESC_BC2_COMP_TYPELESS = SVGA3DBLOCKDESC_BC2 | 251 SVGA3DBLOCKDESC_COMP_TYPELESS, 252 SVGA3DBLOCKDESC_BC2_COMP_UNORM = SVGA3DBLOCKDESC_BC2 | 253 SVGA3DBLOCKDESC_COMP_UNORM, 254 SVGA3DBLOCKDESC_BC2_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_BC2_COMP_UNORM | 255 SVGA3DBLOCKDESC_SRGB, 256 SVGA3DBLOCKDESC_BC3_COMP_TYPELESS = SVGA3DBLOCKDESC_BC3 | 257 SVGA3DBLOCKDESC_COMP_TYPELESS, 258 SVGA3DBLOCKDESC_BC3_COMP_UNORM = SVGA3DBLOCKDESC_BC3 | 259 SVGA3DBLOCKDESC_COMP_UNORM, 260 SVGA3DBLOCKDESC_BC3_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_BC3_COMP_UNORM | 261 SVGA3DBLOCKDESC_SRGB, 262 SVGA3DBLOCKDESC_BC4_COMP_TYPELESS = SVGA3DBLOCKDESC_BC4 | 263 SVGA3DBLOCKDESC_COMP_TYPELESS, 264 SVGA3DBLOCKDESC_BC4_COMP_UNORM = SVGA3DBLOCKDESC_BC4 | 265 SVGA3DBLOCKDESC_COMP_UNORM, 266 SVGA3DBLOCKDESC_BC4_COMP_SNORM = SVGA3DBLOCKDESC_BC4 | 267 SVGA3DBLOCKDESC_COMP_SNORM, 268 SVGA3DBLOCKDESC_BC5_COMP_TYPELESS = SVGA3DBLOCKDESC_BC5 | 269 SVGA3DBLOCKDESC_COMP_TYPELESS, 270 SVGA3DBLOCKDESC_BC5_COMP_UNORM = SVGA3DBLOCKDESC_BC5 | 271 SVGA3DBLOCKDESC_COMP_UNORM, 272 SVGA3DBLOCKDESC_BC5_COMP_SNORM = SVGA3DBLOCKDESC_BC5 | 273 SVGA3DBLOCKDESC_COMP_SNORM, 274 SVGA3DBLOCKDESC_BC6H_COMP_TYPELESS = SVGA3DBLOCKDESC_BC6H | 275 SVGA3DBLOCKDESC_COMP_TYPELESS, 276 SVGA3DBLOCKDESC_BC6H_COMP_UF16 = SVGA3DBLOCKDESC_BC6H | 277 SVGA3DBLOCKDESC_COMPRESSED, 278 SVGA3DBLOCKDESC_BC6H_COMP_SF16 = SVGA3DBLOCKDESC_BC6H | 279 SVGA3DBLOCKDESC_COMPRESSED, 280 SVGA3DBLOCKDESC_BC7_COMP_TYPELESS = SVGA3DBLOCKDESC_BC7 | 281 SVGA3DBLOCKDESC_COMP_TYPELESS, 282 SVGA3DBLOCKDESC_BC7_COMP_UNORM = SVGA3DBLOCKDESC_BC7 | 283 SVGA3DBLOCKDESC_COMP_UNORM, 284 SVGA3DBLOCKDESC_BC7_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_BC7_COMP_UNORM | 285 SVGA3DBLOCKDESC_SRGB, 286 287 SVGA3DBLOCKDESC_NV12 = SVGA3DBLOCKDESC_YUV_VIDEO | 288 SVGA3DBLOCKDESC_PLANAR_YUV | 289 SVGA3DBLOCKDESC_2PLANAR_YUV | 290 SVGA3DBLOCKDESC_COLOR, 291 SVGA3DBLOCKDESC_YV12 = SVGA3DBLOCKDESC_YUV_VIDEO | 292 SVGA3DBLOCKDESC_PLANAR_YUV | 293 SVGA3DBLOCKDESC_3PLANAR_YUV | 294 SVGA3DBLOCKDESC_COLOR, 295 296 SVGA3DBLOCKDESC_DEPTH_UINT = SVGA3DBLOCKDESC_DEPTH | 297 SVGA3DBLOCKDESC_UINT, 298 SVGA3DBLOCKDESC_DEPTH_UNORM = SVGA3DBLOCKDESC_DEPTH_UINT | 299 SVGA3DBLOCKDESC_NORM, 300 SVGA3DBLOCKDESC_DS = SVGA3DBLOCKDESC_DEPTH | 301 SVGA3DBLOCKDESC_STENCIL, 302 SVGA3DBLOCKDESC_DS_UINT = SVGA3DBLOCKDESC_DEPTH | 303 SVGA3DBLOCKDESC_STENCIL | 304 SVGA3DBLOCKDESC_UINT, 305 SVGA3DBLOCKDESC_DS_UNORM = SVGA3DBLOCKDESC_DS_UINT | 306 SVGA3DBLOCKDESC_NORM, 307 SVGA3DBLOCKDESC_DEPTH_FP = SVGA3DBLOCKDESC_DEPTH | 308 SVGA3DBLOCKDESC_FP, 309 310 SVGA3DBLOCKDESC_UV_UINT = SVGA3DBLOCKDESC_UV | 311 SVGA3DBLOCKDESC_UINT, 312 SVGA3DBLOCKDESC_UV_SNORM = SVGA3DBLOCKDESC_UV | 313 SVGA3DBLOCKDESC_SINT | 314 SVGA3DBLOCKDESC_NORM, 315 SVGA3DBLOCKDESC_UVCX_SNORM = SVGA3DBLOCKDESC_UV_SNORM | 316 SVGA3DBLOCKDESC_CX, 317 SVGA3DBLOCKDESC_UVWQ_SNORM = SVGA3DBLOCKDESC_UVWQ | 318 SVGA3DBLOCKDESC_SINT | 319 SVGA3DBLOCKDESC_NORM, 320}; 321 322 323typedef struct SVGA3dChannelDef { 324 union { 325 uint8 blue; 326 uint8 w_bump; 327 uint8 l_bump; 328 uint8 uv_video; 329 uint8 u_video; 330 }; 331 union { 332 uint8 green; 333 uint8 stencil; 334 uint8 v_bump; 335 uint8 v_video; 336 }; 337 union { 338 uint8 red; 339 uint8 u_bump; 340 uint8 luminance; 341 uint8 y_video; 342 uint8 depth; 343 uint8 data; 344 }; 345 union { 346 uint8 alpha; 347 uint8 q_bump; 348 uint8 exp; 349 }; 350} SVGA3dChannelDef; 351 352struct svga3d_surface_desc { 353 SVGA3dSurfaceFormat format; 354 enum svga3d_block_desc block_desc; 355 356 SVGA3dSize block_size; 357 uint32 bytes_per_block; 358 uint32 pitch_bytes_per_block; 359 360 SVGA3dChannelDef bitDepth; 361 SVGA3dChannelDef bitOffset; 362}; 363 364static const struct svga3d_surface_desc svga3d_surface_descs[] = { 365 {SVGA3D_FORMAT_INVALID, SVGA3DBLOCKDESC_NONE, 366 {1, 1, 1}, 0, 0, 367 {{0}, {0}, {0}, {0}}, 368 {{0}, {0}, {0}, {0}}}, 369 370 {SVGA3D_X8R8G8B8, SVGA3DBLOCKDESC_RGB_UNORM, 371 {1, 1, 1}, 4, 4, 372 {{8}, {8}, {8}, {0}}, 373 {{0}, {8}, {16}, {24}}}, 374 375 {SVGA3D_A8R8G8B8, SVGA3DBLOCKDESC_RGBA_UNORM, 376 {1, 1, 1}, 4, 4, 377 {{8}, {8}, {8}, {8}}, 378 {{0}, {8}, {16}, {24}}}, 379 380 {SVGA3D_R5G6B5, SVGA3DBLOCKDESC_RGB_UNORM, 381 {1, 1, 1}, 2, 2, 382 {{5}, {6}, {5}, {0}}, 383 {{0}, {5}, {11}, {0}}}, 384 385 {SVGA3D_X1R5G5B5, SVGA3DBLOCKDESC_RGB_UNORM, 386 {1, 1, 1}, 2, 2, 387 {{5}, {5}, {5}, {0}}, 388 {{0}, {5}, {10}, {0}}}, 389 390 {SVGA3D_A1R5G5B5, SVGA3DBLOCKDESC_RGBA_UNORM, 391 {1, 1, 1}, 2, 2, 392 {{5}, {5}, {5}, {1}}, 393 {{0}, {5}, {10}, {15}}}, 394 395 {SVGA3D_A4R4G4B4, SVGA3DBLOCKDESC_RGBA_UNORM, 396 {1, 1, 1}, 2, 2, 397 {{4}, {4}, {4}, {4}}, 398 {{0}, {4}, {8}, {12}}}, 399 400 {SVGA3D_Z_D32, SVGA3DBLOCKDESC_DEPTH_UNORM, 401 {1, 1, 1}, 4, 4, 402 {{0}, {0}, {32}, {0}}, 403 {{0}, {0}, {0}, {0}}}, 404 405 {SVGA3D_Z_D16, SVGA3DBLOCKDESC_DEPTH_UNORM, 406 {1, 1, 1}, 2, 2, 407 {{0}, {0}, {16}, {0}}, 408 {{0}, {0}, {0}, {0}}}, 409 410 {SVGA3D_Z_D24S8, SVGA3DBLOCKDESC_DS_UNORM, 411 {1, 1, 1}, 4, 4, 412 {{0}, {8}, {24}, {0}}, 413 {{0}, {0}, {8}, {0}}}, 414 415 {SVGA3D_Z_D15S1, SVGA3DBLOCKDESC_DS_UNORM, 416 {1, 1, 1}, 2, 2, 417 {{0}, {1}, {15}, {0}}, 418 {{0}, {0}, {1}, {0}}}, 419 420 {SVGA3D_LUMINANCE8, SVGA3DBLOCKDESC_L_UNORM, 421 {1, 1, 1}, 1, 1, 422 {{0}, {0}, {8}, {0}}, 423 {{0}, {0}, {0}, {0}}}, 424 425 {SVGA3D_LUMINANCE4_ALPHA4, SVGA3DBLOCKDESC_LA_UNORM, 426 {1, 1, 1}, 1, 1, 427 {{0}, {0}, {4}, {4}}, 428 {{0}, {0}, {0}, {4}}}, 429 430 {SVGA3D_LUMINANCE16, SVGA3DBLOCKDESC_L_UNORM, 431 {1, 1, 1}, 2, 2, 432 {{0}, {0}, {16}, {0}}, 433 {{0}, {0}, {0}, {0}}}, 434 435 {SVGA3D_LUMINANCE8_ALPHA8, SVGA3DBLOCKDESC_LA_UNORM, 436 {1, 1, 1}, 2, 2, 437 {{0}, {0}, {8}, {8}}, 438 {{0}, {0}, {0}, {8}}}, 439 440 {SVGA3D_DXT1, SVGA3DBLOCKDESC_BC1_COMP_UNORM, 441 {4, 4, 1}, 8, 8, 442 {{0}, {0}, {64}, {0}}, 443 {{0}, {0}, {0}, {0}}}, 444 445 {SVGA3D_DXT2, SVGA3DBLOCKDESC_BC2_COMP_UNORM, 446 {4, 4, 1}, 16, 16, 447 {{0}, {0}, {128}, {0}}, 448 {{0}, {0}, {0}, {0}}}, 449 450 {SVGA3D_DXT3, SVGA3DBLOCKDESC_BC2_COMP_UNORM, 451 {4, 4, 1}, 16, 16, 452 {{0}, {0}, {128}, {0}}, 453 {{0}, {0}, {0}, {0}}}, 454 455 {SVGA3D_DXT4, SVGA3DBLOCKDESC_BC3_COMP_UNORM, 456 {4, 4, 1}, 16, 16, 457 {{0}, {0}, {128}, {0}}, 458 {{0}, {0}, {0}, {0}}}, 459 460 {SVGA3D_DXT5, SVGA3DBLOCKDESC_BC3_COMP_UNORM, 461 {4, 4, 1}, 16, 16, 462 {{0}, {0}, {128}, {0}}, 463 {{0}, {0}, {0}, {0}}}, 464 465 {SVGA3D_BUMPU8V8, SVGA3DBLOCKDESC_UV_SNORM, 466 {1, 1, 1}, 2, 2, 467 {{0}, {8}, {8}, {0}}, 468 {{0}, {8}, {0}, {0}}}, 469 470 {SVGA3D_BUMPL6V5U5, SVGA3DBLOCKDESC_UVL, 471 {1, 1, 1}, 2, 2, 472 {{6}, {5}, {5}, {0}}, 473 {{10}, {5}, {0}, {0}}}, 474 475 {SVGA3D_BUMPX8L8V8U8, SVGA3DBLOCKDESC_UVL, 476 {1, 1, 1}, 4, 4, 477 {{8}, {8}, {8}, {0}}, 478 {{16}, {8}, {0}, {0}}}, 479 480 {SVGA3D_FORMAT_DEAD1, SVGA3DBLOCKDESC_NONE, 481 {1, 1, 1}, 3, 3, 482 {{8}, {8}, {8}, {0}}, 483 {{16}, {8}, {0}, {0}}}, 484 485 {SVGA3D_ARGB_S10E5, SVGA3DBLOCKDESC_RGBA_FP, 486 {1, 1, 1}, 8, 8, 487 {{16}, {16}, {16}, {16}}, 488 {{32}, {16}, {0}, {48}}}, 489 490 {SVGA3D_ARGB_S23E8, SVGA3DBLOCKDESC_RGBA_FP, 491 {1, 1, 1}, 16, 16, 492 {{32}, {32}, {32}, {32}}, 493 {{64}, {32}, {0}, {96}}}, 494 495 {SVGA3D_A2R10G10B10, SVGA3DBLOCKDESC_RGBA_UNORM, 496 {1, 1, 1}, 4, 4, 497 {{10}, {10}, {10}, {2}}, 498 {{0}, {10}, {20}, {30}}}, 499 500 {SVGA3D_V8U8, SVGA3DBLOCKDESC_UV_SNORM, 501 {1, 1, 1}, 2, 2, 502 {{0}, {8}, {8}, {0}}, 503 {{0}, {8}, {0}, {0}}}, 504 505 {SVGA3D_Q8W8V8U8, SVGA3DBLOCKDESC_UVWQ_SNORM, 506 {1, 1, 1}, 4, 4, 507 {{8}, {8}, {8}, {8}}, 508 {{16}, {8}, {0}, {24}}}, 509 510 {SVGA3D_CxV8U8, SVGA3DBLOCKDESC_UVCX_SNORM, 511 {1, 1, 1}, 2, 2, 512 {{0}, {8}, {8}, {0}}, 513 {{0}, {8}, {0}, {0}}}, 514 515 {SVGA3D_X8L8V8U8, SVGA3DBLOCKDESC_UVL, 516 {1, 1, 1}, 4, 4, 517 {{8}, {8}, {8}, {0}}, 518 {{16}, {8}, {0}, {0}}}, 519 520 {SVGA3D_A2W10V10U10, SVGA3DBLOCKDESC_UVWA, 521 {1, 1, 1}, 4, 4, 522 {{10}, {10}, {10}, {2}}, 523 {{20}, {10}, {0}, {30}}}, 524 525 {SVGA3D_ALPHA8, SVGA3DBLOCKDESC_A_UNORM, 526 {1, 1, 1}, 1, 1, 527 {{0}, {0}, {0}, {8}}, 528 {{0}, {0}, {0}, {0}}}, 529 530 {SVGA3D_R_S10E5, SVGA3DBLOCKDESC_R_FP, 531 {1, 1, 1}, 2, 2, 532 {{0}, {0}, {16}, {0}}, 533 {{0}, {0}, {0}, {0}}}, 534 535 {SVGA3D_R_S23E8, SVGA3DBLOCKDESC_R_FP, 536 {1, 1, 1}, 4, 4, 537 {{0}, {0}, {32}, {0}}, 538 {{0}, {0}, {0}, {0}}}, 539 540 {SVGA3D_RG_S10E5, SVGA3DBLOCKDESC_RG_FP, 541 {1, 1, 1}, 4, 4, 542 {{0}, {16}, {16}, {0}}, 543 {{0}, {16}, {0}, {0}}}, 544 545 {SVGA3D_RG_S23E8, SVGA3DBLOCKDESC_RG_FP, 546 {1, 1, 1}, 8, 8, 547 {{0}, {32}, {32}, {0}}, 548 {{0}, {32}, {0}, {0}}}, 549 550 {SVGA3D_BUFFER, SVGA3DBLOCKDESC_BUFFER, 551 {1, 1, 1}, 1, 1, 552 {{0}, {0}, {8}, {0}}, 553 {{0}, {0}, {0}, {0}}}, 554 555 {SVGA3D_Z_D24X8, SVGA3DBLOCKDESC_DEPTH_UNORM, 556 {1, 1, 1}, 4, 4, 557 {{0}, {0}, {24}, {0}}, 558 {{0}, {0}, {8}, {0}}}, 559 560 {SVGA3D_V16U16, SVGA3DBLOCKDESC_UV_SNORM, 561 {1, 1, 1}, 4, 4, 562 {{0}, {16}, {16}, {0}}, 563 {{0}, {16}, {0}, {0}}}, 564 565 {SVGA3D_G16R16, SVGA3DBLOCKDESC_RG_UNORM, 566 {1, 1, 1}, 4, 4, 567 {{0}, {16}, {16}, {0}}, 568 {{0}, {16}, {0}, {0}}}, 569 570 {SVGA3D_A16B16G16R16, SVGA3DBLOCKDESC_RGBA_UNORM, 571 {1, 1, 1}, 8, 8, 572 {{16}, {16}, {16}, {16}}, 573 {{32}, {16}, {0}, {48}}}, 574 575 {SVGA3D_UYVY, SVGA3DBLOCKDESC_YUV, 576 {2, 1, 1}, 4, 4, 577 {{8}, {0}, {8}, {0}}, 578 {{0}, {0}, {8}, {0}}}, 579 580 {SVGA3D_YUY2, SVGA3DBLOCKDESC_YUV, 581 {2, 1, 1}, 4, 4, 582 {{8}, {0}, {8}, {0}}, 583 {{8}, {0}, {0}, {0}}}, 584 585 {SVGA3D_NV12, SVGA3DBLOCKDESC_NV12, 586 {2, 2, 1}, 6, 2, 587 {{0}, {0}, {48}, {0}}, 588 {{0}, {0}, {0}, {0}}}, 589 590 {SVGA3D_FORMAT_DEAD2, SVGA3DBLOCKDESC_NONE, 591 {1, 1, 1}, 4, 4, 592 {{8}, {8}, {8}, {8}}, 593 {{0}, {8}, {16}, {24}}}, 594 595 {SVGA3D_R32G32B32A32_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, 596 {1, 1, 1}, 16, 16, 597 {{32}, {32}, {32}, {32}}, 598 {{64}, {32}, {0}, {96}}}, 599 600 {SVGA3D_R32G32B32A32_UINT, SVGA3DBLOCKDESC_RGBA_UINT, 601 {1, 1, 1}, 16, 16, 602 {{32}, {32}, {32}, {32}}, 603 {{64}, {32}, {0}, {96}}}, 604 605 {SVGA3D_R32G32B32A32_SINT, SVGA3DBLOCKDESC_RGBA_SINT, 606 {1, 1, 1}, 16, 16, 607 {{32}, {32}, {32}, {32}}, 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SVGA3DBLOCKDESC_RG_SNORM, 1016 {1, 1, 1}, 4, 4, 1017 {{0}, {16}, {16}, {0}}, 1018 {{0}, {16}, {0}, {0}}}, 1019 1020 {SVGA3D_R32_FLOAT, SVGA3DBLOCKDESC_R_FP, 1021 {1, 1, 1}, 4, 4, 1022 {{0}, {0}, {32}, {0}}, 1023 {{0}, {0}, {0}, {0}}}, 1024 1025 {SVGA3D_R8G8_SNORM, SVGA3DBLOCKDESC_RG_SNORM, 1026 {1, 1, 1}, 2, 2, 1027 {{0}, {8}, {8}, {0}}, 1028 {{0}, {8}, {0}, {0}}}, 1029 1030 {SVGA3D_R16_FLOAT, SVGA3DBLOCKDESC_R_FP, 1031 {1, 1, 1}, 2, 2, 1032 {{0}, {0}, {16}, {0}}, 1033 {{0}, {0}, {0}, {0}}}, 1034 1035 {SVGA3D_D16_UNORM, SVGA3DBLOCKDESC_DEPTH_UNORM, 1036 {1, 1, 1}, 2, 2, 1037 {{0}, {0}, {16}, {0}}, 1038 {{0}, {0}, {0}, {0}}}, 1039 1040 {SVGA3D_A8_UNORM, SVGA3DBLOCKDESC_A_UNORM, 1041 {1, 1, 1}, 1, 1, 1042 {{0}, {0}, {0}, {8}}, 1043 {{0}, {0}, {0}, {0}}}, 1044 1045 {SVGA3D_BC1_UNORM, SVGA3DBLOCKDESC_BC1_COMP_UNORM, 1046 {4, 4, 1}, 8, 8, 1047 {{0}, {0}, {64}, {0}}, 1048 {{0}, {0}, {0}, {0}}}, 1049 1050 {SVGA3D_BC2_UNORM, SVGA3DBLOCKDESC_BC2_COMP_UNORM, 1051 {4, 4, 1}, 16, 16, 1052 {{0}, {0}, {128}, {0}}, 1053 {{0}, {0}, {0}, {0}}}, 1054 1055 {SVGA3D_BC3_UNORM, SVGA3DBLOCKDESC_BC3_COMP_UNORM, 1056 {4, 4, 1}, 16, 16, 1057 {{0}, {0}, {128}, {0}}, 1058 {{0}, {0}, {0}, {0}}}, 1059 1060 {SVGA3D_B5G6R5_UNORM, SVGA3DBLOCKDESC_RGB_UNORM, 1061 {1, 1, 1}, 2, 2, 1062 {{5}, {6}, {5}, {0}}, 1063 {{0}, {5}, {11}, {0}}}, 1064 1065 {SVGA3D_B5G5R5A1_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM, 1066 {1, 1, 1}, 2, 2, 1067 {{5}, {5}, {5}, {1}}, 1068 {{0}, {5}, {10}, {15}}}, 1069 1070 {SVGA3D_B8G8R8A8_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM, 1071 {1, 1, 1}, 4, 4, 1072 {{8}, {8}, {8}, {8}}, 1073 {{0}, {8}, {16}, {24}}}, 1074 1075 {SVGA3D_B8G8R8X8_UNORM, SVGA3DBLOCKDESC_RGB_UNORM, 1076 {1, 1, 1}, 4, 4, 1077 {{8}, {8}, {8}, {0}}, 1078 {{0}, {8}, {16}, {24}}}, 1079 1080 {SVGA3D_BC4_UNORM, SVGA3DBLOCKDESC_BC4_COMP_UNORM, 1081 {4, 4, 1}, 8, 8, 1082 {{0}, {0}, {64}, {0}}, 1083 {{0}, {0}, {0}, {0}}}, 1084 1085 {SVGA3D_BC5_UNORM, SVGA3DBLOCKDESC_BC5_COMP_UNORM, 1086 {4, 4, 1}, 16, 16, 1087 {{0}, {0}, {128}, {0}}, 1088 {{0}, {0}, {0}, {0}}}, 1089 1090 {SVGA3D_B4G4R4A4_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM, 1091 {1, 1, 1}, 2, 2, 1092 {{4}, {4}, {4}, {4}}, 1093 {{0}, {4}, {8}, {12}}}, 1094 1095 {SVGA3D_BC6H_TYPELESS, SVGA3DBLOCKDESC_BC6H_COMP_TYPELESS, 1096 {4, 4, 1}, 16, 16, 1097 {{0}, {0}, {128}, {0}}, 1098 {{0}, {0}, {0}, {0}}}, 1099 1100 {SVGA3D_BC6H_UF16, SVGA3DBLOCKDESC_BC6H_COMP_UF16, 1101 {4, 4, 1}, 16, 16, 1102 {{0}, {0}, {128}, {0}}, 1103 {{0}, {0}, {0}, {0}}}, 1104 1105 {SVGA3D_BC6H_SF16, SVGA3DBLOCKDESC_BC6H_COMP_SF16, 1106 {4, 4, 1}, 16, 16, 1107 {{0}, {0}, {128}, {0}}, 1108 {{0}, {0}, {0}, {0}}}, 1109 1110 {SVGA3D_BC7_TYPELESS, SVGA3DBLOCKDESC_BC7_COMP_TYPELESS, 1111 {4, 4, 1}, 16, 16, 1112 {{0}, {0}, {128}, {0}}, 1113 {{0}, {0}, {0}, {0}}}, 1114 1115 {SVGA3D_BC7_UNORM, SVGA3DBLOCKDESC_BC7_COMP_UNORM, 1116 {4, 4, 1}, 16, 16, 1117 {{0}, {0}, {128}, {0}}, 1118 {{0}, {0}, {0}, {0}}}, 1119 1120 {SVGA3D_BC7_UNORM_SRGB, SVGA3DBLOCKDESC_BC7_COMP_UNORM_SRGB, 1121 {4, 4, 1}, 16, 16, 1122 {{0}, {0}, {128}, {0}}, 1123 {{0}, {0}, {0}, {0}}}, 1124 1125 {SVGA3D_AYUV, SVGA3DBLOCKDESC_AYUV, 1126 {1, 1, 1}, 4, 4, 1127 {{8}, {8}, {8}, {8}}, 1128 {{0}, {8}, {16}, {24}}}, 1129 1130 {SVGA3D_R11G11B10_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, 1131 {1, 1, 1}, 4, 4, 1132 {{10}, {11}, {11}, {0}}, 1133 {{22}, {11}, {0}, {0}}}, 1134}; 1135 1136 1137 1138extern const struct svga3d_surface_desc g_SVGA3dSurfaceDescs[]; 1139extern int g_SVGA3dSurfaceDescs_size; 1140 1141static inline uint32 clamped_umul32(uint32 a, uint32 b) 1142{ 1143 uint64_t tmp = (uint64_t) a*b; 1144 return (tmp > (uint64_t) ((uint32) -1)) ? (uint32) -1 : tmp; 1145} 1146 1147static inline uint32 clamped_uadd32(uint32 a, uint32 b) 1148{ 1149 uint32 c = a + b; 1150 if (c < a || c < b) { 1151 return MAX_UINT32; 1152 } 1153 return c; 1154} 1155 1156 1157static inline const struct svga3d_surface_desc * 1158svga3dsurface_get_desc(SVGA3dSurfaceFormat format) 1159{ 1160 if (format < ARRAY_SIZE(svga3d_surface_descs)) 1161 return &svga3d_surface_descs[format]; 1162 1163 return &svga3d_surface_descs[SVGA3D_FORMAT_INVALID]; 1164} 1165 1166/* 1167 *---------------------------------------------------------------------- 1168 * 1169 * svga3dsurface_get_mip_size -- 1170 * 1171 * Given a base level size and the mip level, compute the size of 1172 * the mip level. 1173 * 1174 * Results: 1175 * See above. 1176 * 1177 * Side effects: 1178 * None. 1179 * 1180 *---------------------------------------------------------------------- 1181 */ 1182 1183static inline SVGA3dSize 1184svga3dsurface_get_mip_size(SVGA3dSize base_level, uint32 mip_level) 1185{ 1186 SVGA3dSize size; 1187 1188 size.width = max_t(uint32, base_level.width >> mip_level, 1); 1189 size.height = max_t(uint32, base_level.height >> mip_level, 1); 1190 size.depth = max_t(uint32, base_level.depth >> mip_level, 1); 1191 return size; 1192} 1193 1194static inline void 1195svga3dsurface_get_size_in_blocks(const struct svga3d_surface_desc *desc, 1196 const SVGA3dSize *pixel_size, 1197 SVGA3dSize *block_size) 1198{ 1199 block_size->width = DIV_ROUND_UP(pixel_size->width, 1200 desc->block_size.width); 1201 block_size->height = DIV_ROUND_UP(pixel_size->height, 1202 desc->block_size.height); 1203 block_size->depth = DIV_ROUND_UP(pixel_size->depth, 1204 desc->block_size.depth); 1205} 1206 1207static inline bool 1208svga3dsurface_is_planar_surface(const struct svga3d_surface_desc *desc) 1209{ 1210 return (desc->block_desc & SVGA3DBLOCKDESC_PLANAR_YUV) != 0; 1211} 1212 1213static inline uint32 1214svga3dsurface_calculate_pitch(const struct svga3d_surface_desc *desc, 1215 const SVGA3dSize *size) 1216{ 1217 uint32 pitch; 1218 SVGA3dSize blocks; 1219 1220 svga3dsurface_get_size_in_blocks(desc, size, &blocks); 1221 1222 pitch = blocks.width * desc->pitch_bytes_per_block; 1223 1224 return pitch; 1225} 1226 1227/* 1228 *----------------------------------------------------------------------------- 1229 * 1230 * svga3dsurface_get_image_buffer_size -- 1231 * 1232 * Return the number of bytes of buffer space required to store 1233 * one image of a surface, optionally using the specified pitch. 1234 * 1235 * If pitch is zero, it is assumed that rows are tightly packed. 1236 * 1237 * This function is overflow-safe. If the result would have 1238 * overflowed, instead we return MAX_UINT32. 1239 * 1240 * Results: 1241 * Byte count. 1242 * 1243 * Side effects: 1244 * None. 1245 * 1246 *----------------------------------------------------------------------------- 1247 */ 1248 1249static inline uint32 1250svga3dsurface_get_image_buffer_size(const struct svga3d_surface_desc *desc, 1251 const SVGA3dSize *size, 1252 uint32 pitch) 1253{ 1254 SVGA3dSize image_blocks; 1255 uint32 slice_size, total_size; 1256 1257 svga3dsurface_get_size_in_blocks(desc, size, &image_blocks); 1258 1259 if (svga3dsurface_is_planar_surface(desc)) { 1260 total_size = clamped_umul32(image_blocks.width, 1261 image_blocks.height); 1262 total_size = clamped_umul32(total_size, image_blocks.depth); 1263 total_size = clamped_umul32(total_size, desc->bytes_per_block); 1264 return total_size; 1265 } 1266 1267 if (pitch == 0) 1268 pitch = svga3dsurface_calculate_pitch(desc, size); 1269 1270 slice_size = clamped_umul32(image_blocks.height, pitch); 1271 total_size = clamped_umul32(slice_size, image_blocks.depth); 1272 1273 return total_size; 1274} 1275 1276 1277static inline uint32 1278svga3dsurface_get_image_offset(SVGA3dSurfaceFormat format, 1279 SVGA3dSize baseLevelSize, 1280 uint32 numMipLevels, 1281 uint32 layer, 1282 uint32 mip) 1283 1284{ 1285 uint32 offset; 1286 uint32 mipChainBytes; 1287 uint32 mipChainBytesToLevel; 1288 uint32 i; 1289 const struct svga3d_surface_desc *desc; 1290 SVGA3dSize mipSize; 1291 uint32 bytes; 1292 1293 desc = svga3dsurface_get_desc(format); 1294 1295 mipChainBytes = 0; 1296 mipChainBytesToLevel = 0; 1297 for (i = 0; i < numMipLevels; i++) { 1298 mipSize = svga3dsurface_get_mip_size(baseLevelSize, i); 1299 bytes = svga3dsurface_get_image_buffer_size(desc, &mipSize, 0); 1300 mipChainBytes += bytes; 1301 if (i < mip) { 1302 mipChainBytesToLevel += bytes; 1303 } 1304 } 1305 1306 offset = mipChainBytes * layer + mipChainBytesToLevel; 1307 1308 return offset; 1309} 1310 1311 1312static inline uint32 1313svga3dsurface_get_serialized_size(SVGA3dSurfaceFormat format, 1314 SVGA3dSize base_level_size, 1315 uint32 num_mip_levels, 1316 uint32 num_layers) 1317{ 1318 const struct svga3d_surface_desc *desc = svga3dsurface_get_desc(format); 1319 uint64_t total_size = 0; 1320 uint32 mip; 1321 1322 for (mip = 0; mip < num_mip_levels; mip++) { 1323 SVGA3dSize size = 1324 svga3dsurface_get_mip_size(base_level_size, mip); 1325 total_size += svga3dsurface_get_image_buffer_size(desc, 1326 &size, 0); 1327 } 1328 1329 total_size *= num_layers; 1330 1331 return (total_size > (uint64_t) MAX_UINT32) ? MAX_UINT32 : 1332 (uint32) total_size; 1333} 1334 1335 1336/** 1337 * svga3dsurface_get_serialized_size_extended - Returns the number of bytes 1338 * required for a surface with given parameters. Support for sample count. 1339 * 1340 */ 1341static inline uint32 1342svga3dsurface_get_serialized_size_extended(SVGA3dSurfaceFormat format, 1343 SVGA3dSize base_level_size, 1344 uint32 num_mip_levels, 1345 uint32 num_layers, 1346 uint32 num_samples) 1347{ 1348 uint64_t total_size = svga3dsurface_get_serialized_size(format, 1349 base_level_size, 1350 num_mip_levels, 1351 num_layers); 1352 1353 total_size *= (num_samples > 1 ? num_samples : 1); 1354 1355 return (total_size > (uint64_t) MAX_UINT32) ? MAX_UINT32 : 1356 (uint32) total_size; 1357} 1358 1359 1360/** 1361 * Compute the offset (in bytes) to a pixel in an image (or volume). 1362 * 'width' is the image width in pixels 1363 * 'height' is the image height in pixels 1364 */ 1365static inline uint32 1366svga3dsurface_get_pixel_offset(SVGA3dSurfaceFormat format, 1367 uint32 width, uint32 height, 1368 uint32 x, uint32 y, uint32 z) 1369{ 1370 const struct svga3d_surface_desc *desc = svga3dsurface_get_desc(format); 1371 const uint32 bw = desc->block_size.width, bh = desc->block_size.height; 1372 const uint32 bd = desc->block_size.depth; 1373 const uint32 rowstride = DIV_ROUND_UP(width, bw) * desc->bytes_per_block; 1374 const uint32 imgstride = DIV_ROUND_UP(height, bh) * rowstride; 1375 const uint32 offset = (z / bd * imgstride + 1376 y / bh * rowstride + 1377 x / bw * desc->bytes_per_block); 1378 return offset; 1379} 1380 1381#endif 1382