1/* SPDX-License-Identifier: GPL-2.0 OR MIT */ 2/* 3 * Copyright 2012-2022 VMware, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person 6 * obtaining a copy of this software and associated documentation 7 * files (the "Software"), to deal in the Software without 8 * restriction, including without limitation the rights to use, copy, 9 * modify, merge, publish, distribute, sublicense, and/or sell copies 10 * of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be 14 * included in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 17 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 19 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 20 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 21 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 23 * SOFTWARE. 24 * 25 */ 26 27/* 28 * VGPU10ShaderTokens.h -- 29 * 30 * VGPU10 shader token definitions. 31 */ 32 33 34 35 36 37#ifndef VGPU10SHADERTOKENS_H 38#define VGPU10SHADERTOKENS_H 39 40 41#define VGPU10_MAX_VS_INPUTS 16 42#define VGPU10_MAX_VS_OUTPUTS 16 43#define VGPU10_MAX_GS_INPUTS 16 44#define VGPU10_MAX_GS_OUTPUTS 32 45#define VGPU10_MAX_FS_INPUTS 32 46#define VGPU10_MAX_FS_OUTPUTS 8 47#define VGPU10_MAX_TEMPS 4096 48#define VGPU10_MAX_CONSTANT_BUFFERS (14 + 1) 49#define VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT 4096 50#define VGPU10_MAX_IMMEDIATE_CONSTANT_BUFFER_ELEMENT_COUNT 4096 51#define VGPU10_MAX_SAMPLERS 16 52#define VGPU10_MAX_RESOURCES 128 53#define VGPU10_MIN_TEXEL_FETCH_OFFSET -8 54#define VGPU10_MAX_TEXEL_FETCH_OFFSET 7 55 56 57#define VGPU10_1_MAX_VS_INPUTS 32 58#define VGPU10_1_MAX_VS_OUTPUTS 32 59#define VGPU10_1_MAX_GS_INPUTS 32 60 61 62#define VGPU11_MAX_HS_INPUT_CONTROL_POINTS 32 63#define VGPU11_MAX_HS_INPUT_PATCH_CONSTANTS 32 64#define VGPU11_MAX_HS_OUTPUT_CP_PHASE_ELEMENTS 32 65#define VGPU11_MAX_HS_OUTPUT_CONTROL_POINTS 32 66#define VGPU11_MAX_HS_OUTPUTS 32 67#define VGPU11_MAX_DS_INPUT_CONTROL_POINTS 32 68#define VGPU11_MAX_DS_INPUT_PATCH_CONSTANTS 32 69#define VGPU11_MAX_DS_OUTPUTS 32 70#define VGPU11_MAX_GS_STREAMS 4 71#define VGPU11_MAX_FUNCTION_BODIES 256 72#define VGPU11_MAX_FUNCTION_TABLES 256 73#define VGPU11_MAX_INTERFACES 253 74 75 76#define VGPU10_MAX_INPUTS 32 77#define VGPU10_MAX_OUTPUTS 32 78#define VGPU10_MAX_INPUT_PATCH_CONSTANTS 32 79 80typedef enum { 81 VGPU10_PIXEL_SHADER = 0, 82 VGPU10_VERTEX_SHADER = 1, 83 VGPU10_GEOMETRY_SHADER = 2, 84 85 86 VGPU10_HULL_SHADER = 3, 87 VGPU10_DOMAIN_SHADER = 4, 88 VGPU10_COMPUTE_SHADER = 5 89} VGPU10_PROGRAM_TYPE; 90 91typedef union { 92 struct { 93 unsigned int minorVersion : 4; 94 unsigned int majorVersion : 4; 95 unsigned int : 8; 96 unsigned int programType : 16; 97 }; 98 uint32 value; 99} VGPU10ProgramToken; 100 101 102typedef enum { 103 VGPU10_OPCODE_ADD = 0, 104 VGPU10_OPCODE_AND = 1, 105 VGPU10_OPCODE_BREAK = 2, 106 VGPU10_OPCODE_BREAKC = 3, 107 VGPU10_OPCODE_CALL = 4, 108 VGPU10_OPCODE_CALLC = 5, 109 VGPU10_OPCODE_CASE = 6, 110 VGPU10_OPCODE_CONTINUE = 7, 111 VGPU10_OPCODE_CONTINUEC = 8, 112 VGPU10_OPCODE_CUT = 9, 113 VGPU10_OPCODE_DEFAULT = 10, 114 VGPU10_OPCODE_DERIV_RTX = 11, 115 VGPU10_OPCODE_DERIV_RTY = 12, 116 VGPU10_OPCODE_DISCARD = 13, 117 VGPU10_OPCODE_DIV = 14, 118 VGPU10_OPCODE_DP2 = 15, 119 VGPU10_OPCODE_DP3 = 16, 120 VGPU10_OPCODE_DP4 = 17, 121 VGPU10_OPCODE_ELSE = 18, 122 VGPU10_OPCODE_EMIT = 19, 123 VGPU10_OPCODE_EMITTHENCUT = 20, 124 VGPU10_OPCODE_ENDIF = 21, 125 VGPU10_OPCODE_ENDLOOP = 22, 126 VGPU10_OPCODE_ENDSWITCH = 23, 127 VGPU10_OPCODE_EQ = 24, 128 VGPU10_OPCODE_EXP = 25, 129 VGPU10_OPCODE_FRC = 26, 130 VGPU10_OPCODE_FTOI = 27, 131 VGPU10_OPCODE_FTOU = 28, 132 VGPU10_OPCODE_GE = 29, 133 VGPU10_OPCODE_IADD = 30, 134 VGPU10_OPCODE_IF = 31, 135 VGPU10_OPCODE_IEQ = 32, 136 VGPU10_OPCODE_IGE = 33, 137 VGPU10_OPCODE_ILT = 34, 138 VGPU10_OPCODE_IMAD = 35, 139 VGPU10_OPCODE_IMAX = 36, 140 VGPU10_OPCODE_IMIN = 37, 141 VGPU10_OPCODE_IMUL = 38, 142 VGPU10_OPCODE_INE = 39, 143 VGPU10_OPCODE_INEG = 40, 144 VGPU10_OPCODE_ISHL = 41, 145 VGPU10_OPCODE_ISHR = 42, 146 VGPU10_OPCODE_ITOF = 43, 147 VGPU10_OPCODE_LABEL = 44, 148 VGPU10_OPCODE_LD = 45, 149 VGPU10_OPCODE_LD_MS = 46, 150 VGPU10_OPCODE_LOG = 47, 151 VGPU10_OPCODE_LOOP = 48, 152 VGPU10_OPCODE_LT = 49, 153 VGPU10_OPCODE_MAD = 50, 154 VGPU10_OPCODE_MIN = 51, 155 VGPU10_OPCODE_MAX = 52, 156 VGPU10_OPCODE_CUSTOMDATA = 53, 157 VGPU10_OPCODE_MOV = 54, 158 VGPU10_OPCODE_MOVC = 55, 159 VGPU10_OPCODE_MUL = 56, 160 VGPU10_OPCODE_NE = 57, 161 VGPU10_OPCODE_NOP = 58, 162 VGPU10_OPCODE_NOT = 59, 163 VGPU10_OPCODE_OR = 60, 164 VGPU10_OPCODE_RESINFO = 61, 165 VGPU10_OPCODE_RET = 62, 166 VGPU10_OPCODE_RETC = 63, 167 VGPU10_OPCODE_ROUND_NE = 64, 168 VGPU10_OPCODE_ROUND_NI = 65, 169 VGPU10_OPCODE_ROUND_PI = 66, 170 VGPU10_OPCODE_ROUND_Z = 67, 171 VGPU10_OPCODE_RSQ = 68, 172 VGPU10_OPCODE_SAMPLE = 69, 173 VGPU10_OPCODE_SAMPLE_C = 70, 174 VGPU10_OPCODE_SAMPLE_C_LZ = 71, 175 VGPU10_OPCODE_SAMPLE_L = 72, 176 VGPU10_OPCODE_SAMPLE_D = 73, 177 VGPU10_OPCODE_SAMPLE_B = 74, 178 VGPU10_OPCODE_SQRT = 75, 179 VGPU10_OPCODE_SWITCH = 76, 180 VGPU10_OPCODE_SINCOS = 77, 181 VGPU10_OPCODE_UDIV = 78, 182 VGPU10_OPCODE_ULT = 79, 183 VGPU10_OPCODE_UGE = 80, 184 VGPU10_OPCODE_UMUL = 81, 185 VGPU10_OPCODE_UMAD = 82, 186 VGPU10_OPCODE_UMAX = 83, 187 VGPU10_OPCODE_UMIN = 84, 188 VGPU10_OPCODE_USHR = 85, 189 VGPU10_OPCODE_UTOF = 86, 190 VGPU10_OPCODE_XOR = 87, 191 VGPU10_OPCODE_DCL_RESOURCE = 88, 192 VGPU10_OPCODE_DCL_CONSTANT_BUFFER = 89, 193 VGPU10_OPCODE_DCL_SAMPLER = 90, 194 VGPU10_OPCODE_DCL_INDEX_RANGE = 91, 195 VGPU10_OPCODE_DCL_GS_OUTPUT_PRIMITIVE_TOPOLOGY = 92, 196 VGPU10_OPCODE_DCL_GS_INPUT_PRIMITIVE = 93, 197 VGPU10_OPCODE_DCL_MAX_OUTPUT_VERTEX_COUNT = 94, 198 VGPU10_OPCODE_DCL_INPUT = 95, 199 VGPU10_OPCODE_DCL_INPUT_SGV = 96, 200 VGPU10_OPCODE_DCL_INPUT_SIV = 97, 201 VGPU10_OPCODE_DCL_INPUT_PS = 98, 202 VGPU10_OPCODE_DCL_INPUT_PS_SGV = 99, 203 VGPU10_OPCODE_DCL_INPUT_PS_SIV = 100, 204 VGPU10_OPCODE_DCL_OUTPUT = 101, 205 VGPU10_OPCODE_DCL_OUTPUT_SGV = 102, 206 VGPU10_OPCODE_DCL_OUTPUT_SIV = 103, 207 VGPU10_OPCODE_DCL_TEMPS = 104, 208 VGPU10_OPCODE_DCL_INDEXABLE_TEMP = 105, 209 VGPU10_OPCODE_DCL_GLOBAL_FLAGS = 106, 210 211 212 VGPU10_OPCODE_VMWARE = 107, 213 214 215 VGPU10_OPCODE_LOD = 108, 216 VGPU10_OPCODE_GATHER4 = 109, 217 VGPU10_OPCODE_SAMPLE_POS = 110, 218 VGPU10_OPCODE_SAMPLE_INFO = 111, 219 220 221 VGPU10_OPCODE_RESERVED1 = 112, 222 VGPU10_OPCODE_HS_DECLS = 113, 223 VGPU10_OPCODE_HS_CONTROL_POINT_PHASE = 114, 224 VGPU10_OPCODE_HS_FORK_PHASE = 115, 225 VGPU10_OPCODE_HS_JOIN_PHASE = 116, 226 VGPU10_OPCODE_EMIT_STREAM = 117, 227 VGPU10_OPCODE_CUT_STREAM = 118, 228 VGPU10_OPCODE_EMITTHENCUT_STREAM = 119, 229 VGPU10_OPCODE_INTERFACE_CALL = 120, 230 VGPU10_OPCODE_BUFINFO = 121, 231 VGPU10_OPCODE_DERIV_RTX_COARSE = 122, 232 VGPU10_OPCODE_DERIV_RTX_FINE = 123, 233 VGPU10_OPCODE_DERIV_RTY_COARSE = 124, 234 VGPU10_OPCODE_DERIV_RTY_FINE = 125, 235 VGPU10_OPCODE_GATHER4_C = 126, 236 VGPU10_OPCODE_GATHER4_PO = 127, 237 VGPU10_OPCODE_GATHER4_PO_C = 128, 238 VGPU10_OPCODE_RCP = 129, 239 VGPU10_OPCODE_F32TOF16 = 130, 240 VGPU10_OPCODE_F16TOF32 = 131, 241 VGPU10_OPCODE_UADDC = 132, 242 VGPU10_OPCODE_USUBB = 133, 243 VGPU10_OPCODE_COUNTBITS = 134, 244 VGPU10_OPCODE_FIRSTBIT_HI = 135, 245 VGPU10_OPCODE_FIRSTBIT_LO = 136, 246 VGPU10_OPCODE_FIRSTBIT_SHI = 137, 247 VGPU10_OPCODE_UBFE = 138, 248 VGPU10_OPCODE_IBFE = 139, 249 VGPU10_OPCODE_BFI = 140, 250 VGPU10_OPCODE_BFREV = 141, 251 VGPU10_OPCODE_SWAPC = 142, 252 VGPU10_OPCODE_DCL_STREAM = 143, 253 VGPU10_OPCODE_DCL_FUNCTION_BODY = 144, 254 VGPU10_OPCODE_DCL_FUNCTION_TABLE = 145, 255 VGPU10_OPCODE_DCL_INTERFACE = 146, 256 VGPU10_OPCODE_DCL_INPUT_CONTROL_POINT_COUNT = 147, 257 VGPU10_OPCODE_DCL_OUTPUT_CONTROL_POINT_COUNT = 148, 258 VGPU10_OPCODE_DCL_TESS_DOMAIN = 149, 259 VGPU10_OPCODE_DCL_TESS_PARTITIONING = 150, 260 VGPU10_OPCODE_DCL_TESS_OUTPUT_PRIMITIVE = 151, 261 VGPU10_OPCODE_DCL_HS_MAX_TESSFACTOR = 152, 262 VGPU10_OPCODE_DCL_HS_FORK_PHASE_INSTANCE_COUNT = 153, 263 VGPU10_OPCODE_DCL_HS_JOIN_PHASE_INSTANCE_COUNT = 154, 264 VGPU10_OPCODE_DCL_THREAD_GROUP = 155, 265 VGPU10_OPCODE_DCL_UAV_TYPED = 156, 266 VGPU10_OPCODE_DCL_UAV_RAW = 157, 267 VGPU10_OPCODE_DCL_UAV_STRUCTURED = 158, 268 VGPU10_OPCODE_DCL_TGSM_RAW = 159, 269 VGPU10_OPCODE_DCL_TGSM_STRUCTURED = 160, 270 VGPU10_OPCODE_DCL_RESOURCE_RAW = 161, 271 VGPU10_OPCODE_DCL_RESOURCE_STRUCTURED = 162, 272 VGPU10_OPCODE_LD_UAV_TYPED = 163, 273 VGPU10_OPCODE_STORE_UAV_TYPED = 164, 274 VGPU10_OPCODE_LD_RAW = 165, 275 VGPU10_OPCODE_STORE_RAW = 166, 276 VGPU10_OPCODE_LD_STRUCTURED = 167, 277 VGPU10_OPCODE_STORE_STRUCTURED = 168, 278 VGPU10_OPCODE_ATOMIC_AND = 169, 279 VGPU10_OPCODE_ATOMIC_OR = 170, 280 VGPU10_OPCODE_ATOMIC_XOR = 171, 281 VGPU10_OPCODE_ATOMIC_CMP_STORE = 172, 282 VGPU10_OPCODE_ATOMIC_IADD = 173, 283 VGPU10_OPCODE_ATOMIC_IMAX = 174, 284 VGPU10_OPCODE_ATOMIC_IMIN = 175, 285 VGPU10_OPCODE_ATOMIC_UMAX = 176, 286 VGPU10_OPCODE_ATOMIC_UMIN = 177, 287 VGPU10_OPCODE_IMM_ATOMIC_ALLOC = 178, 288 VGPU10_OPCODE_IMM_ATOMIC_CONSUME = 179, 289 VGPU10_OPCODE_IMM_ATOMIC_IADD = 180, 290 VGPU10_OPCODE_IMM_ATOMIC_AND = 181, 291 VGPU10_OPCODE_IMM_ATOMIC_OR = 182, 292 VGPU10_OPCODE_IMM_ATOMIC_XOR = 183, 293 VGPU10_OPCODE_IMM_ATOMIC_EXCH = 184, 294 VGPU10_OPCODE_IMM_ATOMIC_CMP_EXCH = 185, 295 VGPU10_OPCODE_IMM_ATOMIC_IMAX = 186, 296 VGPU10_OPCODE_IMM_ATOMIC_IMIN = 187, 297 VGPU10_OPCODE_IMM_ATOMIC_UMAX = 188, 298 VGPU10_OPCODE_IMM_ATOMIC_UMIN = 189, 299 VGPU10_OPCODE_SYNC = 190, 300 VGPU10_OPCODE_DADD = 191, 301 VGPU10_OPCODE_DMAX = 192, 302 VGPU10_OPCODE_DMIN = 193, 303 VGPU10_OPCODE_DMUL = 194, 304 VGPU10_OPCODE_DEQ = 195, 305 VGPU10_OPCODE_DGE = 196, 306 VGPU10_OPCODE_DLT = 197, 307 VGPU10_OPCODE_DNE = 198, 308 VGPU10_OPCODE_DMOV = 199, 309 VGPU10_OPCODE_DMOVC = 200, 310 VGPU10_OPCODE_DTOF = 201, 311 VGPU10_OPCODE_FTOD = 202, 312 VGPU10_OPCODE_EVAL_SNAPPED = 203, 313 VGPU10_OPCODE_EVAL_SAMPLE_INDEX = 204, 314 VGPU10_OPCODE_EVAL_CENTROID = 205, 315 VGPU10_OPCODE_DCL_GS_INSTANCE_COUNT = 206, 316 VGPU10_OPCODE_ABORT = 207, 317 VGPU10_OPCODE_DEBUG_BREAK = 208, 318 319 320 VGPU10_OPCODE_RESERVED0 = 209, 321 VGPU10_OPCODE_DDIV = 210, 322 VGPU10_OPCODE_DFMA = 211, 323 VGPU10_OPCODE_DRCP = 212, 324 VGPU10_OPCODE_MSAD = 213, 325 VGPU10_OPCODE_DTOI = 214, 326 VGPU10_OPCODE_DTOU = 215, 327 VGPU10_OPCODE_ITOD = 216, 328 VGPU10_OPCODE_UTOD = 217, 329 330 VGPU10_NUM_OPCODES 331} VGPU10_OPCODE_TYPE; 332 333 334typedef enum { 335 VGPU10_VMWARE_OPCODE_IDIV = 0, 336 VGPU10_VMWARE_OPCODE_DFRC = 1, 337 VGPU10_VMWARE_OPCODE_DRSQ = 2, 338 VGPU10_VMWARE_NUM_OPCODES 339} VGPU10_VMWARE_OPCODE_TYPE; 340 341typedef enum { 342 VGPU10_INTERPOLATION_UNDEFINED = 0, 343 VGPU10_INTERPOLATION_CONSTANT = 1, 344 VGPU10_INTERPOLATION_LINEAR = 2, 345 VGPU10_INTERPOLATION_LINEAR_CENTROID = 3, 346 VGPU10_INTERPOLATION_LINEAR_NOPERSPECTIVE = 4, 347 VGPU10_INTERPOLATION_LINEAR_NOPERSPECTIVE_CENTROID = 5, 348 VGPU10_INTERPOLATION_LINEAR_SAMPLE = 6, 349 VGPU10_INTERPOLATION_LINEAR_NOPERSPECTIVE_SAMPLE = 7 350} VGPU10_INTERPOLATION_MODE; 351 352typedef enum { 353 VGPU10_RESOURCE_DIMENSION_UNKNOWN = 0, 354 VGPU10_RESOURCE_DIMENSION_BUFFER = 1, 355 VGPU10_RESOURCE_DIMENSION_TEXTURE1D = 2, 356 VGPU10_RESOURCE_DIMENSION_TEXTURE2D = 3, 357 VGPU10_RESOURCE_DIMENSION_TEXTURE2DMS = 4, 358 VGPU10_RESOURCE_DIMENSION_TEXTURE3D = 5, 359 VGPU10_RESOURCE_DIMENSION_TEXTURECUBE = 6, 360 VGPU10_RESOURCE_DIMENSION_TEXTURE1DARRAY = 7, 361 VGPU10_RESOURCE_DIMENSION_TEXTURE2DARRAY = 8, 362 VGPU10_RESOURCE_DIMENSION_TEXTURE2DMSARRAY = 9, 363 VGPU10_RESOURCE_DIMENSION_TEXTURECUBEARRAY = 10, 364 365 366 VGPU10_RESOURCE_DIMENSION_RAW_BUFFER = 11, 367 VGPU10_RESOURCE_DIMENSION_STRUCTURED_BUFFER = 12, 368 VGPU10_RESOURCE_DIMENSION_MAX = 12 369} VGPU10_RESOURCE_DIMENSION; 370 371typedef enum { 372 VGPU10_SAMPLER_MODE_DEFAULT = 0, 373 VGPU10_SAMPLER_MODE_COMPARISON = 1, 374 VGPU10_SAMPLER_MODE_MONO = 2 375} VGPU10_SAMPLER_MODE; 376 377typedef enum { 378 VGPU10_INSTRUCTION_TEST_ZERO = 0, 379 VGPU10_INSTRUCTION_TEST_NONZERO = 1 380} VGPU10_INSTRUCTION_TEST_BOOLEAN; 381 382typedef enum { 383 VGPU10_CB_IMMEDIATE_INDEXED = 0, 384 VGPU10_CB_DYNAMIC_INDEXED = 1 385} VGPU10_CB_ACCESS_PATTERN; 386 387typedef enum { 388 VGPU10_PRIMITIVE_UNDEFINED = 0, 389 VGPU10_PRIMITIVE_POINT = 1, 390 VGPU10_PRIMITIVE_LINE = 2, 391 VGPU10_PRIMITIVE_TRIANGLE = 3, 392 VGPU10_PRIMITIVE_LINE_ADJ = 6, 393 VGPU10_PRIMITIVE_TRIANGLE_ADJ = 7, 394 VGPU10_PRIMITIVE_SM40_MAX = 7, 395 396 397 VGPU10_PRIMITIVE_1_CONTROL_POINT_PATCH = 8, 398 VGPU10_PRIMITIVE_2_CONTROL_POINT_PATCH = 9, 399 VGPU10_PRIMITIVE_3_CONTROL_POINT_PATCH = 10, 400 VGPU10_PRIMITIVE_4_CONTROL_POINT_PATCH = 11, 401 VGPU10_PRIMITIVE_5_CONTROL_POINT_PATCH = 12, 402 VGPU10_PRIMITIVE_6_CONTROL_POINT_PATCH = 13, 403 VGPU10_PRIMITIVE_7_CONTROL_POINT_PATCH = 14, 404 VGPU10_PRIMITIVE_8_CONTROL_POINT_PATCH = 15, 405 VGPU10_PRIMITIVE_9_CONTROL_POINT_PATCH = 16, 406 VGPU10_PRIMITIVE_10_CONTROL_POINT_PATCH = 17, 407 VGPU10_PRIMITIVE_11_CONTROL_POINT_PATCH = 18, 408 VGPU10_PRIMITIVE_12_CONTROL_POINT_PATCH = 19, 409 VGPU10_PRIMITIVE_13_CONTROL_POINT_PATCH = 20, 410 VGPU10_PRIMITIVE_14_CONTROL_POINT_PATCH = 21, 411 VGPU10_PRIMITIVE_15_CONTROL_POINT_PATCH = 22, 412 VGPU10_PRIMITIVE_16_CONTROL_POINT_PATCH = 23, 413 VGPU10_PRIMITIVE_17_CONTROL_POINT_PATCH = 24, 414 VGPU10_PRIMITIVE_18_CONTROL_POINT_PATCH = 25, 415 VGPU10_PRIMITIVE_19_CONTROL_POINT_PATCH = 26, 416 VGPU10_PRIMITIVE_20_CONTROL_POINT_PATCH = 27, 417 VGPU10_PRIMITIVE_21_CONTROL_POINT_PATCH = 28, 418 VGPU10_PRIMITIVE_22_CONTROL_POINT_PATCH = 29, 419 VGPU10_PRIMITIVE_23_CONTROL_POINT_PATCH = 30, 420 VGPU10_PRIMITIVE_24_CONTROL_POINT_PATCH = 31, 421 VGPU10_PRIMITIVE_25_CONTROL_POINT_PATCH = 32, 422 VGPU10_PRIMITIVE_26_CONTROL_POINT_PATCH = 33, 423 VGPU10_PRIMITIVE_27_CONTROL_POINT_PATCH = 34, 424 VGPU10_PRIMITIVE_28_CONTROL_POINT_PATCH = 35, 425 VGPU10_PRIMITIVE_29_CONTROL_POINT_PATCH = 36, 426 VGPU10_PRIMITIVE_30_CONTROL_POINT_PATCH = 37, 427 VGPU10_PRIMITIVE_31_CONTROL_POINT_PATCH = 38, 428 VGPU10_PRIMITIVE_32_CONTROL_POINT_PATCH = 39, 429 VGPU10_PRIMITIVE_MAX = 39 430} VGPU10_PRIMITIVE; 431 432typedef enum { 433 VGPU10_PRIMITIVE_TOPOLOGY_UNDEFINED = 0, 434 VGPU10_PRIMITIVE_TOPOLOGY_POINTLIST = 1, 435 VGPU10_PRIMITIVE_TOPOLOGY_LINELIST = 2, 436 VGPU10_PRIMITIVE_TOPOLOGY_LINESTRIP = 3, 437 VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLELIST = 4, 438 VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLESTRIP = 5, 439 VGPU10_PRIMITIVE_TOPOLOGY_LINELIST_ADJ = 10, 440 VGPU10_PRIMITIVE_TOPOLOGY_LINESTRIP_ADJ = 11, 441 VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLELIST_ADJ = 12, 442 VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLESTRIP_ADJ = 13 443} VGPU10_PRIMITIVE_TOPOLOGY; 444 445typedef enum { 446 VGPU10_CUSTOMDATA_COMMENT = 0, 447 VGPU10_CUSTOMDATA_DEBUGINFO = 1, 448 VGPU10_CUSTOMDATA_OPAQUE = 2, 449 VGPU10_CUSTOMDATA_DCL_IMMEDIATE_CONSTANT_BUFFER = 3 450} VGPU10_CUSTOMDATA_CLASS; 451 452typedef enum { 453 VGPU10_RESINFO_RETURN_FLOAT = 0, 454 VGPU10_RESINFO_RETURN_RCPFLOAT = 1, 455 VGPU10_RESINFO_RETURN_UINT = 2 456} VGPU10_RESINFO_RETURN_TYPE; 457 458 459typedef enum { 460 VGPU10_INSTRUCTION_RETURN_FLOAT = 0, 461 VGPU10_INSTRUCTION_RETURN_UINT = 1 462} VGPU10_INSTRUCTION_RETURN_TYPE; 463 464 465typedef enum { 466 VGPU10_TESSELLATOR_DOMAIN_UNDEFINED = 0, 467 VGPU10_TESSELLATOR_DOMAIN_ISOLINE = 1, 468 VGPU10_TESSELLATOR_DOMAIN_TRI = 2, 469 VGPU10_TESSELLATOR_DOMAIN_QUAD = 3, 470 VGPU10_TESSELLATOR_DOMAIN_MAX = 3 471} VGPU10_TESSELLATOR_DOMAIN; 472 473 474typedef enum { 475 VGPU10_TESSELLATOR_PARTITIONING_UNDEFINED = 0, 476 VGPU10_TESSELLATOR_PARTITIONING_INTEGER = 1, 477 VGPU10_TESSELLATOR_PARTITIONING_POW2 = 2, 478 VGPU10_TESSELLATOR_PARTITIONING_FRACTIONAL_ODD = 3, 479 VGPU10_TESSELLATOR_PARTITIONING_FRACTIONAL_EVEN = 4, 480 VGPU10_TESSELLATOR_PARTITIONING_MAX = 4 481} VGPU10_TESSELLATOR_PARTITIONING; 482 483 484typedef enum { 485 VGPU10_TESSELLATOR_OUTPUT_UNDEFINED = 0, 486 VGPU10_TESSELLATOR_OUTPUT_POINT = 1, 487 VGPU10_TESSELLATOR_OUTPUT_LINE = 2, 488 VGPU10_TESSELLATOR_OUTPUT_TRIANGLE_CW = 3, 489 VGPU10_TESSELLATOR_OUTPUT_TRIANGLE_CCW = 4, 490 VGPU10_TESSELLATOR_OUTPUT_MAX = 4 491} VGPU10_TESSELLATOR_OUTPUT_PRIMITIVE; 492 493typedef union { 494 struct { 495 unsigned int opcodeType : 11; 496 unsigned int interpolationMode : 4; 497 unsigned int : 3; 498 unsigned int testBoolean : 1; 499 unsigned int preciseValues : 4; 500 unsigned int : 1; 501 unsigned int instructionLength : 7; 502 unsigned int extended : 1; 503 }; 504 505 struct { 506 unsigned int : 11; 507 unsigned int vmwareOpcodeType : 4; 508 }; 509 struct { 510 unsigned int : 11; 511 unsigned int resourceDimension : 5; 512 unsigned int sampleCount : 7; 513 }; 514 struct { 515 unsigned int : 11; 516 unsigned int samplerMode : 4; 517 }; 518 struct { 519 unsigned int : 11; 520 unsigned int accessPattern : 1; 521 }; 522 struct { 523 unsigned int : 11; 524 unsigned int primitive : 6; 525 }; 526 struct { 527 unsigned int : 11; 528 unsigned int primitiveTopology : 7; 529 }; 530 struct { 531 unsigned int : 11; 532 unsigned int customDataClass : 21; 533 }; 534 struct { 535 unsigned int : 11; 536 unsigned int resinfoReturnType : 2; 537 unsigned int saturate : 1; 538 }; 539 struct { 540 unsigned int : 11; 541 unsigned int refactoringAllowed : 1; 542 543 544 unsigned int enableDoublePrecisionFloatOps : 1; 545 unsigned int forceEarlyDepthStencil : 1; 546 unsigned int enableRawAndStructuredBuffers : 1; 547 }; 548 struct { 549 unsigned int : 11; 550 unsigned int instReturnType : 2; 551 }; 552 553 554 struct { 555 unsigned int : 11; 556 unsigned int syncThreadsInGroup : 1; 557 unsigned int syncThreadGroupShared : 1; 558 unsigned int syncUAVMemoryGroup : 1; 559 unsigned int syncUAVMemoryGlobal : 1; 560 }; 561 struct { 562 unsigned int : 11; 563 unsigned int controlPointCount : 6; 564 }; 565 struct { 566 unsigned int : 11; 567 unsigned int tessDomain : 2; 568 }; 569 struct { 570 unsigned int : 11; 571 unsigned int tessPartitioning : 3; 572 }; 573 struct { 574 unsigned int : 11; 575 unsigned int tessOutputPrimitive : 3; 576 }; 577 struct { 578 unsigned int : 11; 579 unsigned int interfaceIndexedDynamically : 1; 580 }; 581 struct { 582 unsigned int : 11; 583 unsigned int uavResourceDimension : 5; 584 unsigned int globallyCoherent : 1; 585 unsigned int : 6; 586 unsigned int uavHasCounter : 1; 587 }; 588 uint32 value; 589} VGPU10OpcodeToken0; 590 591 592typedef enum { 593 VGPU10_EXTENDED_OPCODE_EMPTY = 0, 594 VGPU10_EXTENDED_OPCODE_SAMPLE_CONTROLS = 1, 595 596 597 VGPU10_EXTENDED_OPCODE_RESOURCE_DIM = 2, 598 VGPU10_EXTENDED_OPCODE_RESOURCE_RETURN_TYPE = 3 599} VGPU10_EXTENDED_OPCODE_TYPE; 600 601typedef union { 602 struct { 603 unsigned int opcodeType : 6; 604 unsigned int : 3; 605 unsigned int offsetU : 4; 606 unsigned int offsetV : 4; 607 unsigned int offsetW : 4; 608 unsigned int : 10; 609 unsigned int extended : 1; 610 }; 611 612 613 struct { 614 unsigned int : 6; 615 unsigned int resourceDimension : 5; 616 }; 617 struct { 618 unsigned int : 6; 619 unsigned int resourceReturnTypeX : 4; 620 unsigned int resourceReturnTypeY : 4; 621 unsigned int resourceReturnTypeZ : 4; 622 unsigned int resourceReturnTypeW : 4; 623 }; 624 uint32 value; 625} VGPU10OpcodeToken1; 626 627 628typedef enum { 629 VGPU10_OPERAND_0_COMPONENT = 0, 630 VGPU10_OPERAND_1_COMPONENT = 1, 631 VGPU10_OPERAND_4_COMPONENT = 2, 632 VGPU10_OPERAND_N_COMPONENT = 3 633} VGPU10_OPERAND_NUM_COMPONENTS; 634 635typedef enum { 636 VGPU10_OPERAND_4_COMPONENT_MASK_MODE = 0, 637 VGPU10_OPERAND_4_COMPONENT_SWIZZLE_MODE = 1, 638 VGPU10_OPERAND_4_COMPONENT_SELECT_1_MODE = 2 639} VGPU10_OPERAND_4_COMPONENT_SELECTION_MODE; 640 641#define VGPU10_OPERAND_4_COMPONENT_MASK_X 0x1 642#define VGPU10_OPERAND_4_COMPONENT_MASK_Y 0x2 643#define VGPU10_OPERAND_4_COMPONENT_MASK_Z 0x4 644#define VGPU10_OPERAND_4_COMPONENT_MASK_W 0x8 645 646#define VGPU10_OPERAND_4_COMPONENT_MASK_XY (VGPU10_OPERAND_4_COMPONENT_MASK_X | VGPU10_OPERAND_4_COMPONENT_MASK_Y) 647#define VGPU10_OPERAND_4_COMPONENT_MASK_XZ (VGPU10_OPERAND_4_COMPONENT_MASK_X | VGPU10_OPERAND_4_COMPONENT_MASK_Z) 648#define VGPU10_OPERAND_4_COMPONENT_MASK_XW (VGPU10_OPERAND_4_COMPONENT_MASK_X | VGPU10_OPERAND_4_COMPONENT_MASK_W) 649#define VGPU10_OPERAND_4_COMPONENT_MASK_YZ (VGPU10_OPERAND_4_COMPONENT_MASK_Y | VGPU10_OPERAND_4_COMPONENT_MASK_Z) 650#define VGPU10_OPERAND_4_COMPONENT_MASK_YW (VGPU10_OPERAND_4_COMPONENT_MASK_Y | VGPU10_OPERAND_4_COMPONENT_MASK_W) 651#define VGPU10_OPERAND_4_COMPONENT_MASK_ZW (VGPU10_OPERAND_4_COMPONENT_MASK_Z | VGPU10_OPERAND_4_COMPONENT_MASK_W) 652#define VGPU10_OPERAND_4_COMPONENT_MASK_XYZ (VGPU10_OPERAND_4_COMPONENT_MASK_XY | VGPU10_OPERAND_4_COMPONENT_MASK_Z) 653#define VGPU10_OPERAND_4_COMPONENT_MASK_XYW (VGPU10_OPERAND_4_COMPONENT_MASK_XY | VGPU10_OPERAND_4_COMPONENT_MASK_W) 654#define VGPU10_OPERAND_4_COMPONENT_MASK_XZW (VGPU10_OPERAND_4_COMPONENT_MASK_XZ | VGPU10_OPERAND_4_COMPONENT_MASK_W) 655#define VGPU10_OPERAND_4_COMPONENT_MASK_YZW (VGPU10_OPERAND_4_COMPONENT_MASK_YZ | VGPU10_OPERAND_4_COMPONENT_MASK_W) 656#define VGPU10_OPERAND_4_COMPONENT_MASK_XYZW (VGPU10_OPERAND_4_COMPONENT_MASK_XYZ | VGPU10_OPERAND_4_COMPONENT_MASK_W) 657#define VGPU10_OPERAND_4_COMPONENT_MASK_ALL VGPU10_OPERAND_4_COMPONENT_MASK_XYZW 658 659#define VGPU10_REGISTER_INDEX_FROM_SEMANTIC 0xffffffff 660 661typedef enum { 662 VGPU10_COMPONENT_X = 0, 663 VGPU10_COMPONENT_Y = 1, 664 VGPU10_COMPONENT_Z = 2, 665 VGPU10_COMPONENT_W = 3 666} VGPU10_COMPONENT_NAME; 667 668typedef enum { 669 VGPU10_OPERAND_TYPE_TEMP = 0, 670 VGPU10_OPERAND_TYPE_INPUT = 1, 671 VGPU10_OPERAND_TYPE_OUTPUT = 2, 672 VGPU10_OPERAND_TYPE_INDEXABLE_TEMP = 3, 673 VGPU10_OPERAND_TYPE_IMMEDIATE32 = 4, 674 VGPU10_OPERAND_TYPE_IMMEDIATE64 = 5, 675 VGPU10_OPERAND_TYPE_SAMPLER = 6, 676 VGPU10_OPERAND_TYPE_RESOURCE = 7, 677 VGPU10_OPERAND_TYPE_CONSTANT_BUFFER = 8, 678 VGPU10_OPERAND_TYPE_IMMEDIATE_CONSTANT_BUFFER = 9, 679 VGPU10_OPERAND_TYPE_LABEL = 10, 680 VGPU10_OPERAND_TYPE_INPUT_PRIMITIVEID = 11, 681 VGPU10_OPERAND_TYPE_OUTPUT_DEPTH = 12, 682 VGPU10_OPERAND_TYPE_NULL = 13, 683 VGPU10_OPERAND_TYPE_SM40_MAX = 13, 684 685 686 VGPU10_OPERAND_TYPE_RASTERIZER = 14, 687 VGPU10_OPERAND_TYPE_OUTPUT_COVERAGE_MASK = 15, 688 VGPU10_OPERAND_TYPE_SM41_MAX = 15, 689 690 691 VGPU10_OPERAND_TYPE_STREAM = 16, 692 VGPU10_OPERAND_TYPE_FUNCTION_BODY = 17, 693 VGPU10_OPERAND_TYPE_FUNCTION_TABLE = 18, 694 VGPU10_OPERAND_TYPE_INTERFACE = 19, 695 VGPU10_OPERAND_TYPE_FUNCTION_INPUT = 20, 696 VGPU10_OPERAND_TYPE_FUNCTION_OUTPUT = 21, 697 VGPU10_OPERAND_TYPE_OUTPUT_CONTROL_POINT_ID = 22, 698 VGPU10_OPERAND_TYPE_INPUT_FORK_INSTANCE_ID = 23, 699 VGPU10_OPERAND_TYPE_INPUT_JOIN_INSTANCE_ID = 24, 700 VGPU10_OPERAND_TYPE_INPUT_CONTROL_POINT = 25, 701 VGPU10_OPERAND_TYPE_OUTPUT_CONTROL_POINT = 26, 702 VGPU10_OPERAND_TYPE_INPUT_PATCH_CONSTANT = 27, 703 VGPU10_OPERAND_TYPE_INPUT_DOMAIN_POINT = 28, 704 VGPU10_OPERAND_TYPE_THIS_POINTER = 29, 705 VGPU10_OPERAND_TYPE_UAV = 30, 706 VGPU10_OPERAND_TYPE_THREAD_GROUP_SHARED_MEMORY = 31, 707 VGPU10_OPERAND_TYPE_INPUT_THREAD_ID = 32, 708 VGPU10_OPERAND_TYPE_INPUT_THREAD_GROUP_ID = 33, 709 VGPU10_OPERAND_TYPE_INPUT_THREAD_ID_IN_GROUP = 34, 710 VGPU10_OPERAND_TYPE_INPUT_COVERAGE_MASK = 35, 711 VGPU10_OPERAND_TYPE_INPUT_THREAD_ID_IN_GROUP_FLATTENED = 36, 712 VGPU10_OPERAND_TYPE_INPUT_GS_INSTANCE_ID = 37, 713 VGPU10_OPERAND_TYPE_OUTPUT_DEPTH_GREATER_EQUAL = 38, 714 VGPU10_OPERAND_TYPE_OUTPUT_DEPTH_LESS_EQUAL = 39, 715 VGPU10_OPERAND_TYPE_CYCLE_COUNTER = 40, 716 VGPU10_OPERAND_TYPE_SM50_MAX = 40, 717 718 VGPU10_NUM_OPERANDS 719} VGPU10_OPERAND_TYPE; 720 721typedef enum { 722 VGPU10_OPERAND_INDEX_0D = 0, 723 VGPU10_OPERAND_INDEX_1D = 1, 724 VGPU10_OPERAND_INDEX_2D = 2, 725 VGPU10_OPERAND_INDEX_3D = 3 726} VGPU10_OPERAND_INDEX_DIMENSION; 727 728typedef enum { 729 VGPU10_OPERAND_INDEX_IMMEDIATE32 = 0, 730 VGPU10_OPERAND_INDEX_IMMEDIATE64 = 1, 731 VGPU10_OPERAND_INDEX_RELATIVE = 2, 732 VGPU10_OPERAND_INDEX_IMMEDIATE32_PLUS_RELATIVE = 3, 733 VGPU10_OPERAND_INDEX_IMMEDIATE64_PLUS_RELATIVE = 4 734} VGPU10_OPERAND_INDEX_REPRESENTATION; 735 736typedef union { 737 struct { 738 unsigned int numComponents : 2; 739 unsigned int selectionMode : 2; 740 unsigned int mask : 4; 741 unsigned int : 4; 742 unsigned int operandType : 8; 743 unsigned int indexDimension : 2; 744 unsigned int index0Representation : 3; 745 unsigned int index1Representation : 3; 746 unsigned int : 3; 747 unsigned int extended : 1; 748 }; 749 struct { 750 unsigned int : 4; 751 unsigned int swizzleX : 2; 752 unsigned int swizzleY : 2; 753 unsigned int swizzleZ : 2; 754 unsigned int swizzleW : 2; 755 }; 756 struct { 757 unsigned int : 4; 758 unsigned int selectMask : 2; 759 }; 760 uint32 value; 761} VGPU10OperandToken0; 762 763 764typedef enum { 765 VGPU10_EXTENDED_OPERAND_EMPTY = 0, 766 VGPU10_EXTENDED_OPERAND_MODIFIER = 1 767} VGPU10_EXTENDED_OPERAND_TYPE; 768 769typedef enum { 770 VGPU10_OPERAND_MODIFIER_NONE = 0, 771 VGPU10_OPERAND_MODIFIER_NEG = 1, 772 VGPU10_OPERAND_MODIFIER_ABS = 2, 773 VGPU10_OPERAND_MODIFIER_ABSNEG = 3 774} VGPU10_OPERAND_MODIFIER; 775 776typedef union { 777 struct { 778 unsigned int extendedOperandType : 6; 779 unsigned int operandModifier : 8; 780 unsigned int : 17; 781 unsigned int extended : 1; 782 }; 783 uint32 value; 784} VGPU10OperandToken1; 785 786 787typedef enum { 788 VGPU10_RETURN_TYPE_MIN = 1, 789 790 VGPU10_RETURN_TYPE_UNORM = 1, 791 VGPU10_RETURN_TYPE_SNORM = 2, 792 VGPU10_RETURN_TYPE_SINT = 3, 793 VGPU10_RETURN_TYPE_UINT = 4, 794 VGPU10_RETURN_TYPE_FLOAT = 5, 795 VGPU10_RETURN_TYPE_MIXED = 6, 796 VGPU10_RETURN_TYPE_SM40_MAX = 6, 797 798 799 VGPU10_RETURN_TYPE_DOUBLE = 7, 800 VGPU10_RETURN_TYPE_CONTINUED = 8, 801 VGPU10_RETURN_TYPE_UNUSED = 9, 802 803 VGPU10_RETURN_TYPE_MAX = 9 804} VGPU10_RESOURCE_RETURN_TYPE; 805 806typedef union { 807 struct { 808 unsigned int component0 : 4; 809 unsigned int component1 : 4; 810 unsigned int component2 : 4; 811 unsigned int component3 : 4; 812 }; 813 uint32 value; 814} VGPU10ResourceReturnTypeToken; 815 816 817typedef enum { 818 VGPU10_NAME_MIN = 0, 819 820 VGPU10_NAME_UNDEFINED = 0, 821 VGPU10_NAME_POSITION = 1, 822 VGPU10_NAME_CLIP_DISTANCE = 2, 823 VGPU10_NAME_CULL_DISTANCE = 3, 824 VGPU10_NAME_RENDER_TARGET_ARRAY_INDEX = 4, 825 VGPU10_NAME_VIEWPORT_ARRAY_INDEX = 5, 826 VGPU10_NAME_VERTEX_ID = 6, 827 VGPU10_NAME_PRIMITIVE_ID = 7, 828 VGPU10_NAME_INSTANCE_ID = 8, 829 VGPU10_NAME_IS_FRONT_FACE = 9, 830 VGPU10_NAME_SAMPLE_INDEX = 10, 831 VGPU10_NAME_SM40_MAX = 10, 832 833 834 VGPU10_NAME_FINAL_QUAD_U_EQ_0_EDGE_TESSFACTOR = 11, 835 VGPU10_NAME_FINAL_QUAD_V_EQ_0_EDGE_TESSFACTOR = 12, 836 VGPU10_NAME_FINAL_QUAD_U_EQ_1_EDGE_TESSFACTOR = 13, 837 VGPU10_NAME_FINAL_QUAD_V_EQ_1_EDGE_TESSFACTOR = 14, 838 VGPU10_NAME_FINAL_QUAD_U_INSIDE_TESSFACTOR = 15, 839 VGPU10_NAME_FINAL_QUAD_V_INSIDE_TESSFACTOR = 16, 840 VGPU10_NAME_FINAL_TRI_U_EQ_0_EDGE_TESSFACTOR = 17, 841 VGPU10_NAME_FINAL_TRI_V_EQ_0_EDGE_TESSFACTOR = 18, 842 VGPU10_NAME_FINAL_TRI_W_EQ_0_EDGE_TESSFACTOR = 19, 843 VGPU10_NAME_FINAL_TRI_INSIDE_TESSFACTOR = 20, 844 VGPU10_NAME_FINAL_LINE_DETAIL_TESSFACTOR = 21, 845 VGPU10_NAME_FINAL_LINE_DENSITY_TESSFACTOR = 22, 846 847 VGPU10_NAME_MAX = 22 848} VGPU10_SYSTEM_NAME; 849 850typedef union { 851 struct { 852 unsigned int name : 16; 853 }; 854 uint32 value; 855} VGPU10NameToken; 856 857#endif 858