1/* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * on the rights to use, copy, modify, merge, publish, distribute, sub 9 * license, and/or sell copies of the Software, and to permit persons to whom 10 * the Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 22 * USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25/* This file handles register programming of primitive binning. */ 26 27#include "si_build_pm4.h" 28#include "sid.h" 29 30struct uvec2 { 31 unsigned x, y; 32}; 33 34struct si_bin_size_map { 35 unsigned start; 36 unsigned bin_size_x; 37 unsigned bin_size_y; 38}; 39 40typedef struct si_bin_size_map si_bin_size_subtable[3][10]; 41 42/* Find the bin size where sum is >= table[i].start and < table[i + 1].start. */ 43static struct uvec2 si_find_bin_size(struct si_screen *sscreen, const si_bin_size_subtable table[], 44 unsigned sum) 45{ 46 unsigned log_num_rb_per_se = 47 util_logbase2_ceil(sscreen->info.max_render_backends / sscreen->info.max_se); 48 unsigned log_num_se = util_logbase2_ceil(sscreen->info.max_se); 49 unsigned i; 50 51 /* Get the chip-specific subtable. */ 52 const struct si_bin_size_map *subtable = &table[log_num_rb_per_se][log_num_se][0]; 53 54 for (i = 0; subtable[i].bin_size_x != 0; i++) { 55 if (sum >= subtable[i].start && sum < subtable[i + 1].start) 56 break; 57 } 58 59 struct uvec2 size = {subtable[i].bin_size_x, subtable[i].bin_size_y}; 60 return size; 61} 62 63static struct uvec2 si_get_color_bin_size(struct si_context *sctx, unsigned cb_target_enabled_4bit) 64{ 65 unsigned num_fragments = sctx->framebuffer.nr_color_samples; 66 unsigned sum = 0; 67 68 /* Compute the sum of all Bpp. */ 69 for (unsigned i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) { 70 if (!(cb_target_enabled_4bit & (0xf << (i * 4)))) 71 continue; 72 73 struct si_texture *tex = (struct si_texture *)sctx->framebuffer.state.cbufs[i]->texture; 74 sum += tex->surface.bpe; 75 } 76 77 /* Multiply the sum by some function of the number of samples. */ 78 if (num_fragments >= 2) { 79 if (si_get_ps_iter_samples(sctx) >= 2) 80 sum *= num_fragments; 81 else 82 sum *= 2; 83 } 84 85 static const si_bin_size_subtable table[] = { 86 { 87 /* One RB / SE */ 88 { 89 /* One shader engine */ 90 {0, 128, 128}, 91 {1, 64, 128}, 92 {2, 32, 128}, 93 {3, 16, 128}, 94 {17, 0, 0}, 95 }, 96 { 97 /* Two shader engines */ 98 {0, 128, 128}, 99 {2, 64, 128}, 100 {3, 32, 128}, 101 {5, 16, 128}, 102 {17, 0, 0}, 103 }, 104 { 105 /* Four shader engines */ 106 {0, 128, 128}, 107 {3, 64, 128}, 108 {5, 16, 128}, 109 {17, 0, 0}, 110 }, 111 }, 112 { 113 /* Two RB / SE */ 114 { 115 /* One shader engine */ 116 {0, 128, 128}, 117 {2, 64, 128}, 118 {3, 32, 128}, 119 {9, 16, 128}, 120 {33, 0, 0}, 121 }, 122 { 123 /* Two shader engines */ 124 {0, 128, 128}, 125 {3, 64, 128}, 126 {5, 32, 128}, 127 {9, 16, 128}, 128 {33, 0, 0}, 129 }, 130 { 131 /* Four shader engines */ 132 {0, 256, 256}, 133 {2, 128, 256}, 134 {3, 128, 128}, 135 {5, 64, 128}, 136 {9, 16, 128}, 137 {33, 0, 0}, 138 }, 139 }, 140 { 141 /* Four RB / SE */ 142 { 143 /* One shader engine */ 144 {0, 128, 256}, 145 {2, 128, 128}, 146 {3, 64, 128}, 147 {5, 32, 128}, 148 {9, 16, 128}, 149 {17, 0, 0}, 150 }, 151 { 152 /* Two shader engines */ 153 {0, 256, 256}, 154 {2, 128, 256}, 155 {3, 128, 128}, 156 {5, 64, 128}, 157 {9, 32, 128}, 158 {17, 16, 128}, 159 {33, 0, 0}, 160 }, 161 { 162 /* Four shader engines */ 163 {0, 256, 512}, 164 {2, 128, 512}, 165 {3, 64, 512}, 166 {5, 32, 512}, 167 {9, 32, 256}, 168 {17, 32, 128}, 169 {33, 0, 0}, 170 }, 171 }, 172 }; 173 174 return si_find_bin_size(sctx->screen, table, sum); 175} 176 177static struct uvec2 si_get_depth_bin_size(struct si_context *sctx) 178{ 179 struct si_state_dsa *dsa = sctx->queued.named.dsa; 180 181 if (!sctx->framebuffer.state.zsbuf || (!dsa->depth_enabled && !dsa->stencil_enabled)) { 182 /* Return the max size. */ 183 struct uvec2 size = {512, 512}; 184 return size; 185 } 186 187 struct si_texture *tex = (struct si_texture *)sctx->framebuffer.state.zsbuf->texture; 188 unsigned depth_coeff = dsa->depth_enabled ? 5 : 0; 189 unsigned stencil_coeff = tex->surface.has_stencil && dsa->stencil_enabled ? 1 : 0; 190 unsigned sum = 4 * (depth_coeff + stencil_coeff) * MAX2(tex->buffer.b.b.nr_samples, 1); 191 192 static const si_bin_size_subtable table[] = { 193 { 194 // One RB / SE 195 { 196 // One shader engine 197 {0, 64, 512}, 198 {2, 64, 256}, 199 {4, 64, 128}, 200 {7, 32, 128}, 201 {13, 16, 128}, 202 {49, 0, 0}, 203 }, 204 { 205 // Two shader engines 206 {0, 128, 512}, 207 {2, 64, 512}, 208 {4, 64, 256}, 209 {7, 64, 128}, 210 {13, 32, 128}, 211 {25, 16, 128}, 212 {49, 0, 0}, 213 }, 214 { 215 // Four shader engines 216 {0, 256, 512}, 217 {2, 128, 512}, 218 {4, 64, 512}, 219 {7, 64, 256}, 220 {13, 64, 128}, 221 {25, 16, 128}, 222 {49, 0, 0}, 223 }, 224 }, 225 { 226 // Two RB / SE 227 { 228 // One shader engine 229 {0, 128, 512}, 230 {2, 64, 512}, 231 {4, 64, 256}, 232 {7, 64, 128}, 233 {13, 32, 128}, 234 {25, 16, 128}, 235 {97, 0, 0}, 236 }, 237 { 238 // Two shader engines 239 {0, 256, 512}, 240 {2, 128, 512}, 241 {4, 64, 512}, 242 {7, 64, 256}, 243 {13, 64, 128}, 244 {25, 32, 128}, 245 {49, 16, 128}, 246 {97, 0, 0}, 247 }, 248 { 249 // Four shader engines 250 {0, 512, 512}, 251 {2, 256, 512}, 252 {4, 128, 512}, 253 {7, 64, 512}, 254 {13, 64, 256}, 255 {25, 64, 128}, 256 {49, 16, 128}, 257 {97, 0, 0}, 258 }, 259 }, 260 { 261 // Four RB / SE 262 { 263 // One shader engine 264 {0, 256, 512}, 265 {2, 128, 512}, 266 {4, 64, 512}, 267 {7, 64, 256}, 268 {13, 64, 128}, 269 {25, 32, 128}, 270 {49, 16, 128}, 271 {193, 0, 0}, 272 }, 273 { 274 // Two shader engines 275 {0, 512, 512}, 276 {2, 256, 512}, 277 {4, 128, 512}, 278 {7, 64, 512}, 279 {13, 64, 256}, 280 {25, 64, 128}, 281 {49, 32, 128}, 282 {97, 16, 128}, 283 {193, 0, 0}, 284 }, 285 { 286 // Four shader engines 287 {0, 512, 512}, 288 {4, 256, 512}, 289 {7, 128, 512}, 290 {13, 64, 512}, 291 {25, 32, 512}, 292 {49, 32, 256}, 293 {97, 16, 128}, 294 {193, 0, 0}, 295 }, 296 }, 297 }; 298 299 return si_find_bin_size(sctx->screen, table, sum); 300} 301 302static void gfx10_get_bin_sizes(struct si_context *sctx, unsigned cb_target_enabled_4bit, 303 struct uvec2 *color_bin_size, struct uvec2 *depth_bin_size) 304{ 305 const unsigned ZsTagSize = 64; 306 const unsigned ZsNumTags = 312; 307 const unsigned CcTagSize = 1024; 308 const unsigned CcReadTags = 31; 309 const unsigned FcTagSize = 256; 310 const unsigned FcReadTags = 44; 311 312 const unsigned num_rbs = sctx->screen->info.max_render_backends; 313 const unsigned num_pipes = MAX2(num_rbs, sctx->screen->info.num_tcc_blocks); 314 315 const unsigned depthBinSizeTagPart = 316 ((ZsNumTags * num_rbs / num_pipes) * (ZsTagSize * num_pipes)); 317 const unsigned colorBinSizeTagPart = 318 ((CcReadTags * num_rbs / num_pipes) * (CcTagSize * num_pipes)); 319 const unsigned fmaskBinSizeTagPart = 320 ((FcReadTags * num_rbs / num_pipes) * (FcTagSize * num_pipes)); 321 322 const unsigned minBinSizeX = 128; 323 const unsigned minBinSizeY = 64; 324 325 const unsigned num_fragments = sctx->framebuffer.nr_color_samples; 326 const unsigned num_samples = sctx->framebuffer.nr_samples; 327 const bool ps_iter_sample = si_get_ps_iter_samples(sctx) >= 2; 328 329 /* Calculate cColor and cFmask(if applicable) */ 330 unsigned cColor = 0; 331 unsigned cFmask = 0; 332 bool has_fmask = false; 333 334 for (unsigned i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) { 335 if (!sctx->framebuffer.state.cbufs[i]) 336 continue; 337 338 struct si_texture *tex = (struct si_texture *)sctx->framebuffer.state.cbufs[i]->texture; 339 const unsigned mmrt = num_fragments == 1 ? 1 : (ps_iter_sample ? num_fragments : 2); 340 341 cColor += tex->surface.bpe * mmrt; 342 if (num_samples >= 2 /* if FMASK is bound */) { 343 const unsigned fragmentsLog2 = util_logbase2(num_fragments); 344 const unsigned samplesLog2 = util_logbase2(num_samples); 345 346 static const unsigned cFmaskMrt[4 /* fragments */][5 /* samples */] = { 347 {0, 1, 1, 1, 2}, /* fragments = 1 */ 348 {0, 1, 1, 2, 4}, /* fragments = 2 */ 349 {0, 1, 1, 4, 8}, /* fragments = 4 */ 350 {0, 1, 2, 4, 8} /* fragments = 8 */ 351 }; 352 cFmask += cFmaskMrt[fragmentsLog2][samplesLog2]; 353 has_fmask = true; 354 } 355 } 356 cColor = MAX2(cColor, 1u); 357 358 const unsigned colorLog2Pixels = util_logbase2(colorBinSizeTagPart / cColor); 359 const unsigned colorBinSizeX = 1 << ((colorLog2Pixels + 1) / 2); /* round up width */ 360 const unsigned colorBinSizeY = 1 << (colorLog2Pixels / 2); /* round down height */ 361 362 unsigned binSizeX = colorBinSizeX; 363 unsigned binSizeY = colorBinSizeY; 364 365 if (has_fmask) { 366 cFmask = MAX2(cFmask, 1u); 367 368 const unsigned fmaskLog2Pixels = util_logbase2(fmaskBinSizeTagPart / cFmask); 369 const unsigned fmaskBinSizeX = 1 << ((fmaskLog2Pixels + 1) / 2); /* round up width */ 370 const unsigned fmaskBinSizeY = 1 << (fmaskLog2Pixels / 2); /* round down height */ 371 372 /* use the smaller of the Color vs. Fmask bin sizes */ 373 if (fmaskLog2Pixels < colorLog2Pixels) { 374 binSizeX = fmaskBinSizeX; 375 binSizeY = fmaskBinSizeY; 376 } 377 } 378 379 /* Return size adjusted for minimum bin size */ 380 color_bin_size->x = MAX2(binSizeX, minBinSizeX); 381 color_bin_size->y = MAX2(binSizeY, minBinSizeY); 382 383 if (!sctx->framebuffer.state.zsbuf) { 384 /* Set to max sizes when no depth buffer is bound. */ 385 depth_bin_size->x = 512; 386 depth_bin_size->y = 512; 387 } else { 388 struct si_texture *zstex = (struct si_texture *)sctx->framebuffer.state.zsbuf->texture; 389 struct si_state_dsa *dsa = sctx->queued.named.dsa; 390 391 const unsigned cPerDepthSample = dsa->depth_enabled ? 5 : 0; 392 const unsigned cPerStencilSample = dsa->stencil_enabled ? 1 : 0; 393 const unsigned cDepth = 394 (cPerDepthSample + cPerStencilSample) * MAX2(zstex->buffer.b.b.nr_samples, 1); 395 396 const unsigned depthLog2Pixels = util_logbase2(depthBinSizeTagPart / MAX2(cDepth, 1u)); 397 unsigned depthBinSizeX = 1 << ((depthLog2Pixels + 1) / 2); 398 unsigned depthBinSizeY = 1 << (depthLog2Pixels / 2); 399 400 depth_bin_size->x = MAX2(depthBinSizeX, minBinSizeX); 401 depth_bin_size->y = MAX2(depthBinSizeY, minBinSizeY); 402 } 403} 404 405static void si_emit_dpbb_disable(struct si_context *sctx) 406{ 407 radeon_begin(&sctx->gfx_cs); 408 409 if (sctx->gfx_level >= GFX10) { 410 struct uvec2 bin_size = {}; 411 struct uvec2 bin_size_extend = {}; 412 413 bin_size.x = 128; 414 bin_size.y = sctx->framebuffer.min_bytes_per_pixel <= 4 ? 128 : 64; 415 416 if (bin_size.x >= 32) 417 bin_size_extend.x = util_logbase2(bin_size.x) - 5; 418 if (bin_size.y >= 32) 419 bin_size_extend.y = util_logbase2(bin_size.y) - 5; 420 421 radeon_opt_set_context_reg( 422 sctx, R_028C44_PA_SC_BINNER_CNTL_0, SI_TRACKED_PA_SC_BINNER_CNTL_0, 423 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) | 424 S_028C44_BIN_SIZE_X(bin_size.x == 16) | S_028C44_BIN_SIZE_Y(bin_size.y == 16) | 425 S_028C44_BIN_SIZE_X_EXTEND(bin_size_extend.x) | 426 S_028C44_BIN_SIZE_Y_EXTEND(bin_size_extend.y) | S_028C44_DISABLE_START_OF_PRIM(1) | 427 S_028C44_FPOVS_PER_BATCH(63) | 428 S_028C44_OPTIMAL_BIN_SELECTION(1) | 429 S_028C44_FLUSH_ON_BINNING_TRANSITION(1)); 430 } else { 431 radeon_opt_set_context_reg( 432 sctx, R_028C44_PA_SC_BINNER_CNTL_0, SI_TRACKED_PA_SC_BINNER_CNTL_0, 433 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) | 434 S_028C44_DISABLE_START_OF_PRIM(1) | 435 S_028C44_FLUSH_ON_BINNING_TRANSITION(sctx->family == CHIP_VEGA12 || 436 sctx->family == CHIP_VEGA20 || 437 sctx->family >= CHIP_RAVEN2)); 438 } 439 radeon_end_update_context_roll(sctx); 440} 441 442void si_emit_dpbb_state(struct si_context *sctx) 443{ 444 struct si_screen *sscreen = sctx->screen; 445 struct si_state_blend *blend = sctx->queued.named.blend; 446 struct si_state_dsa *dsa = sctx->queued.named.dsa; 447 unsigned db_shader_control = sctx->ps_db_shader_control; 448 449 assert(sctx->gfx_level >= GFX9); 450 451 if (!sscreen->dpbb_allowed || sctx->dpbb_force_off || 452 sctx->dpbb_force_off_profile_vs || sctx->dpbb_force_off_profile_ps) { 453 si_emit_dpbb_disable(sctx); 454 return; 455 } 456 457 bool ps_can_kill = 458 G_02880C_KILL_ENABLE(db_shader_control) || G_02880C_MASK_EXPORT_ENABLE(db_shader_control) || 459 G_02880C_COVERAGE_TO_MASK_ENABLE(db_shader_control) || blend->alpha_to_coverage; 460 461 bool db_can_reject_z_trivially = !G_02880C_Z_EXPORT_ENABLE(db_shader_control) || 462 G_02880C_CONSERVATIVE_Z_EXPORT(db_shader_control) || 463 G_02880C_DEPTH_BEFORE_SHADER(db_shader_control); 464 465 /* Disable DPBB when it's believed to be inefficient. */ 466 if (sscreen->info.max_render_backends > 4 && ps_can_kill && db_can_reject_z_trivially && 467 sctx->framebuffer.state.zsbuf && dsa->db_can_write) { 468 si_emit_dpbb_disable(sctx); 469 return; 470 } 471 472 /* Compute the bin size. */ 473 /* TODO: We could also look at enabled pixel shader outputs. */ 474 unsigned cb_target_enabled_4bit = 475 sctx->framebuffer.colorbuf_enabled_4bit & blend->cb_target_enabled_4bit; 476 struct uvec2 color_bin_size, depth_bin_size; 477 478 if (sctx->gfx_level >= GFX10) { 479 gfx10_get_bin_sizes(sctx, cb_target_enabled_4bit, &color_bin_size, &depth_bin_size); 480 } else { 481 color_bin_size = si_get_color_bin_size(sctx, cb_target_enabled_4bit); 482 depth_bin_size = si_get_depth_bin_size(sctx); 483 } 484 485 unsigned color_area = color_bin_size.x * color_bin_size.y; 486 unsigned depth_area = depth_bin_size.x * depth_bin_size.y; 487 488 struct uvec2 bin_size = color_area < depth_area ? color_bin_size : depth_bin_size; 489 490 if (!bin_size.x || !bin_size.y) { 491 si_emit_dpbb_disable(sctx); 492 return; 493 } 494 495 /* Tunable parameters. */ 496 /* Allowed range: 497 * gfx9-10: [0, 255] (0 = unlimited) 498 * gfx11: [1, 255] (255 = unlimited) 499 */ 500 unsigned fpovs_per_batch = 63; 501 502 /* Emit registers. */ 503 struct uvec2 bin_size_extend = {}; 504 if (bin_size.x >= 32) 505 bin_size_extend.x = util_logbase2(bin_size.x) - 5; 506 if (bin_size.y >= 32) 507 bin_size_extend.y = util_logbase2(bin_size.y) - 5; 508 509 radeon_begin(&sctx->gfx_cs); 510 radeon_opt_set_context_reg( 511 sctx, R_028C44_PA_SC_BINNER_CNTL_0, SI_TRACKED_PA_SC_BINNER_CNTL_0, 512 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) | S_028C44_BIN_SIZE_X(bin_size.x == 16) | 513 S_028C44_BIN_SIZE_Y(bin_size.y == 16) | S_028C44_BIN_SIZE_X_EXTEND(bin_size_extend.x) | 514 S_028C44_BIN_SIZE_Y_EXTEND(bin_size_extend.y) | 515 S_028C44_CONTEXT_STATES_PER_BIN(sscreen->pbb_context_states_per_bin - 1) | 516 S_028C44_PERSISTENT_STATES_PER_BIN(sscreen->pbb_persistent_states_per_bin - 1) | 517 S_028C44_DISABLE_START_OF_PRIM(1) | 518 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) | S_028C44_OPTIMAL_BIN_SELECTION(1) | 519 S_028C44_FLUSH_ON_BINNING_TRANSITION(sctx->family == CHIP_VEGA12 || 520 sctx->family == CHIP_VEGA20 || 521 sctx->family >= CHIP_RAVEN2)); 522 radeon_end_update_context_roll(sctx); 523} 524