1/*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef SI_STATE_H
26#define SI_STATE_H
27
28#include "pipebuffer/pb_slab.h"
29#include "si_pm4.h"
30#include "util/u_blitter.h"
31
32#ifdef __cplusplus
33extern "C" {
34#endif
35
36#define SI_NUM_GRAPHICS_SHADERS (PIPE_SHADER_TESS_EVAL + 1)
37#define SI_NUM_SHADERS          (PIPE_SHADER_COMPUTE + 1)
38
39#define SI_NUM_VERTEX_BUFFERS SI_MAX_ATTRIBS
40#define SI_NUM_SAMPLERS       32 /* OpenGL textures units per shader */
41#define SI_NUM_CONST_BUFFERS  16
42#define SI_NUM_IMAGES         16
43#define SI_NUM_IMAGE_SLOTS    (SI_NUM_IMAGES * 2) /* the second half are FMASK slots */
44#define SI_NUM_SHADER_BUFFERS 32
45
46struct si_screen;
47struct si_shader;
48struct si_shader_ctx_state;
49struct si_shader_selector;
50struct si_texture;
51struct si_qbo_state;
52
53struct si_state_blend {
54   struct si_pm4_state pm4;
55   uint32_t cb_target_mask;
56   /* Set 0xf or 0x0 (4 bits) per render target if the following is
57    * true. ANDed with spi_shader_col_format.
58    */
59   unsigned cb_target_enabled_4bit;
60   unsigned blend_enable_4bit;
61   unsigned need_src_alpha_4bit;
62   unsigned commutative_4bit;
63   unsigned dcc_msaa_corruption_4bit;
64   bool alpha_to_coverage : 1;
65   bool alpha_to_one : 1;
66   bool dual_src_blend : 1;
67   bool logicop_enable : 1;
68   bool allows_noop_optimization : 1;
69};
70
71struct si_state_rasterizer {
72   struct si_pm4_state pm4;
73   /* poly offset states for 16-bit, 24-bit, and 32-bit zbuffers */
74   struct si_pm4_state *pm4_poly_offset;
75   unsigned pa_sc_line_stipple;
76   unsigned pa_cl_clip_cntl;
77   float line_width;
78   float max_point_size;
79   unsigned ngg_cull_flags_tris : 16;
80   unsigned ngg_cull_flags_tris_y_inverted : 16;
81   unsigned ngg_cull_flags_lines : 16;
82   unsigned sprite_coord_enable : 8;
83   unsigned clip_plane_enable : 8;
84   unsigned half_pixel_center : 1;
85   unsigned flatshade : 1;
86   unsigned flatshade_first : 1;
87   unsigned two_side : 1;
88   unsigned multisample_enable : 1;
89   unsigned force_persample_interp : 1;
90   unsigned line_stipple_enable : 1;
91   unsigned poly_stipple_enable : 1;
92   unsigned line_smooth : 1;
93   unsigned poly_smooth : 1;
94   unsigned point_smooth : 1;
95   unsigned uses_poly_offset : 1;
96   unsigned clamp_fragment_color : 1;
97   unsigned clamp_vertex_color : 1;
98   unsigned rasterizer_discard : 1;
99   unsigned scissor_enable : 1;
100   unsigned clip_halfz : 1;
101   unsigned polygon_mode_is_lines : 1;
102   unsigned polygon_mode_is_points : 1;
103   unsigned perpendicular_end_caps : 1;
104};
105
106struct si_dsa_stencil_ref_part {
107   uint8_t valuemask[2];
108   uint8_t writemask[2];
109};
110
111struct si_dsa_order_invariance {
112   /** Whether the final result in Z/S buffers is guaranteed to be
113    * invariant under changes to the order in which fragments arrive. */
114   bool zs : 1;
115
116   /** Whether the set of fragments that pass the combined Z/S test is
117    * guaranteed to be invariant under changes to the order in which
118    * fragments arrive. */
119   bool pass_set : 1;
120};
121
122struct si_state_dsa {
123   struct si_pm4_state pm4;
124   struct si_dsa_stencil_ref_part stencil_ref;
125
126   /* 0 = without stencil buffer, 1 = when both Z and S buffers are present */
127   struct si_dsa_order_invariance order_invariance[2];
128
129   ubyte alpha_func : 3;
130   bool depth_enabled : 1;
131   bool depth_write_enabled : 1;
132   bool stencil_enabled : 1;
133   bool stencil_write_enabled : 1;
134   bool db_can_write : 1;
135};
136
137struct si_stencil_ref {
138   struct pipe_stencil_ref state;
139   struct si_dsa_stencil_ref_part dsa_part;
140};
141
142struct si_vertex_elements {
143   struct si_resource *instance_divisor_factor_buffer;
144   uint32_t rsrc_word3[SI_MAX_ATTRIBS];
145   uint16_t src_offset[SI_MAX_ATTRIBS];
146   uint8_t fix_fetch[SI_MAX_ATTRIBS];
147   uint8_t format_size[SI_MAX_ATTRIBS];
148   uint8_t vertex_buffer_index[SI_MAX_ATTRIBS];
149
150   /* Bitmask of elements that always need a fixup to be applied. */
151   uint16_t fix_fetch_always;
152
153   /* Bitmask of elements whose fetch should always be opencoded. */
154   uint16_t fix_fetch_opencode;
155
156   /* Bitmask of elements which need to be opencoded if the vertex buffer
157    * is unaligned. */
158   uint16_t fix_fetch_unaligned;
159
160   /* For elements in fix_fetch_unaligned: whether the effective
161    * element load size as seen by the hardware is a dword (as opposed
162    * to a short).
163    */
164   uint16_t hw_load_is_dword;
165
166   /* Bitmask of vertex buffers requiring alignment check */
167   uint16_t vb_alignment_check_mask;
168
169   uint8_t count;
170
171   uint16_t first_vb_use_mask;
172   /* Vertex buffer descriptor list size aligned for optimal prefetch. */
173   uint16_t vb_desc_list_alloc_size;
174   uint16_t instance_divisor_is_one;     /* bitmask of inputs */
175   uint16_t instance_divisor_is_fetched; /* bitmask of inputs */
176};
177
178union si_state {
179   struct si_state_named {
180      struct si_state_blend *blend;
181      struct si_state_rasterizer *rasterizer;
182      struct si_state_dsa *dsa;
183      struct si_pm4_state *poly_offset;
184      struct si_shader *ls;
185      struct si_shader *hs;
186      struct si_shader *es;
187      struct si_shader *gs;
188      struct si_pm4_state *vgt_shader_config;
189      struct si_shader *vs;
190      struct si_shader *ps;
191   } named;
192   struct si_pm4_state *array[sizeof(struct si_state_named) / sizeof(struct si_pm4_state *)];
193};
194
195#define SI_STATE_IDX(name) (offsetof(union si_state, named.name) / sizeof(struct si_pm4_state *))
196#define SI_STATE_BIT(name) (1 << SI_STATE_IDX(name))
197#define SI_NUM_STATES      (sizeof(union si_state) / sizeof(struct si_pm4_state *))
198
199static inline unsigned si_states_that_always_roll_context(void)
200{
201   return (SI_STATE_BIT(blend) | SI_STATE_BIT(rasterizer) | SI_STATE_BIT(dsa) |
202           SI_STATE_BIT(poly_offset) | SI_STATE_BIT(vgt_shader_config));
203}
204
205union si_state_atoms {
206   struct si_atoms_s {
207      /* The order matters. */
208      struct si_atom render_cond;
209      struct si_atom streamout_begin;
210      struct si_atom streamout_enable; /* must be after streamout_begin */
211      struct si_atom framebuffer;
212      struct si_atom msaa_sample_locs;
213      struct si_atom db_render_state;
214      struct si_atom dpbb_state;
215      struct si_atom msaa_config;
216      struct si_atom sample_mask;
217      struct si_atom cb_render_state;
218      struct si_atom blend_color;
219      struct si_atom clip_regs;
220      struct si_atom clip_state;
221      struct si_atom shader_pointers;
222      struct si_atom guardband;
223      struct si_atom scissors;
224      struct si_atom viewports;
225      struct si_atom stencil_ref;
226      struct si_atom spi_map;
227      struct si_atom scratch_state;
228      struct si_atom window_rectangles;
229      struct si_atom shader_query;
230      struct si_atom ngg_cull_state;
231   } s;
232   struct si_atom array[sizeof(struct si_atoms_s) / sizeof(struct si_atom)];
233};
234
235#define SI_ATOM_BIT(name) (1 << (offsetof(union si_state_atoms, s.name) / sizeof(struct si_atom)))
236#define SI_NUM_ATOMS      (sizeof(union si_state_atoms) / sizeof(struct si_atom))
237
238static inline unsigned si_atoms_that_always_roll_context(void)
239{
240   return (SI_ATOM_BIT(streamout_begin) | SI_ATOM_BIT(streamout_enable) | SI_ATOM_BIT(framebuffer) |
241           SI_ATOM_BIT(msaa_sample_locs) | SI_ATOM_BIT(sample_mask) | SI_ATOM_BIT(blend_color) |
242           SI_ATOM_BIT(clip_state) | SI_ATOM_BIT(scissors) | SI_ATOM_BIT(viewports) |
243           SI_ATOM_BIT(stencil_ref) | SI_ATOM_BIT(scratch_state) | SI_ATOM_BIT(window_rectangles));
244}
245
246struct si_shader_data {
247   uint32_t sh_base[SI_NUM_SHADERS];
248};
249
250/* The list of registers whose emitted values are remembered by si_context. */
251enum si_tracked_reg
252{
253   SI_TRACKED_DB_RENDER_CONTROL, /* 2 consecutive registers */
254   SI_TRACKED_DB_COUNT_CONTROL,
255
256   SI_TRACKED_DB_RENDER_OVERRIDE2,
257   SI_TRACKED_DB_SHADER_CONTROL,
258
259   SI_TRACKED_CB_TARGET_MASK,
260   SI_TRACKED_CB_DCC_CONTROL,
261
262   SI_TRACKED_SX_PS_DOWNCONVERT, /* 3 consecutive registers */
263   SI_TRACKED_SX_BLEND_OPT_EPSILON,
264   SI_TRACKED_SX_BLEND_OPT_CONTROL,
265
266   SI_TRACKED_PA_SC_LINE_CNTL, /* 2 consecutive registers */
267   SI_TRACKED_PA_SC_AA_CONFIG,
268
269   SI_TRACKED_DB_EQAA,
270   SI_TRACKED_PA_SC_MODE_CNTL_1,
271
272   SI_TRACKED_PA_SU_PRIM_FILTER_CNTL,
273   SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL,
274
275   SI_TRACKED_PA_CL_VS_OUT_CNTL,
276   SI_TRACKED_PA_CL_CLIP_CNTL,
277
278   SI_TRACKED_PA_SC_BINNER_CNTL_0,
279
280   SI_TRACKED_DB_PA_SC_VRS_OVERRIDE_CNTL,
281
282   SI_TRACKED_PA_CL_GB_VERT_CLIP_ADJ, /* 4 consecutive registers */
283   SI_TRACKED_PA_CL_GB_VERT_DISC_ADJ,
284   SI_TRACKED_PA_CL_GB_HORZ_CLIP_ADJ,
285   SI_TRACKED_PA_CL_GB_HORZ_DISC_ADJ,
286
287   SI_TRACKED_PA_SU_HARDWARE_SCREEN_OFFSET,
288   SI_TRACKED_PA_SU_VTX_CNTL,
289
290   SI_TRACKED_PA_SC_CLIPRECT_RULE,
291
292   SI_TRACKED_PA_SC_LINE_STIPPLE,
293
294   SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
295
296   SI_TRACKED_VGT_GSVS_RING_OFFSET_1, /* 3 consecutive registers */
297   SI_TRACKED_VGT_GSVS_RING_OFFSET_2,
298   SI_TRACKED_VGT_GSVS_RING_OFFSET_3,
299
300   SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
301   SI_TRACKED_VGT_GS_MAX_VERT_OUT,
302
303   SI_TRACKED_VGT_GS_VERT_ITEMSIZE, /* 4 consecutive registers */
304   SI_TRACKED_VGT_GS_VERT_ITEMSIZE_1,
305   SI_TRACKED_VGT_GS_VERT_ITEMSIZE_2,
306   SI_TRACKED_VGT_GS_VERT_ITEMSIZE_3,
307
308   SI_TRACKED_VGT_GS_INSTANCE_CNT,
309   SI_TRACKED_VGT_GS_ONCHIP_CNTL,
310   SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
311   SI_TRACKED_VGT_GS_MODE,
312   SI_TRACKED_VGT_PRIMITIVEID_EN,
313   SI_TRACKED_VGT_REUSE_OFF,
314   SI_TRACKED_SPI_VS_OUT_CONFIG,
315   SI_TRACKED_PA_CL_VTE_CNTL,
316   SI_TRACKED_PA_CL_NGG_CNTL,
317   SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
318   SI_TRACKED_GE_NGG_SUBGRP_CNTL,
319
320   SI_TRACKED_SPI_SHADER_IDX_FORMAT, /* 2 consecutive registers */
321   SI_TRACKED_SPI_SHADER_POS_FORMAT,
322
323   SI_TRACKED_SPI_PS_INPUT_ENA, /* 2 consecutive registers */
324   SI_TRACKED_SPI_PS_INPUT_ADDR,
325
326   SI_TRACKED_SPI_BARYC_CNTL,
327   SI_TRACKED_SPI_PS_IN_CONTROL,
328
329   SI_TRACKED_SPI_SHADER_Z_FORMAT, /* 2 consecutive registers */
330   SI_TRACKED_SPI_SHADER_COL_FORMAT,
331
332   SI_TRACKED_CB_SHADER_MASK,
333   SI_TRACKED_VGT_TF_PARAM,
334   SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
335
336   /* Non-context registers: */
337   SI_TRACKED_GE_PC_ALLOC,
338   SI_TRACKED_SPI_SHADER_PGM_RSRC3_GS,
339   SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS,
340
341   SI_NUM_TRACKED_REGS,
342};
343
344struct si_tracked_regs {
345   uint64_t reg_saved;
346   uint32_t reg_value[SI_NUM_TRACKED_REGS];
347   uint32_t spi_ps_input_cntl[32];
348};
349
350/* Private read-write buffer slots. */
351enum
352{
353   SI_VS_STREAMOUT_BUF0,
354   SI_VS_STREAMOUT_BUF1,
355   SI_VS_STREAMOUT_BUF2,
356   SI_VS_STREAMOUT_BUF3,
357
358   /* Image descriptor of color buffer 0 for KHR_blend_equation_advanced. */
359   SI_PS_IMAGE_COLORBUF0,
360   SI_PS_IMAGE_COLORBUF0_HI,
361   SI_PS_IMAGE_COLORBUF0_FMASK,        /* gfx6-10 */
362   SI_PS_IMAGE_COLORBUF0_FMASK_HI,     /* gfx6-10 */
363
364   /* Internal constant buffers. */
365   SI_HS_CONST_DEFAULT_TESS_LEVELS,
366   SI_VS_CONST_INSTANCE_DIVISORS,
367   SI_VS_CONST_CLIP_PLANES,
368   SI_PS_CONST_POLY_STIPPLE,
369   SI_PS_CONST_SAMPLE_POSITIONS,
370
371   SI_RING_ESGS,                       /* gfx6-8 */
372   SI_RING_GSVS,                       /* gfx6-10 */
373   SI_GS_QUERY_EMULATED_COUNTERS_BUF,  /* gfx10+ */
374
375   SI_NUM_INTERNAL_BINDINGS,
376
377   /* Aliases to reuse slots that are unused on other generations. */
378   SI_GS_QUERY_BUF = SI_RING_ESGS,     /* gfx10+ */
379
380   /* Only u_blitter uses this (and compute should be used in most cases, so this shouldn't
381    * be used much). Normal draws get the address from a user SGPR.
382    */
383   SI_GS_ATTRIBUTE_RING = SI_RING_GSVS, /* gfx11+ */
384};
385
386/* Indices into sctx->descriptors, laid out so that gfx and compute pipelines
387 * are contiguous:
388 *
389 *  0 - rw buffers
390 *  1 - vertex const and shader buffers
391 *  2 - vertex samplers and images
392 *  3 - fragment const and shader buffer
393 *   ...
394 *  11 - compute const and shader buffers
395 *  12 - compute samplers and images
396 */
397enum
398{
399   SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
400   SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
401   SI_NUM_SHADER_DESCS,
402};
403
404#define SI_DESCS_INTERNAL      0
405#define SI_DESCS_FIRST_SHADER  1
406#define SI_DESCS_FIRST_COMPUTE (SI_DESCS_FIRST_SHADER + PIPE_SHADER_COMPUTE * SI_NUM_SHADER_DESCS)
407#define SI_NUM_DESCS           (SI_DESCS_FIRST_SHADER + SI_NUM_SHADERS * SI_NUM_SHADER_DESCS)
408
409#define SI_DESCS_SHADER_MASK(name)                                                                 \
410   u_bit_consecutive(SI_DESCS_FIRST_SHADER + PIPE_SHADER_##name * SI_NUM_SHADER_DESCS,             \
411                     SI_NUM_SHADER_DESCS)
412
413static inline unsigned si_const_and_shader_buffer_descriptors_idx(unsigned shader)
414{
415   return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
416          SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS;
417}
418
419static inline unsigned si_sampler_and_image_descriptors_idx(unsigned shader)
420{
421   return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
422          SI_SHADER_DESCS_SAMPLERS_AND_IMAGES;
423}
424
425/* This represents descriptors in memory, such as buffer resources,
426 * image resources, and sampler states.
427 */
428struct si_descriptors {
429   /* The list of descriptors in malloc'd memory. */
430   uint32_t *list;
431   /* The list in mapped GPU memory. */
432   uint32_t *gpu_list;
433
434   /* The buffer where the descriptors have been uploaded. */
435   struct si_resource *buffer;
436   uint64_t gpu_address;
437
438   /* The maximum number of descriptors. */
439   uint32_t num_elements;
440
441   /* Slots that are used by currently-bound shaders.
442    * It determines which slots are uploaded.
443    */
444   uint32_t first_active_slot;
445   uint32_t num_active_slots;
446
447   /* The SH register offset relative to USER_DATA*_0 where the pointer
448    * to the descriptor array will be stored. */
449   short shader_userdata_offset;
450   /* The size of one descriptor. */
451   ubyte element_dw_size;
452   /* If there is only one slot enabled, bind it directly instead of
453    * uploading descriptors. -1 if disabled. */
454   signed char slot_index_to_bind_directly;
455};
456
457struct si_buffer_resources {
458   struct pipe_resource **buffers; /* this has num_buffers elements */
459   unsigned *offsets;              /* this has num_buffers elements */
460
461   unsigned priority;
462   unsigned priority_constbuf;
463
464   /* The i-th bit is set if that element is enabled (non-NULL resource). */
465   uint64_t enabled_mask;
466   uint64_t writable_mask;
467};
468
469#define si_pm4_state_changed(sctx, member)                                                         \
470   ((sctx)->queued.named.member != (sctx)->emitted.named.member)
471
472#define si_pm4_state_enabled_and_changed(sctx, member)                                             \
473   ((sctx)->queued.named.member && si_pm4_state_changed(sctx, member))
474
475#define si_pm4_bind_state(sctx, member, value)                                                     \
476   do {                                                                                            \
477      (sctx)->queued.named.member = (value);                                                       \
478      if (value && value != (sctx)->emitted.named.member)                                          \
479         (sctx)->dirty_states |= SI_STATE_BIT(member);                                             \
480      else                                                                                         \
481         (sctx)->dirty_states &= ~SI_STATE_BIT(member);                                            \
482   } while (0)
483
484/* si_descriptors.c */
485void si_get_inline_uniform_state(union si_shader_key *key, enum pipe_shader_type shader,
486                                 bool *inline_uniforms, uint32_t **inlined_values);
487void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture *tex,
488                                    const struct legacy_surf_level *base_level_info,
489                                    unsigned base_level, unsigned first_level, unsigned block_width,
490                                    /* restrict decreases overhead of si_set_sampler_view_desc ~8x. */
491                                    bool is_stencil, uint16_t access, uint32_t * restrict state);
492void si_update_ps_colorbuf0_slot(struct si_context *sctx);
493void si_invalidate_inlinable_uniforms(struct si_context *sctx, enum pipe_shader_type shader);
494void si_get_pipe_constant_buffer(struct si_context *sctx, uint shader, uint slot,
495                                 struct pipe_constant_buffer *cbuf);
496void si_set_shader_buffers(struct pipe_context *ctx, enum pipe_shader_type shader,
497                           unsigned start_slot, unsigned count,
498                           const struct pipe_shader_buffer *sbuffers,
499                           unsigned writable_bitmask, bool internal_blit);
500void si_get_shader_buffers(struct si_context *sctx, enum pipe_shader_type shader, uint start_slot,
501                           uint count, struct pipe_shader_buffer *sbuf);
502void si_set_ring_buffer(struct si_context *sctx, uint slot, struct pipe_resource *buffer,
503                        unsigned stride, unsigned num_records, bool add_tid, bool swizzle,
504                        unsigned element_size, unsigned index_stride, uint64_t offset);
505void si_init_all_descriptors(struct si_context *sctx);
506bool si_upload_graphics_shader_descriptors(struct si_context *sctx);
507bool si_upload_compute_shader_descriptors(struct si_context *sctx);
508void si_release_all_descriptors(struct si_context *sctx);
509void si_gfx_resources_add_all_to_bo_list(struct si_context *sctx);
510void si_compute_resources_add_all_to_bo_list(struct si_context *sctx);
511bool si_gfx_resources_check_encrypted(struct si_context *sctx);
512bool si_compute_resources_check_encrypted(struct si_context *sctx);
513void si_shader_pointers_mark_dirty(struct si_context *sctx);
514void si_add_all_descriptors_to_bo_list(struct si_context *sctx);
515void si_update_all_texture_descriptors(struct si_context *sctx);
516void si_shader_change_notify(struct si_context *sctx);
517void si_update_needs_color_decompress_masks(struct si_context *sctx);
518void si_emit_graphics_shader_pointers(struct si_context *sctx);
519void si_emit_compute_shader_pointers(struct si_context *sctx);
520void si_set_internal_const_buffer(struct si_context *sctx, uint slot,
521                                  const struct pipe_constant_buffer *input);
522void si_set_internal_shader_buffer(struct si_context *sctx, uint slot,
523                                   const struct pipe_shader_buffer *sbuffer);
524void si_set_active_descriptors(struct si_context *sctx, unsigned desc_idx,
525                               uint64_t new_active_mask);
526void si_set_active_descriptors_for_shader(struct si_context *sctx, struct si_shader_selector *sel);
527bool si_bindless_descriptor_can_reclaim_slab(void *priv, struct pb_slab_entry *entry);
528struct pb_slab *si_bindless_descriptor_slab_alloc(void *priv, unsigned heap, unsigned entry_size,
529                                                  unsigned group_index);
530void si_bindless_descriptor_slab_free(void *priv, struct pb_slab *pslab);
531void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf);
532/* si_state.c */
533uint32_t si_translate_colorformat(enum amd_gfx_level gfx_level, enum pipe_format format);
534void si_init_state_compute_functions(struct si_context *sctx);
535void si_init_state_functions(struct si_context *sctx);
536void si_init_screen_state_functions(struct si_screen *sscreen);
537void si_init_cs_preamble_state(struct si_context *sctx, bool uses_reg_shadowing);
538void si_make_buffer_descriptor(struct si_screen *screen, struct si_resource *buf,
539                               enum pipe_format format, unsigned offset, unsigned num_elements,
540                               uint32_t *state);
541void si_set_sampler_depth_decompress_mask(struct si_context *sctx, struct si_texture *tex);
542void si_update_fb_dirtiness_after_rendering(struct si_context *sctx);
543void si_mark_display_dcc_dirty(struct si_context *sctx, struct si_texture *tex);
544void si_update_ps_iter_samples(struct si_context *sctx);
545void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st);
546void si_restore_qbo_state(struct si_context *sctx, struct si_qbo_state *st);
547void si_set_occlusion_query_state(struct si_context *sctx, bool old_perfect_enable);
548unsigned gfx103_get_cu_mask_ps(struct si_screen *sscreen);
549
550struct si_fast_udiv_info32 {
551   unsigned multiplier; /* the "magic number" multiplier */
552   unsigned pre_shift;  /* shift for the dividend before multiplying */
553   unsigned post_shift; /* shift for the dividend after multiplying */
554   int increment;       /* 0 or 1; if set then increment the numerator, using one of
555                           the two strategies */
556};
557
558struct si_fast_udiv_info32 si_compute_fast_udiv_info32(uint32_t D, unsigned num_bits);
559
560/* si_state_binning.c */
561void si_emit_dpbb_state(struct si_context *sctx);
562
563/* si_state_shaders.cpp */
564struct si_pm4_state *si_build_vgt_shader_config(struct si_screen *screen, union si_vgt_stages_key key);
565void si_get_ir_cache_key(struct si_shader_selector *sel, bool ngg, bool es,
566                         unsigned wave_size, unsigned char ir_sha1_cache_key[20]);
567bool si_shader_cache_load_shader(struct si_screen *sscreen, unsigned char ir_sha1_cache_key[20],
568                                 struct si_shader *shader);
569void si_shader_cache_insert_shader(struct si_screen *sscreen, unsigned char ir_sha1_cache_key[20],
570                                   struct si_shader *shader, bool insert_into_disk_cache);
571bool si_shader_mem_ordered(struct si_shader *shader);
572void si_init_screen_live_shader_cache(struct si_screen *sscreen);
573void si_init_shader_functions(struct si_context *sctx);
574bool si_init_shader_cache(struct si_screen *sscreen);
575void si_destroy_shader_cache(struct si_screen *sscreen);
576void si_schedule_initial_compile(struct si_context *sctx, gl_shader_stage stage,
577                                 struct util_queue_fence *ready_fence,
578                                 struct si_compiler_ctx_state *compiler_ctx_state, void *job,
579                                 util_queue_execute_func execute);
580void si_get_active_slot_masks(struct si_screen *sscreen, const struct si_shader_info *info,
581                              uint64_t *const_and_shader_buffers, uint64_t *samplers_and_images);
582int si_shader_select(struct pipe_context *ctx, struct si_shader_ctx_state *state);
583void si_vs_key_update_inputs(struct si_context *sctx);
584void si_get_vs_key_inputs(struct si_context *sctx, union si_shader_key *key,
585                          struct si_vs_prolog_bits *prolog_key);
586void si_update_ps_inputs_read_or_disabled(struct si_context *sctx);
587void si_update_vrs_flat_shading(struct si_context *sctx);
588unsigned si_get_input_prim(const struct si_shader_selector *gs, const union si_shader_key *key);
589bool si_update_ngg(struct si_context *sctx);
590void si_ps_key_update_framebuffer(struct si_context *sctx);
591void si_ps_key_update_framebuffer_blend(struct si_context *sctx);
592void si_ps_key_update_blend_rasterizer(struct si_context *sctx);
593void si_ps_key_update_rasterizer(struct si_context *sctx);
594void si_ps_key_update_dsa(struct si_context *sctx);
595void si_ps_key_update_sample_shading(struct si_context *sctx);
596void si_ps_key_update_framebuffer_rasterizer_sample_shading(struct si_context *sctx);
597void si_init_tess_factor_ring(struct si_context *sctx);
598bool si_update_gs_ring_buffers(struct si_context *sctx);
599bool si_update_spi_tmpring_size(struct si_context *sctx, unsigned bytes);
600unsigned si_get_shader_prefetch_size(struct si_shader *shader);
601bool si_set_tcs_to_fixed_func_shader(struct si_context *sctx);
602
603/* si_state_draw.cpp */
604void si_cp_dma_prefetch(struct si_context *sctx, struct pipe_resource *buf,
605                        unsigned offset, unsigned size);
606void si_set_vertex_buffer_descriptor(struct si_screen *sscreen, struct si_vertex_elements *velems,
607                                     struct pipe_vertex_buffer *vb, unsigned element_index,
608                                     uint32_t *out);
609void si_init_draw_functions_GFX6(struct si_context *sctx);
610void si_init_draw_functions_GFX7(struct si_context *sctx);
611void si_init_draw_functions_GFX8(struct si_context *sctx);
612void si_init_draw_functions_GFX9(struct si_context *sctx);
613void si_init_draw_functions_GFX10(struct si_context *sctx);
614void si_init_draw_functions_GFX10_3(struct si_context *sctx);
615void si_init_draw_functions_GFX11(struct si_context *sctx);
616void si_init_spi_map_functions(struct si_context *sctx);
617
618/* si_state_msaa.c */
619void si_init_msaa_functions(struct si_context *sctx);
620void si_emit_sample_locations(struct radeon_cmdbuf *cs, int nr_samples);
621
622/* si_state_streamout.c */
623void si_streamout_buffers_dirty(struct si_context *sctx);
624void si_emit_streamout_end(struct si_context *sctx);
625void si_update_prims_generated_query_state(struct si_context *sctx, unsigned type, int diff);
626void si_init_streamout_functions(struct si_context *sctx);
627
628static inline unsigned si_get_constbuf_slot(unsigned slot)
629{
630   /* Constant buffers are in slots [32..47], ascending */
631   return SI_NUM_SHADER_BUFFERS + slot;
632}
633
634static inline unsigned si_get_shaderbuf_slot(unsigned slot)
635{
636   /* shader buffers are in slots [31..0], descending */
637   return SI_NUM_SHADER_BUFFERS - 1 - slot;
638}
639
640static inline unsigned si_get_sampler_slot(unsigned slot)
641{
642   /* 32 samplers are in sampler slots [16..47], 16 dw per slot, ascending */
643   /* those are equivalent to image slots [32..95], 8 dw per slot, ascending  */
644   return SI_NUM_IMAGE_SLOTS / 2 + slot;
645}
646
647static inline unsigned si_get_image_slot(unsigned slot)
648{
649   /* image slots are in [31..0] (sampler slots [15..0]), descending */
650   /* images are in slots [31..16], while FMASKs are in slots [15..0] */
651   return SI_NUM_IMAGE_SLOTS - 1 - slot;
652}
653
654static inline unsigned si_clamp_texture_texel_count(unsigned max_texel_buffer_elements,
655                                                    enum pipe_format format,
656                                                    uint32_t size)
657{
658   /* The spec says:
659    *    The number of texels in the texel array is then clamped to the value of
660    *    the implementation-dependent limit GL_MAX_TEXTURE_BUFFER_SIZE.
661    *
662    * So compute the number of texels, compare to GL_MAX_TEXTURE_BUFFER_SIZE and update it.
663    */
664   unsigned stride = util_format_get_blocksize(format);
665   return MIN2(max_texel_buffer_elements, size / stride);
666}
667
668#ifdef __cplusplus
669}
670#endif
671
672#endif
673