1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * Copyright 2018 Advanced Micro Devices, Inc. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * on the rights to use, copy, modify, merge, publish, distribute, sub 10 * license, and/or sell copies of the Software, and to permit persons to whom 11 * the Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 23 * USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25#ifndef SI_PIPE_H 26#define SI_PIPE_H 27 28#include "si_shader.h" 29#include "si_state.h" 30#include "util/u_dynarray.h" 31#include "util/u_idalloc.h" 32#include "util/u_suballoc.h" 33#include "util/u_threaded_context.h" 34#include "util/u_vertex_state_cache.h" 35#include "ac_sqtt.h" 36#include "ac_spm.h" 37 38#ifdef __cplusplus 39extern "C" { 40#endif 41 42#if UTIL_ARCH_BIG_ENDIAN 43#define SI_BIG_ENDIAN 1 44#else 45#define SI_BIG_ENDIAN 0 46#endif 47 48#define ATI_VENDOR_ID 0x1002 49#define SI_NOT_QUERY 0xffffffff 50 51/* The base vertex and primitive restart can be any number, but we must pick 52 * one which will mean "unknown" for the purpose of state tracking and 53 * the number shouldn't be a commonly-used one. */ 54#define SI_BASE_VERTEX_UNKNOWN INT_MIN 55#define SI_START_INSTANCE_UNKNOWN ((unsigned)INT_MIN) 56#define SI_DRAW_ID_UNKNOWN ((unsigned)INT_MIN) 57#define SI_RESTART_INDEX_UNKNOWN ((unsigned)INT_MIN) 58#define SI_INSTANCE_COUNT_UNKNOWN ((unsigned)INT_MIN) 59#define SI_NUM_SMOOTH_AA_SAMPLES 4 60#define SI_MAX_POINT_SIZE 2048 61#define SI_GS_PER_ES 128 62/* Alignment for optimal CP DMA performance. */ 63#define SI_CPDMA_ALIGNMENT 32 64 65/* Tunables for compute-based clear_buffer and copy_buffer: */ 66#define SI_COMPUTE_CLEAR_DW_PER_THREAD 4 67#define SI_COMPUTE_COPY_DW_PER_THREAD 4 68/* L2 LRU is recommended because the compute shader can finish sooner due to fewer L2 evictions. */ 69#define SI_COMPUTE_DST_CACHE_POLICY L2_LRU 70 71/* Pipeline & streamout query controls. */ 72#define SI_CONTEXT_START_PIPELINE_STATS (1 << 0) 73#define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1) 74#define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2) 75/* Instruction cache. */ 76#define SI_CONTEXT_INV_ICACHE (1 << 3) 77/* Scalar cache. (GFX6-9: scalar L1; GFX10: scalar L0) 78 * GFX10: This also invalidates the L1 shader array cache. */ 79#define SI_CONTEXT_INV_SCACHE (1 << 4) 80/* Vector cache. (GFX6-9: vector L1; GFX10: vector L0) 81 * GFX10: This also invalidates the L1 shader array cache. */ 82#define SI_CONTEXT_INV_VCACHE (1 << 5) 83/* L2 cache + L2 metadata cache writeback & invalidate. 84 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */ 85#define SI_CONTEXT_INV_L2 (1 << 6) 86/* L2 writeback (write dirty L2 lines to memory for non-L2 clients). 87 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8. 88 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */ 89#define SI_CONTEXT_WB_L2 (1 << 7) 90/* Writeback & invalidate the L2 metadata cache only. It can only be coupled with 91 * a CB or DB flush. */ 92#define SI_CONTEXT_INV_L2_METADATA (1 << 8) 93/* Framebuffer caches. */ 94#define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9) 95#define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10) 96#define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11) 97/* Engine synchronization. */ 98#define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12) 99#define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13) 100#define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14) 101#define SI_CONTEXT_VGT_FLUSH (1 << 15) 102#define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16) 103/* PFP waits for ME to finish. Used to sync for index and indirect buffers and render 104 * condition. It's typically set when doing a VS/PS/CS partial flush for buffers. */ 105#define SI_CONTEXT_PFP_SYNC_ME (1 << 17) 106 107#define SI_PREFETCH_LS (1 << 1) 108#define SI_PREFETCH_HS (1 << 2) 109#define SI_PREFETCH_ES (1 << 3) 110#define SI_PREFETCH_GS (1 << 4) 111#define SI_PREFETCH_VS (1 << 5) 112#define SI_PREFETCH_PS (1 << 6) 113 114#define SI_MAX_BORDER_COLORS 4096 115#define SI_MAX_VIEWPORTS 16 116#define SI_MAP_BUFFER_ALIGNMENT 64 117/* We only support the minimum allowed value (512), so that we can pack a 3D block size 118 * in 1 SGPR. */ 119#define SI_MAX_VARIABLE_THREADS_PER_BLOCK 512 120 121#define SI_CONTEXT_FLAG_AUX (1u << 31) 122 123#define SI_RESOURCE_FLAG_FORCE_LINEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 0) 124#define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1) 125#define SI_RESOURCE_FLAG_FORCE_MSAA_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2) 126#define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3) 127#define SI_RESOURCE_FLAG_DRIVER_INTERNAL (PIPE_RESOURCE_FLAG_DRV_PRIV << 4) 128#define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5) 129#define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6) 130#define SI_RESOURCE_FLAG_CLEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 7) 131#define SI_RESOURCE_AUX_PLANE (PIPE_RESOURCE_FLAG_DRV_PRIV << 8) 132/* Set a micro tile mode: */ 133#define SI_RESOURCE_FLAG_FORCE_MICRO_TILE_MODE (PIPE_RESOURCE_FLAG_DRV_PRIV << 9) 134#define SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT (util_logbase2(PIPE_RESOURCE_FLAG_DRV_PRIV) + 10) 135#define SI_RESOURCE_FLAG_MICRO_TILE_MODE_SET(x) \ 136 (((x)&0x3) << SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT) 137#define SI_RESOURCE_FLAG_MICRO_TILE_MODE_GET(x) \ 138 (((x) >> SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT) & 0x3) 139#define SI_RESOURCE_FLAG_GL2_BYPASS (PIPE_RESOURCE_FLAG_DRV_PRIV << 12) 140/* Discard instead of evict. */ 141#define SI_RESOURCE_FLAG_DISCARDABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 13) 142 143enum si_has_gs { 144 GS_OFF, 145 GS_ON, 146}; 147 148enum si_has_tess { 149 TESS_OFF, 150 TESS_ON, 151}; 152 153enum si_has_ngg { 154 NGG_OFF, 155 NGG_ON, 156}; 157 158#define DCC_CODE(x) (((x) << 24) | ((x) << 16) | ((x) << 8) | (x)) 159 160enum si_clear_code 161{ 162 /* Common clear codes. */ 163 DCC_CLEAR_0000 = DCC_CODE(0x00), /* all bits are 0 */ 164 DCC_UNCOMPRESSED = DCC_CODE(0xFF), 165 166 GFX8_DCC_CLEAR_0000 = DCC_CLEAR_0000, 167 GFX8_DCC_CLEAR_0001 = DCC_CODE(0x40), 168 GFX8_DCC_CLEAR_1110 = DCC_CODE(0x80), 169 GFX8_DCC_CLEAR_1111 = DCC_CODE(0xC0), 170 GFX8_DCC_CLEAR_REG = DCC_CODE(0x20), 171 GFX9_DCC_CLEAR_SINGLE = DCC_CODE(0x10), 172 173 GFX11_DCC_CLEAR_SINGLE = DCC_CODE(0x01), 174 GFX11_DCC_CLEAR_0000 = DCC_CLEAR_0000, /* all bits are 0 */ 175 GFX11_DCC_CLEAR_1111_UNORM = DCC_CODE(0x02), /* all bits are 1 */ 176 GFX11_DCC_CLEAR_1111_FP16 = DCC_CODE(0x04), /* all 16-bit words are 0x3c00, max 64bpp */ 177 GFX11_DCC_CLEAR_1111_FP32 = DCC_CODE(0x06), /* all 32-bit words are 0x3f800000 */ 178 /* Color bits are 0, alpha bits are 1; only 88, 8888, 16161616 with alpha_on_msb=1 */ 179 GFX11_DCC_CLEAR_0001_UNORM = DCC_CODE(0x08), 180 /* Color bits are 1, alpha bits are 0, only 88, 8888, 16161616 with alpha_on_msb=1 */ 181 GFX11_DCC_CLEAR_1110_UNORM = DCC_CODE(0x0A), 182}; 183 184#define SI_IMAGE_ACCESS_DCC_OFF (1 << 8) 185#define SI_IMAGE_ACCESS_ALLOW_DCC_STORE (1 << 9) 186#define SI_IMAGE_ACCESS_BLOCK_FORMAT_AS_UINT (1 << 10) /* for compressed/subsampled images */ 187 188/* Debug flags. */ 189enum 190{ 191 /* Shader logging options: */ 192 DBG_VS = MESA_SHADER_VERTEX, 193 DBG_TCS = MESA_SHADER_TESS_CTRL, 194 DBG_TES = MESA_SHADER_TESS_EVAL, 195 DBG_GS = MESA_SHADER_GEOMETRY, 196 DBG_PS = MESA_SHADER_FRAGMENT, 197 DBG_CS = MESA_SHADER_COMPUTE, 198 DBG_NO_IR, 199 DBG_NO_NIR, 200 DBG_NO_ASM, 201 DBG_PREOPT_IR, 202 203 /* Shader compiler options the shader cache should be aware of: */ 204 DBG_FS_CORRECT_DERIVS_AFTER_KILL, 205 DBG_W32_GE, 206 DBG_W32_PS, 207 DBG_W32_PS_DISCARD, 208 DBG_W32_CS, 209 DBG_W64_GE, 210 DBG_W64_PS, 211 DBG_W64_CS, 212 213 /* Shader compiler options (with no effect on the shader cache): */ 214 DBG_CHECK_IR, 215 DBG_MONOLITHIC_SHADERS, 216 DBG_NO_OPT_VARIANT, 217 218 /* Information logging options: */ 219 DBG_INFO, 220 DBG_TEX, 221 DBG_COMPUTE, 222 DBG_VM, 223 DBG_CACHE_STATS, 224 DBG_IB, 225 226 /* Driver options: */ 227 DBG_NO_WC, 228 DBG_CHECK_VM, 229 DBG_RESERVE_VMID, 230 DBG_SHADOW_REGS, 231 DBG_NO_FAST_DISPLAY_LIST, 232 233 /* Multimedia options: */ 234 DBG_NO_EFC, 235 236 /* 3D engine options: */ 237 DBG_NO_GFX, 238 DBG_NO_NGG, 239 DBG_ALWAYS_NGG_CULLING_ALL, 240 DBG_NO_NGG_CULLING, 241 DBG_SWITCH_ON_EOP, 242 DBG_NO_OUT_OF_ORDER, 243 DBG_NO_DPBB, 244 DBG_DPBB, 245 DBG_NO_HYPERZ, 246 DBG_NO_2D_TILING, 247 DBG_NO_TILING, 248 DBG_NO_DISPLAY_TILING, 249 DBG_NO_DISPLAY_DCC, 250 DBG_NO_EXPORTED_DCC, 251 DBG_NO_DCC, 252 DBG_NO_DCC_CLEAR, 253 DBG_NO_DCC_STORE, 254 DBG_DCC_STORE, 255 DBG_NO_DCC_MSAA, 256 DBG_NO_FMASK, 257 DBG_NO_DMA, 258 259 DBG_TMZ, 260 DBG_SQTT, 261 262 DBG_COUNT 263}; 264 265enum 266{ 267 /* Tests: */ 268 DBG_TEST_IMAGE_COPY, 269 DBG_TEST_CB_RESOLVE, 270 DBG_TEST_COMPUTE_BLIT, 271 DBG_TEST_VMFAULT_CP, 272 DBG_TEST_VMFAULT_SHADER, 273 DBG_TEST_DMA_PERF, 274 DBG_TEST_GDS, 275 DBG_TEST_GDS_MM, 276 DBG_TEST_GDS_OA_MM, 277}; 278 279#define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1)) 280#define DBG(name) (1ull << DBG_##name) 281 282enum si_cache_policy 283{ 284 L2_BYPASS, 285 L2_STREAM, /* same as SLC=1 */ 286 L2_LRU, /* same as SLC=0 */ 287}; 288 289enum si_coherency 290{ 291 SI_COHERENCY_NONE, /* no cache flushes needed */ 292 SI_COHERENCY_SHADER, 293 SI_COHERENCY_CB_META, 294 SI_COHERENCY_DB_META, 295 SI_COHERENCY_CP, 296}; 297 298#define SI_BIND_CONSTANT_BUFFER_SHIFT 0 299#define SI_BIND_SHADER_BUFFER_SHIFT 6 300#define SI_BIND_IMAGE_BUFFER_SHIFT 12 301#define SI_BIND_SAMPLER_BUFFER_SHIFT 18 302#define SI_BIND_OTHER_BUFFER_SHIFT 24 303 304/* Bind masks for all 6 shader stages. */ 305#define SI_BIND_CONSTANT_BUFFER_ALL (0x3f << SI_BIND_CONSTANT_BUFFER_SHIFT) 306#define SI_BIND_SHADER_BUFFER_ALL (0x3f << SI_BIND_SHADER_BUFFER_SHIFT) 307#define SI_BIND_IMAGE_BUFFER_ALL (0x3f << SI_BIND_IMAGE_BUFFER_SHIFT) 308#define SI_BIND_SAMPLER_BUFFER_ALL (0x3f << SI_BIND_SAMPLER_BUFFER_SHIFT) 309 310#define SI_BIND_CONSTANT_BUFFER(shader) ((1 << (shader)) << SI_BIND_CONSTANT_BUFFER_SHIFT) 311#define SI_BIND_SHADER_BUFFER(shader) ((1 << (shader)) << SI_BIND_SHADER_BUFFER_SHIFT) 312#define SI_BIND_IMAGE_BUFFER(shader) ((1 << (shader)) << SI_BIND_IMAGE_BUFFER_SHIFT) 313#define SI_BIND_SAMPLER_BUFFER(shader) ((1 << (shader)) << SI_BIND_SAMPLER_BUFFER_SHIFT) 314#define SI_BIND_VERTEX_BUFFER (1 << (SI_BIND_OTHER_BUFFER_SHIFT + 0)) 315#define SI_BIND_STREAMOUT_BUFFER (1 << (SI_BIND_OTHER_BUFFER_SHIFT + 1)) 316 317struct si_compute; 318struct si_shader_context; 319struct hash_table; 320 321/* Only 32-bit buffer allocations are supported, gallium doesn't support more 322 * at the moment. 323 */ 324struct si_resource { 325 struct threaded_resource b; 326 327 /* Winsys objects. */ 328 struct pb_buffer *buf; 329 uint64_t gpu_address; 330 /* Memory usage if the buffer placement is optimal. */ 331 uint32_t memory_usage_kb; 332 333 /* Resource properties. */ 334 uint64_t bo_size; 335 uint8_t bo_alignment_log2; 336 enum radeon_bo_domain domains:8; 337 enum radeon_bo_flag flags:16; 338 unsigned bind_history; /* bitmask of SI_BIND_xxx_BUFFER */ 339 340 /* The buffer range which is initialized (with a write transfer, 341 * streamout, DMA, or as a random access target). The rest of 342 * the buffer is considered invalid and can be mapped unsynchronized. 343 * 344 * This allows unsynchronized mapping of a buffer range which hasn't 345 * been used yet. It's for applications which forget to use 346 * the unsynchronized map flag and expect the driver to figure it out. 347 */ 348 struct util_range valid_buffer_range; 349 350 /* For buffers only. This indicates that a write operation has been 351 * performed by TC L2, but the cache hasn't been flushed. 352 * Any hw block which doesn't use or bypasses TC L2 should check this 353 * flag and flush the cache before using the buffer. 354 * 355 * For example, TC L2 must be flushed if a buffer which has been 356 * modified by a shader store instruction is about to be used as 357 * an index buffer. The reason is that VGT DMA index fetching doesn't 358 * use TC L2. 359 */ 360 bool TC_L2_dirty; 361 362 /* Whether this resource is referenced by bindless handles. */ 363 bool texture_handle_allocated; 364 bool image_handle_allocated; 365 366 /* Whether the resource has been exported via resource_get_handle. */ 367 uint8_t external_usage; /* PIPE_HANDLE_USAGE_* */ 368}; 369 370struct si_transfer { 371 struct threaded_transfer b; 372 struct si_resource *staging; 373}; 374 375struct si_texture { 376 struct si_resource buffer; 377 378 struct radeon_surf surface; 379 struct si_texture *flushed_depth_texture; 380 381 /* One texture allocation can contain these buffers: 382 * - image (pixel data) 383 * - FMASK buffer (MSAA compression) 384 * - CMASK buffer (MSAA compression and/or legacy fast color clear) 385 * - HTILE buffer (Z/S compression and fast Z/S clear) 386 * - DCC buffer (color compression and new fast color clear) 387 * - displayable DCC buffer (if the DCC buffer is not displayable) 388 */ 389 uint64_t cmask_base_address_reg; 390 struct si_resource *cmask_buffer; 391 unsigned cb_color_info; /* fast clear enable bit */ 392 unsigned color_clear_value[2]; /* not on gfx11 */ 393 unsigned last_msaa_resolve_target_micro_mode; 394 bool swap_rgb_to_bgr_on_next_clear; 395 bool swap_rgb_to_bgr; 396 unsigned num_level0_transfers; 397 unsigned plane_index; /* other planes are different pipe_resources */ 398 unsigned num_planes; 399 400 /* Depth buffer compression and fast clear. */ 401 float depth_clear_value[RADEON_SURF_MAX_LEVELS]; 402 uint8_t stencil_clear_value[RADEON_SURF_MAX_LEVELS]; 403 uint16_t depth_cleared_level_mask_once; /* if it was cleared at least once */ 404 uint16_t depth_cleared_level_mask; /* track if it's cleared (can be false negative) */ 405 uint16_t stencil_cleared_level_mask_once; /* if it was cleared at least once */ 406 uint16_t dirty_level_mask; /* each bit says if that mipmap is compressed */ 407 uint16_t stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */ 408 enum pipe_format db_render_format : 16; 409 bool fmask_is_identity : 1; 410 bool tc_compatible_htile : 1; 411 bool enable_tc_compatible_htile_next_clear : 1; 412 bool htile_stencil_disabled : 1; 413 bool upgraded_depth : 1; /* upgraded from unorm to Z32_FLOAT */ 414 bool is_depth : 1; 415 bool db_compatible : 1; 416 bool can_sample_z : 1; 417 bool can_sample_s : 1; 418 bool need_flush_after_depth_decompression: 1; 419 420 /* We need to track DCC dirtiness, because st/dri usually calls 421 * flush_resource twice per frame (not a bug) and we don't wanna 422 * decompress DCC twice. 423 */ 424 bool displayable_dcc_dirty : 1; 425 426 /* Counter that should be non-zero if the texture is bound to a 427 * framebuffer. 428 */ 429 unsigned framebuffers_bound; 430}; 431 432/* State trackers create separate textures in a next-chain for extra planes 433 * even if those are planes created purely for modifiers. Because the linking 434 * of the chain happens outside of the driver, and NULL is interpreted as 435 * failure, let's create some dummy texture structs. We could use these 436 * later to use the offsets for linking if we really wanted to. 437 * 438 * For now just create a dummy struct and completely ignore it. 439 * 440 * Potentially in the future we could store stride/offset and use it during 441 * creation, though we might want to change how linking is done first. 442 */ 443struct si_auxiliary_texture { 444 struct threaded_resource b; 445 struct pb_buffer *buffer; 446 uint32_t offset; 447 uint32_t stride; 448}; 449 450struct si_surface { 451 struct pipe_surface base; 452 453 /* These can vary with block-compressed textures. */ 454 uint16_t width0; 455 uint16_t height0; 456 457 bool color_initialized : 1; 458 bool depth_initialized : 1; 459 460 /* Misc. color flags. */ 461 bool color_is_int8 : 1; 462 bool color_is_int10 : 1; 463 bool dcc_incompatible : 1; 464 465 /* Color registers. */ 466 unsigned cb_color_info; 467 unsigned cb_color_view; 468 unsigned cb_color_attrib; 469 unsigned cb_color_attrib2; /* GFX9 and later */ 470 unsigned cb_color_attrib3; /* GFX10 and later */ 471 unsigned cb_dcc_control; /* GFX8 and later */ 472 unsigned spi_shader_col_format : 8; /* no blending, no alpha-to-coverage. */ 473 unsigned spi_shader_col_format_alpha : 8; /* alpha-to-coverage */ 474 unsigned spi_shader_col_format_blend : 8; /* blending without alpha. */ 475 unsigned spi_shader_col_format_blend_alpha : 8; /* blending with alpha. */ 476 477 /* DB registers. */ 478 uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE */ 479 uint64_t db_stencil_base; 480 uint64_t db_htile_data_base; 481 unsigned db_depth_info; 482 unsigned db_z_info; 483 unsigned db_z_info2; /* GFX9 only */ 484 unsigned db_depth_view; 485 unsigned db_depth_size; 486 unsigned db_depth_slice; 487 unsigned db_stencil_info; 488 unsigned db_stencil_info2; /* GFX9 only */ 489 unsigned db_htile_surface; 490}; 491 492struct si_mmio_counter { 493 unsigned busy; 494 unsigned idle; 495}; 496 497union si_mmio_counters { 498 struct si_mmio_counters_named { 499 /* For global GPU load including SDMA. */ 500 struct si_mmio_counter gpu; 501 502 /* GRBM_STATUS */ 503 struct si_mmio_counter spi; 504 struct si_mmio_counter gui; 505 struct si_mmio_counter ta; 506 struct si_mmio_counter gds; 507 struct si_mmio_counter vgt; 508 struct si_mmio_counter ia; 509 struct si_mmio_counter sx; 510 struct si_mmio_counter wd; 511 struct si_mmio_counter bci; 512 struct si_mmio_counter sc; 513 struct si_mmio_counter pa; 514 struct si_mmio_counter db; 515 struct si_mmio_counter cp; 516 struct si_mmio_counter cb; 517 518 /* SRBM_STATUS2 */ 519 struct si_mmio_counter sdma; 520 521 /* CP_STAT */ 522 struct si_mmio_counter pfp; 523 struct si_mmio_counter meq; 524 struct si_mmio_counter me; 525 struct si_mmio_counter surf_sync; 526 struct si_mmio_counter cp_dma; 527 struct si_mmio_counter scratch_ram; 528 } named; 529 530 unsigned array[sizeof(struct si_mmio_counters_named) / sizeof(unsigned)]; 531}; 532 533struct si_memory_object { 534 struct pipe_memory_object b; 535 struct pb_buffer *buf; 536 uint32_t stride; 537}; 538 539/* Saved CS data for debugging features. */ 540struct radeon_saved_cs { 541 uint32_t *ib; 542 unsigned num_dw; 543 544 struct radeon_bo_list_item *bo_list; 545 unsigned bo_count; 546}; 547 548struct si_screen { 549 struct pipe_screen b; 550 struct radeon_winsys *ws; 551 struct disk_cache *disk_shader_cache; 552 553 struct radeon_info info; 554 struct nir_shader_compiler_options nir_options; 555 uint64_t debug_flags; 556 char renderer_string[183]; 557 558 void (*make_texture_descriptor)(struct si_screen *screen, struct si_texture *tex, bool sampler, 559 enum pipe_texture_target target, enum pipe_format pipe_format, 560 const unsigned char state_swizzle[4], unsigned first_level, 561 unsigned last_level, unsigned first_layer, unsigned last_layer, 562 unsigned width, unsigned height, unsigned depth, uint32_t *state, 563 uint32_t *fmask_state); 564 565 unsigned max_memory_usage_kb; 566 unsigned pa_sc_raster_config; 567 unsigned pa_sc_raster_config_1; 568 unsigned se_tile_repeat; 569 unsigned gs_table_depth; 570 struct ac_hs_info hs; 571 unsigned eqaa_force_coverage_samples; 572 unsigned eqaa_force_z_samples; 573 unsigned eqaa_force_color_samples; 574 unsigned pbb_context_states_per_bin; 575 unsigned pbb_persistent_states_per_bin; 576 bool has_draw_indirect_multi; 577 bool has_out_of_order_rast; 578 bool dpbb_allowed; 579 bool use_ngg; 580 bool use_ngg_culling; 581 bool use_ngg_streamout; 582 bool allow_dcc_msaa_clear_to_reg_for_bpp[5]; /* indexed by log2(Bpp) */ 583 bool always_allow_dcc_stores; 584 585 struct { 586#define OPT_BOOL(name, dflt, description) bool name : 1; 587#define OPT_INT(name, dflt, description) int name; 588#include "si_debug_options.h" 589 } options; 590 591 /* Whether shaders are monolithic (1-part) or separate (3-part). */ 592 bool use_monolithic_shaders; 593 bool record_llvm_ir; 594 595 struct slab_parent_pool pool_transfers; 596 597 /* Texture filter settings. */ 598 int force_aniso; /* -1 = disabled */ 599 600 unsigned max_texel_buffer_elements; 601 602 /* Auxiliary context. Mainly used to initialize resources. */ 603 void *aux_context; 604 mtx_t aux_context_lock; 605 606 /* Async compute context for DRI_PRIME copies. */ 607 struct pipe_context *async_compute_context; 608 simple_mtx_t async_compute_context_lock; 609 610 /* This must be in the screen, because UE4 uses one context for 611 * compilation and another one for rendering. 612 */ 613 unsigned num_compilations; 614 /* Along with ST_DEBUG=precompile, this should show if applications 615 * are loading shaders on demand. This is a monotonic counter. 616 */ 617 unsigned num_shaders_created; 618 unsigned num_memory_shader_cache_hits; 619 unsigned num_memory_shader_cache_misses; 620 unsigned num_disk_shader_cache_hits; 621 unsigned num_disk_shader_cache_misses; 622 623 /* GPU load thread. */ 624 simple_mtx_t gpu_load_mutex; 625 thrd_t gpu_load_thread; 626 bool gpu_load_thread_created; 627 union si_mmio_counters mmio_counters; 628 volatile unsigned gpu_load_stop_thread; /* bool */ 629 630 /* Performance counters. */ 631 struct si_perfcounters *perfcounters; 632 633 /* If pipe_screen wants to recompute and re-emit the framebuffer, 634 * sampler, and image states of all contexts, it should atomically 635 * increment this. 636 * 637 * Each context will compare this with its own last known value of 638 * the counter before drawing and re-emit the states accordingly. 639 */ 640 unsigned dirty_tex_counter; 641 unsigned dirty_buf_counter; 642 643 /* Atomically increment this counter when an existing texture's 644 * metadata is enabled or disabled in a way that requires changing 645 * contexts' compressed texture binding masks. 646 */ 647 unsigned compressed_colortex_counter; 648 649 struct { 650 /* Context flags to set so that all writes from earlier jobs 651 * in the CP are seen by L2 clients. 652 */ 653 unsigned cp_to_L2; 654 655 /* Context flags to set so that all writes from earlier jobs 656 * that end in L2 are seen by CP. 657 */ 658 unsigned L2_to_cp; 659 } barrier_flags; 660 661 simple_mtx_t shader_parts_mutex; 662 struct si_shader_part *vs_prologs; 663 struct si_shader_part *tcs_epilogs; 664 struct si_shader_part *ps_prologs; 665 struct si_shader_part *ps_epilogs; 666 667 /* Shader cache in memory. 668 * 669 * Design & limitations: 670 * - The shader cache is per screen (= per process), never saved to 671 * disk, and skips redundant shader compilations from NIR to bytecode. 672 * - It can only be used with one-variant-per-shader support, in which 673 * case only the main (typically middle) part of shaders is cached. 674 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS 675 * variants of VS and TES are cached, so LS and ES aren't. 676 * - GS and CS aren't cached, but it's certainly possible to cache 677 * those as well. 678 */ 679 simple_mtx_t shader_cache_mutex; 680 struct hash_table *shader_cache; 681 /* Maximum and current size */ 682 uint32_t shader_cache_size; 683 uint32_t shader_cache_max_size; 684 685 /* Shader cache of live shaders. */ 686 struct util_live_shader_cache live_shader_cache; 687 688 /* Shader compiler queue for multithreaded compilation. */ 689 struct util_queue shader_compiler_queue; 690 /* Use at most 3 normal compiler threads on quadcore and better. 691 * Hyperthreaded CPUs report the number of threads, but we want 692 * the number of cores. We only need this many threads for shader-db. */ 693 struct ac_llvm_compiler compiler[24]; /* used by the queue only */ 694 695 struct util_queue shader_compiler_queue_low_priority; 696 /* Use at most 2 low priority threads on quadcore and better. 697 * We want to minimize the impact on multithreaded Mesa. */ 698 struct ac_llvm_compiler compiler_lowp[10]; 699 700 unsigned ngg_subgroup_size; 701 702 struct util_idalloc_mt buffer_ids; 703 struct util_vertex_state_cache vertex_state_cache; 704 705 struct si_resource *attribute_ring; 706 707 /* NGG streamout. */ 708 simple_mtx_t gds_mutex; 709 struct pb_buffer *gds; 710 struct pb_buffer *gds_oa; 711}; 712 713struct si_sampler_view { 714 struct pipe_sampler_view base; 715 /* [0..7] = image descriptor 716 * [4..7] = buffer descriptor */ 717 uint32_t state[8]; 718 uint32_t fmask_state[8]; 719 const struct legacy_surf_level *base_level_info; 720 ubyte block_width; 721 bool is_stencil_sampler; 722 bool dcc_incompatible; 723}; 724 725#define SI_SAMPLER_STATE_MAGIC 0x34f1c35a 726 727struct si_sampler_state { 728#ifndef NDEBUG 729 unsigned magic; 730#endif 731 uint32_t val[4]; 732 uint32_t upgraded_depth_val[4]; 733}; 734 735struct si_cs_shader_state { 736 struct si_compute *program; 737 struct si_compute *emitted_program; 738 unsigned offset; 739 bool initialized; 740}; 741 742struct si_samplers { 743 struct pipe_sampler_view *views[SI_NUM_SAMPLERS]; 744 struct si_sampler_state *sampler_states[SI_NUM_SAMPLERS]; 745 746 /* The i-th bit is set if that element is enabled (non-NULL resource). */ 747 unsigned enabled_mask; 748 uint32_t has_depth_tex_mask; 749 uint32_t needs_depth_decompress_mask; 750 uint32_t needs_color_decompress_mask; 751}; 752 753struct si_images { 754 struct pipe_image_view views[SI_NUM_IMAGES]; 755 uint32_t needs_color_decompress_mask; 756 unsigned enabled_mask; 757 unsigned display_dcc_store_mask; 758}; 759 760struct si_framebuffer { 761 struct pipe_framebuffer_state state; 762 unsigned colorbuf_enabled_4bit; 763 unsigned spi_shader_col_format; 764 unsigned spi_shader_col_format_alpha; 765 unsigned spi_shader_col_format_blend; 766 unsigned spi_shader_col_format_blend_alpha; 767 ubyte nr_samples : 5; /* at most 16xAA */ 768 ubyte log_samples : 3; /* at most 4 = 16xAA */ 769 ubyte nr_color_samples; /* at most 8xAA */ 770 ubyte compressed_cb_mask; 771 ubyte uncompressed_cb_mask; 772 ubyte color_is_int8; 773 ubyte color_is_int10; 774 ubyte dirty_cbufs; 775 ubyte min_bytes_per_pixel; 776 bool dirty_zsbuf; 777 bool any_dst_linear; 778 bool CB_has_shader_readable_metadata; 779 bool DB_has_shader_readable_metadata; 780 bool all_DCC_pipe_aligned; 781 bool has_dcc_msaa; 782}; 783 784enum si_quant_mode 785{ 786 /* This is the list we want to support. */ 787 SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH, 788 SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH, 789 SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH, 790}; 791 792struct si_signed_scissor { 793 int minx; 794 int miny; 795 int maxx; 796 int maxy; 797 enum si_quant_mode quant_mode; 798}; 799 800struct si_viewports { 801 struct pipe_viewport_state states[SI_MAX_VIEWPORTS]; 802 struct si_signed_scissor as_scissor[SI_MAX_VIEWPORTS]; 803}; 804 805struct si_streamout_target { 806 struct pipe_stream_output_target b; 807 808 /* The buffer where BUFFER_FILLED_SIZE is stored. */ 809 struct si_resource *buf_filled_size; 810 unsigned buf_filled_size_offset; 811 bool buf_filled_size_valid; 812 813 unsigned stride_in_dw; 814}; 815 816struct si_streamout { 817 bool begin_emitted; 818 819 unsigned enabled_mask; 820 unsigned num_targets; 821 struct si_streamout_target *targets[PIPE_MAX_SO_BUFFERS]; 822 823 unsigned append_bitmask; 824 bool suspended; 825 826 /* External state which comes from the vertex shader, 827 * it must be set explicitly when binding a shader. */ 828 uint8_t *stride_in_dw; 829 unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */ 830 831 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */ 832 unsigned hw_enabled_mask; 833 834 /* The state of VGT_STRMOUT_(CONFIG|EN). */ 835 bool streamout_enabled; 836 bool prims_gen_query_enabled; 837 int num_prims_gen_queries; 838}; 839 840/* A shader state consists of the shader selector, which is a constant state 841 * object shared by multiple contexts and shouldn't be modified, and 842 * the current shader variant selected for this context. 843 */ 844struct si_shader_ctx_state { 845 struct si_shader_selector *cso; 846 struct si_shader *current; 847 /* The shader variant key representing the current state. */ 848 union si_shader_key key; 849}; 850 851#define SI_NUM_VGT_PARAM_KEY_BITS 12 852#define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS) 853 854/* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values. 855 * Some fields are set by state-change calls, most are set by draw_vbo. 856 */ 857union si_vgt_param_key { 858 struct { 859#if UTIL_ARCH_LITTLE_ENDIAN 860 uint16_t prim : 4; 861 uint16_t uses_instancing : 1; 862 uint16_t multi_instances_smaller_than_primgroup : 1; 863 uint16_t primitive_restart : 1; 864 uint16_t count_from_stream_output : 1; 865 uint16_t line_stipple_enabled : 1; 866 uint16_t uses_tess : 1; 867 uint16_t tess_uses_prim_id : 1; 868 uint16_t uses_gs : 1; 869 uint16_t _pad : 16 - SI_NUM_VGT_PARAM_KEY_BITS; 870#else /* UTIL_ARCH_BIG_ENDIAN */ 871 uint16_t _pad : 16 - SI_NUM_VGT_PARAM_KEY_BITS; 872 uint16_t uses_gs : 1; 873 uint16_t tess_uses_prim_id : 1; 874 uint16_t uses_tess : 1; 875 uint16_t line_stipple_enabled : 1; 876 uint16_t count_from_stream_output : 1; 877 uint16_t primitive_restart : 1; 878 uint16_t multi_instances_smaller_than_primgroup : 1; 879 uint16_t uses_instancing : 1; 880 uint16_t prim : 4; 881#endif 882 } u; 883 uint16_t index; 884}; 885 886struct si_texture_handle { 887 unsigned desc_slot; 888 bool desc_dirty; 889 struct pipe_sampler_view *view; 890 struct si_sampler_state sstate; 891}; 892 893struct si_image_handle { 894 unsigned desc_slot; 895 bool desc_dirty; 896 struct pipe_image_view view; 897}; 898 899struct si_saved_cs { 900 struct pipe_reference reference; 901 struct si_context *ctx; 902 struct radeon_saved_cs gfx; 903 struct radeon_saved_cs compute; 904 struct si_resource *trace_buf; 905 unsigned trace_id; 906 907 unsigned gfx_last_dw; 908 bool flushed; 909 int64_t time_flush; 910}; 911 912struct si_small_prim_cull_info { 913 float scale[2], translate[2]; 914 float scale_no_aa[2], translate_no_aa[2]; 915 float clip_half_line_width[2]; /* line_width * 0.5 in clip space in X and Y directions */ 916}; 917 918struct si_vertex_state { 919 struct pipe_vertex_state b; 920 struct si_vertex_elements velems; 921 uint32_t descriptors[4 * SI_MAX_ATTRIBS]; 922}; 923 924typedef void (*pipe_draw_vbo_func)(struct pipe_context *pipe, 925 const struct pipe_draw_info *info, 926 unsigned drawid_offset, 927 const struct pipe_draw_indirect_info *indirect, 928 const struct pipe_draw_start_count_bias *draws, 929 unsigned num_draws); 930typedef void (*pipe_draw_vertex_state_func)(struct pipe_context *ctx, 931 struct pipe_vertex_state *vstate, 932 uint32_t partial_velem_mask, 933 struct pipe_draw_vertex_state_info info, 934 const struct pipe_draw_start_count_bias *draws, 935 unsigned num_draws); 936 937struct si_context { 938 struct pipe_context b; /* base class */ 939 940 enum radeon_family family; 941 enum amd_gfx_level gfx_level; 942 943 struct radeon_winsys *ws; 944 struct radeon_winsys_ctx *ctx; 945 struct radeon_cmdbuf gfx_cs; /* compute IB if graphics is disabled */ 946 struct radeon_cmdbuf *sdma_cs; 947 struct pipe_fence_handle *last_gfx_fence; 948 struct si_resource *eop_bug_scratch; 949 struct si_resource *eop_bug_scratch_tmz; 950 struct u_upload_mgr *cached_gtt_allocator; 951 struct threaded_context *tc; 952 struct u_suballocator allocator_zeroed_memory; 953 struct slab_child_pool pool_transfers; 954 struct slab_child_pool pool_transfers_unsync; /* for threaded_context */ 955 struct pipe_device_reset_callback device_reset_callback; 956 struct u_log_context *log; 957 void *query_result_shader; 958 void *sh_query_result_shader; 959 struct si_resource *shadowed_regs; 960 961 void (*emit_cache_flush)(struct si_context *ctx, struct radeon_cmdbuf *cs); 962 963 struct blitter_context *blitter; 964 void *noop_blend; 965 void *noop_dsa; 966 void *no_velems_state; 967 void *discard_rasterizer_state; 968 void *custom_dsa_flush; 969 void *custom_blend_resolve; 970 void *custom_blend_fmask_decompress; 971 void *custom_blend_eliminate_fastclear; 972 void *custom_blend_dcc_decompress; 973 void *vs_blit_pos; 974 void *vs_blit_pos_layered; 975 void *vs_blit_color; 976 void *vs_blit_color_layered; 977 void *vs_blit_texcoord; 978 void *cs_clear_buffer; 979 void *cs_clear_buffer_rmw; 980 void *cs_copy_buffer; 981 void *cs_copy_image[2][2]; /* [src_is_1d][dst_is_1d] */ 982 void *cs_clear_render_target; 983 void *cs_clear_render_target_1d_array; 984 void *cs_clear_12bytes_buffer; 985 void *cs_dcc_retile[32]; 986 void *cs_fmask_expand[3][2]; /* [log2(samples)-1][is_array] */ 987 struct si_screen *screen; 988 struct util_debug_callback debug; 989 struct ac_llvm_compiler compiler; /* only non-threaded compilation */ 990 struct hash_table *fixed_func_tcs_shader_cache; 991 struct si_resource *wait_mem_scratch; 992 struct si_resource *wait_mem_scratch_tmz; 993 unsigned wait_mem_number; 994 uint16_t prefetch_L2_mask; 995 996 bool blitter_running; 997 bool in_update_ps_colorbuf0_slot; 998 bool is_noop:1; 999 bool has_graphics:1; 1000 bool gfx_flush_in_progress : 1; 1001 bool gfx_last_ib_is_busy : 1; 1002 bool compute_is_busy : 1; 1003 int8_t pipeline_stats_enabled; /* -1 = unknown, 0 = disabled, 1 = enabled */ 1004 1005 unsigned num_gfx_cs_flushes; 1006 unsigned initial_gfx_cs_size; 1007 unsigned last_dirty_tex_counter; 1008 unsigned last_dirty_buf_counter; 1009 unsigned last_compressed_colortex_counter; 1010 unsigned last_num_draw_calls; 1011 unsigned flags; /* flush flags */ 1012 /* Current unaccounted memory usage. */ 1013 uint32_t memory_usage_kb; 1014 1015 /* Atoms (direct states). */ 1016 union si_state_atoms atoms; 1017 unsigned dirty_atoms; /* mask */ 1018 /* PM4 states (precomputed immutable states) */ 1019 unsigned dirty_states; 1020 union si_state queued; 1021 union si_state emitted; 1022 1023 /* Atom declarations. */ 1024 struct si_framebuffer framebuffer; 1025 unsigned sample_locs_num_samples; 1026 uint16_t sample_mask; 1027 unsigned last_cb_target_mask; 1028 struct pipe_blend_color blend_color; 1029 struct pipe_clip_state clip_state; 1030 struct si_shader_data shader_pointers; 1031 struct si_stencil_ref stencil_ref; 1032 bool blend_color_any_nonzeros:1; 1033 bool clip_state_any_nonzeros:1; 1034 bool viewport0_y_inverted; 1035 struct pipe_scissor_state scissors[SI_MAX_VIEWPORTS]; 1036 struct si_streamout streamout; 1037 struct si_viewports viewports; 1038 unsigned num_window_rectangles; 1039 bool window_rectangles_include; 1040 struct pipe_scissor_state window_rectangles[4]; 1041 1042 /* Precomputed states. */ 1043 struct si_pm4_state *last_preamble; 1044 struct si_pm4_state *cs_preamble_state; 1045 struct si_pm4_state *cs_preamble_state_tmz; 1046 uint16_t gs_ring_state_dw_offset; 1047 uint16_t gs_ring_state_dw_offset_tmz; 1048 bool cs_preamble_has_vgt_flush; 1049 bool cs_preamble_has_vgt_flush_tmz; 1050 1051 struct si_pm4_state *vgt_shader_config[SI_NUM_VGT_STAGES_STATES]; 1052 1053 /* shaders */ 1054 union { 1055 struct { 1056 struct si_shader_ctx_state vs; 1057 struct si_shader_ctx_state ps; 1058 struct si_shader_ctx_state gs; 1059 struct si_shader_ctx_state tcs; 1060 struct si_shader_ctx_state tes; 1061 } shader; 1062 /* indexed access using pipe_shader_type (not by MESA_SHADER_*) */ 1063 struct si_shader_ctx_state shaders[SI_NUM_GRAPHICS_SHADERS]; 1064 }; 1065 struct si_cs_shader_state cs_shader_state; 1066 /* if current tcs set by user */ 1067 bool is_user_tcs; 1068 1069 /* shader information */ 1070 uint64_t ps_inputs_read_or_disabled; 1071 struct si_vertex_elements *vertex_elements; 1072 unsigned num_vertex_elements; 1073 unsigned cs_max_waves_per_sh; 1074 bool uses_nontrivial_vs_prolog; 1075 bool force_trivial_vs_prolog; 1076 bool do_update_shaders; 1077 bool compute_shaderbuf_sgprs_dirty; 1078 bool compute_image_sgprs_dirty; 1079 bool vs_uses_base_instance; 1080 bool vs_uses_draw_id; 1081 uint8_t patch_vertices; 1082 1083 /* shader descriptors */ 1084 struct si_descriptors descriptors[SI_NUM_DESCS]; 1085 unsigned descriptors_dirty; 1086 unsigned shader_pointers_dirty; 1087 unsigned shader_needs_decompress_mask; 1088 unsigned shader_has_depth_tex; 1089 struct si_buffer_resources internal_bindings; 1090 struct si_buffer_resources const_and_shader_buffers[SI_NUM_SHADERS]; 1091 struct si_samplers samplers[SI_NUM_SHADERS]; 1092 struct si_images images[SI_NUM_SHADERS]; 1093 bool bo_list_add_all_resident_resources; 1094 bool bo_list_add_all_gfx_resources; 1095 bool bo_list_add_all_compute_resources; 1096 1097 /* other shader resources */ 1098 struct pipe_constant_buffer null_const_buf; /* used for set_constant_buffer(NULL) on GFX7 */ 1099 struct pipe_resource *esgs_ring; 1100 struct pipe_resource *gsvs_ring; 1101 struct pipe_resource *tess_rings; 1102 struct pipe_resource *tess_rings_tmz; 1103 union pipe_color_union *border_color_table; /* in CPU memory, any endian */ 1104 struct si_resource *border_color_buffer; 1105 union pipe_color_union *border_color_map; /* in VRAM (slow access), little endian */ 1106 unsigned border_color_count; 1107 unsigned num_vs_blit_sgprs; 1108 uint32_t vs_blit_sh_data[SI_VS_BLIT_SGPRS_POS_TEXCOORD]; 1109 uint32_t cs_user_data[4]; 1110 1111 /* Vertex buffers. */ 1112 bool vertex_buffers_dirty; 1113 bool vertex_buffer_pointer_dirty; 1114 bool vertex_buffer_user_sgprs_dirty; 1115 struct pipe_vertex_buffer vertex_buffer[SI_NUM_VERTEX_BUFFERS]; 1116 uint16_t vertex_buffer_unaligned; /* bitmask of not dword-aligned buffers */ 1117 uint32_t *vb_descriptors_gpu_list; 1118 struct si_resource *vb_descriptors_buffer; 1119 unsigned vb_descriptors_offset; 1120 unsigned vb_descriptor_user_sgprs[5 * 4]; 1121 1122 /* MSAA config state. */ 1123 int ps_iter_samples; 1124 bool ps_uses_fbfetch; 1125 bool smoothing_enabled; 1126 1127 /* point smoothing state.*/ 1128 bool point_smoothing_enabled; 1129 1130 /* DB render state. */ 1131 unsigned ps_db_shader_control; 1132 unsigned dbcb_copy_sample; 1133 bool dbcb_depth_copy_enabled : 1; 1134 bool dbcb_stencil_copy_enabled : 1; 1135 bool db_flush_depth_inplace : 1; 1136 bool db_flush_stencil_inplace : 1; 1137 bool db_depth_clear : 1; 1138 bool db_depth_disable_expclear : 1; 1139 bool db_stencil_clear : 1; 1140 bool db_stencil_disable_expclear : 1; 1141 bool occlusion_queries_disabled : 1; 1142 bool generate_mipmap_for_depth : 1; 1143 bool allow_flat_shading : 1; 1144 1145 /* Emitted draw state. */ 1146 bool ngg : 1; 1147 bool disable_instance_packing : 1; 1148 uint16_t ngg_culling; 1149 unsigned last_index_size; 1150 int last_base_vertex; 1151 unsigned last_start_instance; 1152 unsigned last_instance_count; 1153 unsigned last_drawid; 1154 unsigned last_sh_base_reg; 1155 int last_primitive_restart_en; 1156 unsigned last_restart_index; 1157 unsigned last_prim; 1158 unsigned last_multi_vgt_param; 1159 unsigned last_gs_out_prim; 1160 unsigned current_vs_state; /* all VS bits including LS bits */ 1161 unsigned current_gs_state; /* only GS and NGG bits */ 1162 unsigned last_vs_state; 1163 unsigned last_gs_state; 1164 enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */ 1165 1166 struct si_small_prim_cull_info last_small_prim_cull_info; 1167 struct si_resource *small_prim_cull_info_buf; 1168 uint64_t small_prim_cull_info_address; 1169 1170 /* Scratch buffer */ 1171 struct si_resource *scratch_buffer; 1172 unsigned spi_tmpring_size; 1173 unsigned max_seen_scratch_bytes_per_wave; 1174 unsigned max_seen_compute_scratch_bytes_per_wave; 1175 1176 struct si_resource *compute_scratch_buffer; 1177 1178 /* Emitted derived tessellation state. */ 1179 /* Local shader (VS), or HS if LS-HS are merged. */ 1180 struct si_shader *last_ls; 1181 struct si_shader_selector *last_tcs; 1182 unsigned last_num_tcs_input_cp; 1183 unsigned last_tes_sh_base; 1184 bool last_tess_uses_primid; 1185 unsigned last_num_patches; 1186 unsigned last_ls_hs_config; 1187 1188 /* Debug state. */ 1189 bool is_debug; 1190 struct si_saved_cs *current_saved_cs; 1191 uint64_t dmesg_timestamp; 1192 unsigned apitrace_call_number; 1193 1194 /* Other state */ 1195 bool need_check_render_feedback; 1196 bool decompression_enabled; 1197 bool dpbb_force_off; 1198 bool dpbb_force_off_profile_vs; 1199 bool dpbb_force_off_profile_ps; 1200 bool vs_writes_viewport_index; 1201 bool vs_disables_clipping_viewport; 1202 1203 /* Precomputed IA_MULTI_VGT_PARAM */ 1204 union si_vgt_param_key ia_multi_vgt_param_key; 1205 unsigned ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES]; 1206 1207 /* Bindless descriptors. */ 1208 struct si_descriptors bindless_descriptors; 1209 struct util_idalloc bindless_used_slots; 1210 unsigned num_bindless_descriptors; 1211 bool bindless_descriptors_dirty; 1212 bool graphics_bindless_pointer_dirty; 1213 bool compute_bindless_pointer_dirty; 1214 bool gs_attribute_ring_pointer_dirty; 1215 1216 /* Allocated bindless handles */ 1217 struct hash_table *tex_handles; 1218 struct hash_table *img_handles; 1219 1220 /* Resident bindless handles */ 1221 struct util_dynarray resident_tex_handles; 1222 struct util_dynarray resident_img_handles; 1223 1224 /* Resident bindless handles which need decompression */ 1225 struct util_dynarray resident_tex_needs_color_decompress; 1226 struct util_dynarray resident_img_needs_color_decompress; 1227 struct util_dynarray resident_tex_needs_depth_decompress; 1228 1229 /* Bindless state */ 1230 bool uses_bindless_samplers; 1231 bool uses_bindless_images; 1232 1233 /* MSAA sample locations. 1234 * The first index is the sample index. 1235 * The second index is the coordinate: X, Y. */ 1236 struct { 1237 float x1[1][2]; 1238 float x2[2][2]; 1239 float x4[4][2]; 1240 float x8[8][2]; 1241 float x16[16][2]; 1242 } sample_positions; 1243 struct pipe_resource *sample_pos_buffer; 1244 1245 /* Misc stats. */ 1246 unsigned num_draw_calls; 1247 unsigned num_decompress_calls; 1248 unsigned num_prim_restart_calls; 1249 unsigned num_compute_calls; 1250 unsigned num_cp_dma_calls; 1251 unsigned num_vs_flushes; 1252 unsigned num_ps_flushes; 1253 unsigned num_cs_flushes; 1254 unsigned num_cb_cache_flushes; 1255 unsigned num_db_cache_flushes; 1256 unsigned num_L2_invalidates; 1257 unsigned num_L2_writebacks; 1258 unsigned num_resident_handles; 1259 uint64_t num_alloc_tex_transfer_bytes; 1260 unsigned last_tex_ps_draw_ratio; /* for query */ 1261 unsigned context_roll; 1262 1263 /* Queries. */ 1264 /* Maintain the list of active queries for pausing between IBs. */ 1265 int num_occlusion_queries; 1266 int num_perfect_occlusion_queries; 1267 int num_pipeline_stat_queries; 1268 int num_pipeline_stat_emulated_queries; 1269 struct list_head active_queries; 1270 unsigned num_cs_dw_queries_suspend; 1271 /* Shared buffer for pipeline stats queries implemented with an atomic op */ 1272 struct si_resource *pipeline_stats_query_buf; 1273 1274 /* Render condition. */ 1275 struct pipe_query *render_cond; 1276 unsigned render_cond_mode; 1277 bool render_cond_invert; 1278 bool render_cond_enabled; /* for u_blitter */ 1279 1280 /* Shader-based queries. */ 1281 struct list_head shader_query_buffers; 1282 unsigned num_active_shader_queries; 1283 1284 bool force_cb_shader_coherent; 1285 1286 struct si_tracked_regs tracked_regs; 1287 1288 /* Resources that need to be flushed, but will not get an explicit 1289 * flush_resource from the frontend and that will need to get flushed during 1290 * a context flush. 1291 */ 1292 struct hash_table *dirty_implicit_resources; 1293 1294 pipe_draw_vbo_func draw_vbo[2][2][2]; 1295 pipe_draw_vertex_state_func draw_vertex_state[2][2][2]; 1296 /* When b.draw_vbo is a wrapper, real_draw_vbo is the real draw_vbo function */ 1297 pipe_draw_vbo_func real_draw_vbo; 1298 pipe_draw_vertex_state_func real_draw_vertex_state; 1299 void (*emit_spi_map[33])(struct si_context *sctx); 1300 1301 /* SQTT */ 1302 struct ac_thread_trace_data *thread_trace; 1303 struct ac_spm_trace_data spm_trace; 1304 struct pipe_fence_handle *last_sqtt_fence; 1305 enum rgp_sqtt_marker_event_type sqtt_next_event; 1306 bool thread_trace_enabled; 1307 1308 unsigned context_flags; 1309 1310 /* Shaders. */ 1311 /* TODO: move other shaders here too */ 1312 /* Only used for DCC MSAA clears with 4-8 fragments and 4-16 samples. */ 1313 void *cs_clear_dcc_msaa[32][5][2][3][2]; /* [swizzle_mode][log2(bpe)][fragments == 8][log2(samples)-2][is_array] */ 1314}; 1315 1316/* si_blit.c */ 1317enum si_blitter_op /* bitmask */ 1318{ 1319 SI_SAVE_TEXTURES = 1, 1320 SI_SAVE_FRAMEBUFFER = 2, 1321 SI_SAVE_FRAGMENT_STATE = 4, 1322 SI_DISABLE_RENDER_COND = 8, 1323}; 1324 1325void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op); 1326void si_blitter_end(struct si_context *sctx); 1327void si_init_blit_functions(struct si_context *sctx); 1328void si_decompress_textures(struct si_context *sctx, unsigned shader_mask); 1329void si_decompress_subresource(struct pipe_context *ctx, struct pipe_resource *tex, unsigned planes, 1330 unsigned level, unsigned first_layer, unsigned last_layer, 1331 bool need_fmask_expand); 1332void si_resource_copy_region(struct pipe_context *ctx, struct pipe_resource *dst, 1333 unsigned dst_level, unsigned dstx, unsigned dsty, unsigned dstz, 1334 struct pipe_resource *src, unsigned src_level, 1335 const struct pipe_box *src_box); 1336void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex); 1337void si_flush_implicit_resources(struct si_context *sctx); 1338bool si_msaa_resolve_blit_via_CB(struct pipe_context *ctx, const struct pipe_blit_info *info); 1339void si_gfx_blit(struct pipe_context *ctx, const struct pipe_blit_info *info); 1340 1341/* si_nir_optim.c */ 1342bool si_nir_is_output_const_if_tex_is_const(nir_shader *shader, float *in, float *out, int *texunit); 1343 1344/* si_buffer.c */ 1345bool si_cs_is_buffer_referenced(struct si_context *sctx, struct pb_buffer *buf, 1346 unsigned usage); 1347void *si_buffer_map(struct si_context *sctx, struct si_resource *resource, 1348 unsigned usage); 1349void si_init_resource_fields(struct si_screen *sscreen, struct si_resource *res, uint64_t size, 1350 unsigned alignment); 1351bool si_alloc_resource(struct si_screen *sscreen, struct si_resource *res); 1352struct pipe_resource *pipe_aligned_buffer_create(struct pipe_screen *screen, unsigned flags, 1353 unsigned usage, unsigned size, unsigned alignment); 1354struct si_resource *si_aligned_buffer_create(struct pipe_screen *screen, unsigned flags, 1355 unsigned usage, unsigned size, unsigned alignment); 1356struct pipe_resource *si_buffer_from_winsys_buffer(struct pipe_screen *screen, 1357 const struct pipe_resource *templ, 1358 struct pb_buffer *imported_buf, 1359 uint64_t offset); 1360void si_replace_buffer_storage(struct pipe_context *ctx, struct pipe_resource *dst, 1361 struct pipe_resource *src, unsigned num_rebinds, 1362 uint32_t rebind_mask, uint32_t delete_buffer_id); 1363void si_init_screen_buffer_functions(struct si_screen *sscreen); 1364void si_init_buffer_functions(struct si_context *sctx); 1365 1366/* si_clear.c */ 1367#define SI_CLEAR_TYPE_CMASK (1 << 0) 1368#define SI_CLEAR_TYPE_DCC (1 << 1) 1369#define SI_CLEAR_TYPE_HTILE (1 << 2) 1370 1371struct si_clear_info { 1372 struct pipe_resource *resource; 1373 uint64_t offset; 1374 uint32_t size; 1375 uint32_t clear_value; 1376 uint32_t writemask; 1377 bool is_dcc_msaa; /* Clear it as a DCC MSAA image. */ 1378}; 1379 1380enum pipe_format si_simplify_cb_format(enum pipe_format format); 1381bool vi_alpha_is_on_msb(struct si_screen *sscreen, enum pipe_format format); 1382bool vi_dcc_get_clear_info(struct si_context *sctx, struct si_texture *tex, unsigned level, 1383 unsigned clear_value, struct si_clear_info *out); 1384void si_init_buffer_clear(struct si_clear_info *info, 1385 struct pipe_resource *resource, uint64_t offset, 1386 uint32_t size, uint32_t clear_value); 1387void si_execute_clears(struct si_context *sctx, struct si_clear_info *info, 1388 unsigned num_clears, unsigned types); 1389void si_init_clear_functions(struct si_context *sctx); 1390 1391/* si_compute_blit.c */ 1392#define SI_OP_SYNC_CS_BEFORE (1 << 0) 1393#define SI_OP_SYNC_PS_BEFORE (1 << 1) 1394#define SI_OP_SYNC_CPDMA_BEFORE (1 << 2) /* only affects CP DMA calls */ 1395#define SI_OP_SYNC_BEFORE (SI_OP_SYNC_CS_BEFORE | SI_OP_SYNC_PS_BEFORE | SI_OP_SYNC_CPDMA_BEFORE) 1396#define SI_OP_SYNC_AFTER (1 << 3) 1397#define SI_OP_SYNC_BEFORE_AFTER (SI_OP_SYNC_BEFORE | SI_OP_SYNC_AFTER) 1398#define SI_OP_SKIP_CACHE_INV_BEFORE (1 << 4) /* don't invalidate caches */ 1399#define SI_OP_CS_IMAGE (1 << 5) 1400#define SI_OP_CS_RENDER_COND_ENABLE (1 << 6) 1401#define SI_OP_CPDMA_SKIP_CHECK_CS_SPACE (1 << 7) /* don't call need_cs_space */ 1402#define SI_OP_SYNC_GE_BEFORE (1 << 8) /* only sync VS, TCS, TES, GS */ 1403 1404unsigned si_get_flush_flags(struct si_context *sctx, enum si_coherency coher, 1405 enum si_cache_policy cache_policy); 1406void si_launch_grid_internal_ssbos(struct si_context *sctx, struct pipe_grid_info *info, 1407 void *shader, unsigned flags, enum si_coherency coher, 1408 unsigned num_buffers, const struct pipe_shader_buffer *buffers, 1409 unsigned writeable_bitmask); 1410enum si_clear_method { 1411 SI_CP_DMA_CLEAR_METHOD, 1412 SI_COMPUTE_CLEAR_METHOD, 1413 SI_AUTO_SELECT_CLEAR_METHOD 1414}; 1415void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst, 1416 uint64_t offset, uint64_t size, uint32_t *clear_value, 1417 uint32_t clear_value_size, unsigned flags, 1418 enum si_coherency coher, enum si_clear_method method); 1419void si_compute_clear_buffer_rmw(struct si_context *sctx, struct pipe_resource *dst, 1420 unsigned dst_offset, unsigned size, 1421 uint32_t clear_value, uint32_t writebitmask, 1422 unsigned flags, enum si_coherency coher); 1423void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst, uint64_t offset, 1424 uint64_t size, unsigned value, unsigned flags); 1425void si_copy_buffer(struct si_context *sctx, struct pipe_resource *dst, struct pipe_resource *src, 1426 uint64_t dst_offset, uint64_t src_offset, unsigned size, unsigned flags); 1427bool si_compute_copy_image(struct si_context *sctx, struct pipe_resource *dst, unsigned dst_level, 1428 struct pipe_resource *src, unsigned src_level, unsigned dstx, 1429 unsigned dsty, unsigned dstz, const struct pipe_box *src_box, 1430 unsigned flags); 1431void si_compute_clear_render_target(struct pipe_context *ctx, struct pipe_surface *dstsurf, 1432 const union pipe_color_union *color, unsigned dstx, 1433 unsigned dsty, unsigned width, unsigned height, 1434 bool render_condition_enabled); 1435void si_retile_dcc(struct si_context *sctx, struct si_texture *tex); 1436void gfx9_clear_dcc_msaa(struct si_context *sctx, struct pipe_resource *res, uint32_t clear_value, 1437 unsigned flags, enum si_coherency coher); 1438void si_compute_expand_fmask(struct pipe_context *ctx, struct pipe_resource *tex); 1439void si_init_compute_blit_functions(struct si_context *sctx); 1440 1441/* si_cp_dma.c */ 1442void si_cp_dma_wait_for_idle(struct si_context *sctx, struct radeon_cmdbuf *cs); 1443void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs, 1444 struct pipe_resource *dst, uint64_t offset, uint64_t size, 1445 unsigned value, unsigned user_flags, enum si_coherency coher, 1446 enum si_cache_policy cache_policy); 1447void si_cp_dma_copy_buffer(struct si_context *sctx, struct pipe_resource *dst, 1448 struct pipe_resource *src, uint64_t dst_offset, uint64_t src_offset, 1449 unsigned size, unsigned user_flags, enum si_coherency coher, 1450 enum si_cache_policy cache_policy); 1451void si_test_gds(struct si_context *sctx); 1452void si_cp_write_data(struct si_context *sctx, struct si_resource *buf, unsigned offset, 1453 unsigned size, unsigned dst_sel, unsigned engine, const void *data); 1454void si_cp_copy_data(struct si_context *sctx, struct radeon_cmdbuf *cs, unsigned dst_sel, 1455 struct si_resource *dst, unsigned dst_offset, unsigned src_sel, 1456 struct si_resource *src, unsigned src_offset); 1457 1458/* si_cp_reg_shadowing.c */ 1459void si_init_cp_reg_shadowing(struct si_context *sctx); 1460 1461/* si_debug.c */ 1462void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, struct radeon_saved_cs *saved, 1463 bool get_buffer_list); 1464void si_clear_saved_cs(struct radeon_saved_cs *saved); 1465void si_destroy_saved_cs(struct si_saved_cs *scs); 1466void si_auto_log_cs(void *data, struct u_log_context *log); 1467void si_log_hw_flush(struct si_context *sctx); 1468void si_log_draw_state(struct si_context *sctx, struct u_log_context *log); 1469void si_log_compute_state(struct si_context *sctx, struct u_log_context *log); 1470void si_init_debug_functions(struct si_context *sctx); 1471void si_check_vm_faults(struct si_context *sctx, struct radeon_saved_cs *saved, 1472 enum amd_ip_type ring); 1473bool si_replace_shader(unsigned num, struct si_shader_binary *binary); 1474void si_print_current_ib(struct si_context *sctx, FILE *f); 1475 1476/* si_fence.c */ 1477void si_cp_release_mem(struct si_context *ctx, struct radeon_cmdbuf *cs, unsigned event, 1478 unsigned event_flags, unsigned dst_sel, unsigned int_sel, unsigned data_sel, 1479 struct si_resource *buf, uint64_t va, uint32_t new_fence, 1480 unsigned query_type); 1481unsigned si_cp_write_fence_dwords(struct si_screen *screen); 1482void si_cp_wait_mem(struct si_context *ctx, struct radeon_cmdbuf *cs, uint64_t va, uint32_t ref, 1483 uint32_t mask, unsigned flags); 1484void si_init_fence_functions(struct si_context *ctx); 1485void si_init_screen_fence_functions(struct si_screen *screen); 1486struct pipe_fence_handle *si_create_fence(struct pipe_context *ctx, 1487 struct tc_unflushed_batch_token *tc_token); 1488 1489/* si_get.c */ 1490void si_init_screen_get_functions(struct si_screen *sscreen); 1491 1492bool si_sdma_copy_image(struct si_context *ctx, struct si_texture *dst, struct si_texture *src); 1493 1494/* si_gfx_cs.c */ 1495void si_flush_gfx_cs(struct si_context *ctx, unsigned flags, struct pipe_fence_handle **fence); 1496void si_allocate_gds(struct si_context *ctx); 1497void si_set_tracked_regs_to_clear_state(struct si_context *ctx); 1498void si_begin_new_gfx_cs(struct si_context *ctx, bool first_cs); 1499void si_trace_emit(struct si_context *sctx); 1500void si_emit_surface_sync(struct si_context *sctx, struct radeon_cmdbuf *cs, 1501 unsigned cp_coher_cntl); 1502void gfx10_emit_cache_flush(struct si_context *sctx, struct radeon_cmdbuf *cs); 1503void si_emit_cache_flush(struct si_context *sctx, struct radeon_cmdbuf *cs); 1504/* Replace the sctx->b.draw_vbo function with a wrapper. This can be use to implement 1505 * optimizations without affecting the normal draw_vbo functions perf. 1506 */ 1507void si_install_draw_wrapper(struct si_context *sctx, pipe_draw_vbo_func wrapper, 1508 pipe_draw_vertex_state_func vstate_wrapper); 1509 1510/* si_gpu_load.c */ 1511void si_gpu_load_kill_thread(struct si_screen *sscreen); 1512uint64_t si_begin_counter(struct si_screen *sscreen, unsigned type); 1513unsigned si_end_counter(struct si_screen *sscreen, unsigned type, uint64_t begin); 1514 1515/* si_compute.c */ 1516void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf *cs); 1517void si_init_compute_functions(struct si_context *sctx); 1518 1519/* si_pipe.c */ 1520bool si_init_compiler(struct si_screen *sscreen, struct ac_llvm_compiler *compiler); 1521void si_init_aux_async_compute_ctx(struct si_screen *sscreen); 1522struct si_context* si_get_aux_context(struct si_screen *sscreen); 1523void si_put_aux_context_flush(struct si_screen *sscreen); 1524 1525/* si_perfcounters.c */ 1526void si_init_perfcounters(struct si_screen *screen); 1527void si_destroy_perfcounters(struct si_screen *screen); 1528void si_inhibit_clockgating(struct si_context *sctx, struct radeon_cmdbuf *cs, bool inhibit); 1529void si_pc_emit_shaders(struct radeon_cmdbuf *cs, unsigned shaders); 1530void si_pc_emit_spm_start(struct radeon_cmdbuf *cs); 1531void si_pc_emit_spm_stop(struct radeon_cmdbuf *cs, bool never_stop_sq_perf_counters, 1532 bool never_send_perfcounter_stop); 1533void si_pc_emit_spm_reset(struct radeon_cmdbuf *cs); 1534void si_emit_spm_setup(struct si_context *sctx, struct radeon_cmdbuf *cs); 1535bool si_spm_init(struct si_context *sctx); 1536void si_spm_finish(struct si_context *sctx); 1537 1538/* si_query.c */ 1539void si_init_screen_query_functions(struct si_screen *sscreen); 1540void si_init_query_functions(struct si_context *sctx); 1541void si_suspend_queries(struct si_context *sctx); 1542void si_resume_queries(struct si_context *sctx); 1543 1544/* si_shaderlib_nir.c */ 1545void *si_create_copy_image_cs(struct si_context *sctx, bool src_is_1d_array, bool dst_is_1d_array); 1546void *si_create_dcc_retile_cs(struct si_context *sctx, struct radeon_surf *surf); 1547void *gfx9_create_clear_dcc_msaa_cs(struct si_context *sctx, struct si_texture *tex); 1548void *si_create_passthrough_tcs(struct si_context *sctx); 1549 1550/* si_shaderlib_tgsi.c */ 1551void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type, 1552 unsigned num_layers); 1553void *si_create_dma_compute_shader(struct pipe_context *ctx, unsigned num_dwords_per_thread, 1554 bool dst_stream_cache_policy, bool is_copy); 1555void *si_create_clear_buffer_rmw_cs(struct si_context *sctx); 1556void *si_clear_render_target_shader(struct pipe_context *ctx); 1557void *si_clear_render_target_shader_1d_array(struct pipe_context *ctx); 1558void *si_clear_12bytes_buffer_shader(struct pipe_context *ctx); 1559void *si_create_fmask_expand_cs(struct pipe_context *ctx, unsigned num_samples, bool is_array); 1560void *si_create_query_result_cs(struct si_context *sctx); 1561void *gfx10_create_sh_query_result_cs(struct si_context *sctx); 1562 1563/* gfx10_query.c */ 1564void gfx10_init_query(struct si_context *sctx); 1565void gfx10_destroy_query(struct si_context *sctx); 1566 1567/* si_test_image_copy_region.c */ 1568void si_test_image_copy_region(struct si_screen *sscreen); 1569void si_test_blit(struct si_screen *sscreen, unsigned test_flags); 1570 1571/* si_test_clearbuffer.c */ 1572void si_test_dma_perf(struct si_screen *sscreen); 1573 1574/* si_uvd.c */ 1575struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context, 1576 const struct pipe_video_codec *templ); 1577 1578struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe, 1579 const struct pipe_video_buffer *tmpl); 1580struct pipe_video_buffer *si_video_buffer_create_with_modifiers(struct pipe_context *pipe, 1581 const struct pipe_video_buffer *tmpl, 1582 const uint64_t *modifiers, 1583 unsigned int modifiers_count); 1584 1585/* si_state_viewport.c */ 1586void si_update_vs_viewport_state(struct si_context *ctx); 1587void si_init_viewport_functions(struct si_context *ctx); 1588 1589/* si_texture.c */ 1590void si_eliminate_fast_color_clear(struct si_context *sctx, struct si_texture *tex, 1591 bool *ctx_flushed); 1592void si_texture_discard_cmask(struct si_screen *sscreen, struct si_texture *tex); 1593bool si_init_flushed_depth_texture(struct pipe_context *ctx, struct pipe_resource *texture); 1594void si_print_texture_info(struct si_screen *sscreen, struct si_texture *tex, 1595 struct u_log_context *log); 1596struct pipe_resource *si_texture_create(struct pipe_screen *screen, 1597 const struct pipe_resource *templ); 1598bool si_texture_commit(struct si_context *ctx, struct si_resource *res, unsigned level, 1599 struct pipe_box *box, bool commit); 1600bool vi_dcc_formats_compatible(struct si_screen *sscreen, enum pipe_format format1, 1601 enum pipe_format format2); 1602bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex, unsigned level, 1603 enum pipe_format view_format); 1604void vi_disable_dcc_if_incompatible_format(struct si_context *sctx, struct pipe_resource *tex, 1605 unsigned level, enum pipe_format view_format); 1606unsigned si_translate_colorswap(enum amd_gfx_level gfx_level, enum pipe_format format, 1607 bool do_endian_swap); 1608bool si_texture_disable_dcc(struct si_context *sctx, struct si_texture *tex); 1609void si_init_screen_texture_functions(struct si_screen *sscreen); 1610void si_init_context_texture_functions(struct si_context *sctx); 1611 1612/* si_sqtt.c */ 1613void si_sqtt_write_event_marker(struct si_context* sctx, struct radeon_cmdbuf *rcs, 1614 enum rgp_sqtt_marker_event_type api_type, 1615 uint32_t vertex_offset_user_data, 1616 uint32_t instance_offset_user_data, 1617 uint32_t draw_index_user_data); 1618bool si_sqtt_register_pipeline(struct si_context* sctx, uint64_t pipeline_hash, uint64_t base_address, bool is_compute); 1619bool si_sqtt_pipeline_is_registered(struct ac_thread_trace_data *thread_trace_data, 1620 uint64_t pipeline_hash); 1621void si_sqtt_describe_pipeline_bind(struct si_context* sctx, uint64_t pipeline_hash, int bind_point); 1622void 1623si_write_event_with_dims_marker(struct si_context* sctx, struct radeon_cmdbuf *rcs, 1624 enum rgp_sqtt_marker_event_type api_type, 1625 uint32_t x, uint32_t y, uint32_t z); 1626void 1627si_write_user_event(struct si_context* sctx, struct radeon_cmdbuf *rcs, 1628 enum rgp_sqtt_marker_user_event_type type, 1629 const char *str, int len); 1630void 1631si_sqtt_describe_barrier_start(struct si_context* sctx, struct radeon_cmdbuf *rcs); 1632void 1633si_sqtt_describe_barrier_end(struct si_context* sctx, struct radeon_cmdbuf *rcs, unsigned flags); 1634bool si_init_thread_trace(struct si_context *sctx); 1635void si_destroy_thread_trace(struct si_context *sctx); 1636void si_handle_thread_trace(struct si_context *sctx, struct radeon_cmdbuf *rcs); 1637 1638/* 1639 * common helpers 1640 */ 1641 1642static inline struct si_resource *si_resource(struct pipe_resource *r) 1643{ 1644 return (struct si_resource *)r; 1645} 1646 1647static inline void si_resource_reference(struct si_resource **ptr, struct si_resource *res) 1648{ 1649 pipe_resource_reference((struct pipe_resource **)ptr, (struct pipe_resource *)res); 1650} 1651 1652static inline void si_texture_reference(struct si_texture **ptr, struct si_texture *res) 1653{ 1654 pipe_resource_reference((struct pipe_resource **)ptr, &res->buffer.b.b); 1655} 1656 1657static inline void 1658si_shader_selector_reference(struct si_context *sctx, /* sctx can optionally be NULL */ 1659 struct si_shader_selector **dst, struct si_shader_selector *src) 1660{ 1661 if (*dst == src) 1662 return; 1663 1664 struct si_screen *sscreen = src ? src->screen : (*dst)->screen; 1665 util_shader_reference(&sctx->b, &sscreen->live_shader_cache, (void **)dst, src); 1666} 1667 1668static inline bool vi_dcc_enabled(struct si_texture *tex, unsigned level) 1669{ 1670 return !tex->is_depth && tex->surface.meta_offset && level < tex->surface.num_meta_levels; 1671} 1672 1673static inline unsigned si_tile_mode_index(struct si_texture *tex, unsigned level, bool stencil) 1674{ 1675 if (stencil) 1676 return tex->surface.u.legacy.zs.stencil_tiling_index[level]; 1677 else 1678 return tex->surface.u.legacy.tiling_index[level]; 1679} 1680 1681static inline unsigned si_get_minimum_num_gfx_cs_dwords(struct si_context *sctx, 1682 unsigned num_draws) 1683{ 1684 /* Don't count the needed CS space exactly and just use an upper bound. 1685 * 1686 * Also reserve space for stopping queries at the end of IB, because 1687 * the number of active queries is unlimited in theory. 1688 */ 1689 return 2048 + sctx->num_cs_dw_queries_suspend + num_draws * 10; 1690} 1691 1692static inline void si_context_add_resource_size(struct si_context *sctx, struct pipe_resource *r) 1693{ 1694 if (r) { 1695 /* Add memory usage for need_gfx_cs_space */ 1696 sctx->memory_usage_kb += si_resource(r)->memory_usage_kb; 1697 } 1698} 1699 1700static inline void si_invalidate_draw_sh_constants(struct si_context *sctx) 1701{ 1702 sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN; 1703 sctx->last_start_instance = SI_START_INSTANCE_UNKNOWN; 1704 sctx->last_drawid = SI_DRAW_ID_UNKNOWN; 1705} 1706 1707static inline void si_invalidate_draw_constants(struct si_context *sctx) 1708{ 1709 si_invalidate_draw_sh_constants(sctx); 1710 sctx->last_instance_count = SI_INSTANCE_COUNT_UNKNOWN; 1711} 1712 1713static inline unsigned si_get_atom_bit(struct si_context *sctx, struct si_atom *atom) 1714{ 1715 return 1 << (atom - sctx->atoms.array); 1716} 1717 1718static inline void si_set_atom_dirty(struct si_context *sctx, struct si_atom *atom, bool dirty) 1719{ 1720 unsigned bit = si_get_atom_bit(sctx, atom); 1721 1722 if (dirty) 1723 sctx->dirty_atoms |= bit; 1724 else 1725 sctx->dirty_atoms &= ~bit; 1726} 1727 1728static inline bool si_is_atom_dirty(struct si_context *sctx, struct si_atom *atom) 1729{ 1730 return (sctx->dirty_atoms & si_get_atom_bit(sctx, atom)) != 0; 1731} 1732 1733static inline void si_mark_atom_dirty(struct si_context *sctx, struct si_atom *atom) 1734{ 1735 si_set_atom_dirty(sctx, atom, true); 1736} 1737 1738/* This should be evaluated at compile time if all parameters except sctx are constants. */ 1739static ALWAYS_INLINE struct si_shader_ctx_state * 1740si_get_vs_inline(struct si_context *sctx, enum si_has_tess has_tess, enum si_has_gs has_gs) 1741{ 1742 if (has_gs) 1743 return &sctx->shader.gs; 1744 if (has_tess) 1745 return &sctx->shader.tes; 1746 1747 return &sctx->shader.vs; 1748} 1749 1750static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx) 1751{ 1752 return si_get_vs_inline(sctx, sctx->shader.tes.cso ? TESS_ON : TESS_OFF, 1753 sctx->shader.gs.cso ? GS_ON : GS_OFF); 1754} 1755 1756static inline bool si_can_dump_shader(struct si_screen *sscreen, gl_shader_stage stage) 1757{ 1758 return sscreen->debug_flags & (1 << stage); 1759} 1760 1761static inline bool si_get_strmout_en(struct si_context *sctx) 1762{ 1763 return sctx->streamout.streamout_enabled || sctx->streamout.prims_gen_query_enabled; 1764} 1765 1766static inline unsigned si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size) 1767{ 1768 unsigned alignment, tcc_cache_line_size; 1769 1770 /* If the upload size is less than the cache line size (e.g. 16, 32), 1771 * the whole thing will fit into a cache line if we align it to its size. 1772 * The idea is that multiple small uploads can share a cache line. 1773 * If the upload size is greater, align it to the cache line size. 1774 */ 1775 alignment = util_next_power_of_two(upload_size); 1776 tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size; 1777 return MIN2(alignment, tcc_cache_line_size); 1778} 1779 1780static inline void si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src) 1781{ 1782 if (pipe_reference(&(*dst)->reference, &src->reference)) 1783 si_destroy_saved_cs(*dst); 1784 1785 *dst = src; 1786} 1787 1788static inline void si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples, 1789 bool shaders_read_metadata, bool dcc_pipe_aligned) 1790{ 1791 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_INV_VCACHE; 1792 sctx->force_cb_shader_coherent = false; 1793 1794 if (sctx->gfx_level >= GFX10) { 1795 if (sctx->screen->info.tcc_rb_non_coherent) 1796 sctx->flags |= SI_CONTEXT_INV_L2; 1797 else if (shaders_read_metadata) 1798 sctx->flags |= SI_CONTEXT_INV_L2_METADATA; 1799 } else if (sctx->gfx_level == GFX9) { 1800 /* Single-sample color is coherent with shaders on GFX9, but 1801 * L2 metadata must be flushed if shaders read metadata. 1802 * (DCC, CMASK). 1803 */ 1804 if (num_samples >= 2 || (shaders_read_metadata && !dcc_pipe_aligned)) 1805 sctx->flags |= SI_CONTEXT_INV_L2; 1806 else if (shaders_read_metadata) 1807 sctx->flags |= SI_CONTEXT_INV_L2_METADATA; 1808 } else { 1809 /* GFX6-GFX8 */ 1810 sctx->flags |= SI_CONTEXT_INV_L2; 1811 } 1812} 1813 1814static inline void si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples, 1815 bool include_stencil, bool shaders_read_metadata) 1816{ 1817 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB | SI_CONTEXT_INV_VCACHE; 1818 1819 if (sctx->gfx_level >= GFX10) { 1820 if (sctx->screen->info.tcc_rb_non_coherent) 1821 sctx->flags |= SI_CONTEXT_INV_L2; 1822 else if (shaders_read_metadata) 1823 sctx->flags |= SI_CONTEXT_INV_L2_METADATA; 1824 } else if (sctx->gfx_level == GFX9) { 1825 /* Single-sample depth (not stencil) is coherent with shaders 1826 * on GFX9, but L2 metadata must be flushed if shaders read 1827 * metadata. 1828 */ 1829 if (num_samples >= 2 || include_stencil) 1830 sctx->flags |= SI_CONTEXT_INV_L2; 1831 else if (shaders_read_metadata) 1832 sctx->flags |= SI_CONTEXT_INV_L2_METADATA; 1833 } else { 1834 /* GFX6-GFX8 */ 1835 sctx->flags |= SI_CONTEXT_INV_L2; 1836 } 1837} 1838 1839static inline bool si_can_sample_zs(struct si_texture *tex, bool stencil_sampler) 1840{ 1841 return (stencil_sampler && tex->can_sample_s) || (!stencil_sampler && tex->can_sample_z); 1842} 1843 1844static inline bool si_htile_enabled(struct si_texture *tex, unsigned level, unsigned zs_mask) 1845{ 1846 if (zs_mask == PIPE_MASK_S && (tex->htile_stencil_disabled || !tex->surface.has_stencil)) 1847 return false; 1848 1849 if (!tex->is_depth || !tex->surface.meta_offset) 1850 return false; 1851 1852 struct si_screen *sscreen = (struct si_screen *)tex->buffer.b.b.screen; 1853 if (sscreen->info.gfx_level >= GFX8) { 1854 return level < tex->surface.num_meta_levels; 1855 } else { 1856 /* GFX6-7 don't have TC-compatible HTILE, which means they have to run 1857 * a decompression pass for every mipmap level before texturing, so compress 1858 * only one level to reduce the number of decompression passes to a minimum. 1859 */ 1860 return level == 0; 1861 } 1862} 1863 1864static inline bool vi_tc_compat_htile_enabled(struct si_texture *tex, unsigned level, 1865 unsigned zs_mask) 1866{ 1867 assert(!tex->tc_compatible_htile || tex->surface.meta_offset); 1868 return tex->tc_compatible_htile && si_htile_enabled(tex, level, zs_mask); 1869} 1870 1871static inline unsigned si_get_ps_iter_samples(struct si_context *sctx) 1872{ 1873 if (sctx->ps_uses_fbfetch) 1874 return sctx->framebuffer.nr_color_samples; 1875 1876 return MIN2(sctx->ps_iter_samples, sctx->framebuffer.nr_color_samples); 1877} 1878 1879static inline unsigned si_get_total_colormask(struct si_context *sctx) 1880{ 1881 if (sctx->queued.named.rasterizer->rasterizer_discard) 1882 return 0; 1883 1884 struct si_shader_selector *ps = sctx->shader.ps.cso; 1885 if (!ps) 1886 return 0; 1887 1888 unsigned colormask = 1889 sctx->framebuffer.colorbuf_enabled_4bit & sctx->queued.named.blend->cb_target_mask; 1890 1891 if (!ps->info.color0_writes_all_cbufs) 1892 colormask &= ps->info.colors_written_4bit; 1893 else if (!ps->info.colors_written_4bit) 1894 colormask = 0; /* color0 writes all cbufs, but it's not written */ 1895 1896 return colormask; 1897} 1898 1899#define UTIL_ALL_PRIM_LINE_MODES \ 1900 ((1 << PIPE_PRIM_LINES) | (1 << PIPE_PRIM_LINE_LOOP) | (1 << PIPE_PRIM_LINE_STRIP) | \ 1901 (1 << PIPE_PRIM_LINES_ADJACENCY) | (1 << PIPE_PRIM_LINE_STRIP_ADJACENCY)) 1902 1903#define UTIL_ALL_PRIM_TRIANGLE_MODES \ 1904 ((1 << PIPE_PRIM_TRIANGLES) | (1 << PIPE_PRIM_TRIANGLE_STRIP) | \ 1905 (1 << PIPE_PRIM_TRIANGLE_FAN) | (1 << PIPE_PRIM_QUADS) | (1 << PIPE_PRIM_QUAD_STRIP) | \ 1906 (1 << PIPE_PRIM_POLYGON) | (1 << PIPE_PRIM_TRIANGLES_ADJACENCY) | \ 1907 (1 << PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY)) 1908 1909static inline bool util_prim_is_lines(unsigned prim) 1910{ 1911 return ((1 << prim) & UTIL_ALL_PRIM_LINE_MODES) != 0; 1912} 1913 1914static inline bool util_prim_is_points_or_lines(unsigned prim) 1915{ 1916 return ((1 << prim) & (UTIL_ALL_PRIM_LINE_MODES | (1 << PIPE_PRIM_POINTS))) != 0; 1917} 1918 1919static inline bool util_rast_prim_is_triangles(unsigned prim) 1920{ 1921 return ((1 << prim) & UTIL_ALL_PRIM_TRIANGLE_MODES) != 0; 1922} 1923 1924static inline bool util_rast_prim_is_lines_or_triangles(unsigned prim) 1925{ 1926 return ((1 << prim) & (UTIL_ALL_PRIM_LINE_MODES | UTIL_ALL_PRIM_TRIANGLE_MODES)) != 0; 1927} 1928 1929/** 1930 * Return true if there is enough memory in VRAM and GTT for the buffers 1931 * added so far. 1932 * 1933 * \param vram VRAM memory size not added to the buffer list yet 1934 * \param gtt GTT memory size not added to the buffer list yet 1935 */ 1936static inline bool radeon_cs_memory_below_limit(struct si_screen *screen, struct radeon_cmdbuf *cs, 1937 uint32_t kb) 1938{ 1939 return kb + cs->used_vram_kb + cs->used_gart_kb < screen->max_memory_usage_kb; 1940} 1941 1942static inline void si_need_gfx_cs_space(struct si_context *ctx, unsigned num_draws) 1943{ 1944 struct radeon_cmdbuf *cs = &ctx->gfx_cs; 1945 1946 /* There are two memory usage counters in the winsys for all buffers 1947 * that have been added (cs_add_buffer) and one counter in the pipe 1948 * driver for those that haven't been added yet. 1949 */ 1950 uint32_t kb = ctx->memory_usage_kb; 1951 ctx->memory_usage_kb = 0; 1952 1953 if (radeon_cs_memory_below_limit(ctx->screen, &ctx->gfx_cs, kb) && 1954 ctx->ws->cs_check_space(cs, si_get_minimum_num_gfx_cs_dwords(ctx, num_draws))) 1955 return; 1956 1957 si_flush_gfx_cs(ctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL); 1958} 1959 1960/** 1961 * Add a buffer to the buffer list for the given command stream (CS). 1962 * 1963 * All buffers used by a CS must be added to the list. This tells the kernel 1964 * driver which buffers are used by GPU commands. Other buffers can 1965 * be swapped out (not accessible) during execution. 1966 * 1967 * The buffer list becomes empty after every context flush and must be 1968 * rebuilt. 1969 */ 1970static inline void radeon_add_to_buffer_list(struct si_context *sctx, struct radeon_cmdbuf *cs, 1971 struct si_resource *bo, unsigned usage) 1972{ 1973 assert(usage); 1974 sctx->ws->cs_add_buffer(cs, bo->buf, usage | RADEON_USAGE_SYNCHRONIZED, 1975 bo->domains); 1976} 1977 1978/** 1979 * Same as above, but also checks memory usage and flushes the context 1980 * accordingly. 1981 * 1982 * When this SHOULD NOT be used: 1983 * 1984 * - if si_context_add_resource_size has been called for the buffer 1985 * followed by *_need_cs_space for checking the memory usage 1986 * 1987 * - when emitting state packets and draw packets (because preceding packets 1988 * can't be re-emitted at that point) 1989 * 1990 * - if shader resource "enabled_mask" is not up-to-date or there is 1991 * a different constraint disallowing a context flush 1992 */ 1993static inline void radeon_add_to_gfx_buffer_list_check_mem(struct si_context *sctx, 1994 struct si_resource *bo, 1995 unsigned usage, 1996 bool check_mem) 1997{ 1998 if (check_mem && 1999 !radeon_cs_memory_below_limit(sctx->screen, &sctx->gfx_cs, sctx->memory_usage_kb + bo->memory_usage_kb)) 2000 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL); 2001 2002 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, bo, usage); 2003} 2004 2005static inline void si_select_draw_vbo(struct si_context *sctx) 2006{ 2007 pipe_draw_vbo_func draw_vbo = sctx->draw_vbo[!!sctx->shader.tes.cso] 2008 [!!sctx->shader.gs.cso] 2009 [sctx->ngg]; 2010 pipe_draw_vertex_state_func draw_vertex_state = 2011 sctx->draw_vertex_state[!!sctx->shader.tes.cso] 2012 [!!sctx->shader.gs.cso] 2013 [sctx->ngg]; 2014 assert(draw_vbo); 2015 assert(draw_vertex_state); 2016 2017 if (unlikely(sctx->real_draw_vbo)) { 2018 assert(sctx->real_draw_vertex_state); 2019 sctx->real_draw_vbo = draw_vbo; 2020 sctx->real_draw_vertex_state = draw_vertex_state; 2021 } else { 2022 assert(!sctx->real_draw_vertex_state); 2023 sctx->b.draw_vbo = draw_vbo; 2024 sctx->b.draw_vertex_state = draw_vertex_state; 2025 } 2026} 2027 2028/* Return the number of samples that the rasterizer uses. */ 2029static inline unsigned si_get_num_coverage_samples(struct si_context *sctx) 2030{ 2031 if (sctx->framebuffer.nr_samples > 1 && 2032 sctx->queued.named.rasterizer->multisample_enable) 2033 return sctx->framebuffer.nr_samples; 2034 2035 /* Note that smoothing_enabled is set by si_update_shaders. */ 2036 if (sctx->smoothing_enabled) 2037 return SI_NUM_SMOOTH_AA_SAMPLES; 2038 2039 return 1; 2040} 2041 2042static unsigned ALWAYS_INLINE 2043si_num_vbos_in_user_sgprs_inline(enum amd_gfx_level gfx_level) 2044{ 2045 /* This decreases CPU overhead if all descriptors are in user SGPRs because we don't 2046 * have to allocate and count references for the upload buffer. 2047 */ 2048 return gfx_level >= GFX9 ? 5 : 1; 2049} 2050 2051static inline unsigned si_num_vbos_in_user_sgprs(struct si_screen *sscreen) 2052{ 2053 return si_num_vbos_in_user_sgprs_inline(sscreen->info.gfx_level); 2054} 2055 2056static inline 2057void si_check_dirty_buffers_textures(struct si_context *sctx) 2058{ 2059 /* Recompute and re-emit the texture resource states if needed. */ 2060 unsigned dirty_tex_counter = p_atomic_read(&sctx->screen->dirty_tex_counter); 2061 if (unlikely(dirty_tex_counter != sctx->last_dirty_tex_counter)) { 2062 sctx->last_dirty_tex_counter = dirty_tex_counter; 2063 sctx->framebuffer.dirty_cbufs |= ((1 << sctx->framebuffer.state.nr_cbufs) - 1); 2064 sctx->framebuffer.dirty_zsbuf = true; 2065 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer); 2066 si_update_all_texture_descriptors(sctx); 2067 } 2068 2069 unsigned dirty_buf_counter = p_atomic_read(&sctx->screen->dirty_buf_counter); 2070 if (unlikely(dirty_buf_counter != sctx->last_dirty_buf_counter)) { 2071 sctx->last_dirty_buf_counter = dirty_buf_counter; 2072 /* Rebind all buffers unconditionally. */ 2073 si_rebind_buffer(sctx, NULL); 2074 } 2075} 2076 2077 2078#define PRINT_ERR(fmt, args...) \ 2079 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args) 2080 2081#ifdef __cplusplus 2082} 2083#endif 2084 2085#endif 2086