1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * Copyright 2015 Advanced Micro Devices, Inc. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * on the rights to use, copy, modify, merge, publish, distribute, sub 10 * license, and/or sell copies of the Software, and to permit persons to whom 11 * the Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 23 * USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26#include "si_compute.h" 27#include "si_pipe.h" 28#include "util/format/u_format.h" 29#include "util/u_log.h" 30#include "util/u_surface.h" 31 32enum 33{ 34 SI_COPY = 35 SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES | SI_SAVE_FRAGMENT_STATE | SI_DISABLE_RENDER_COND, 36 37 SI_BLIT = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES | SI_SAVE_FRAGMENT_STATE, 38 39 SI_DECOMPRESS = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE | SI_DISABLE_RENDER_COND, 40 41 SI_COLOR_RESOLVE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE 42}; 43 44void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op) 45{ 46 util_blitter_save_vertex_shader(sctx->blitter, sctx->shader.vs.cso); 47 util_blitter_save_tessctrl_shader(sctx->blitter, sctx->shader.tcs.cso); 48 util_blitter_save_tesseval_shader(sctx->blitter, sctx->shader.tes.cso); 49 util_blitter_save_geometry_shader(sctx->blitter, sctx->shader.gs.cso); 50 util_blitter_save_so_targets(sctx->blitter, sctx->streamout.num_targets, 51 (struct pipe_stream_output_target **)sctx->streamout.targets); 52 util_blitter_save_rasterizer(sctx->blitter, sctx->queued.named.rasterizer); 53 54 if (op & SI_SAVE_FRAGMENT_STATE) { 55 struct pipe_constant_buffer fs_cb = {}; 56 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_FRAGMENT, 0, &fs_cb); 57 util_blitter_save_fragment_constant_buffer_slot(sctx->blitter, &fs_cb); 58 pipe_resource_reference(&fs_cb.buffer, NULL); 59 util_blitter_save_blend(sctx->blitter, sctx->queued.named.blend); 60 util_blitter_save_depth_stencil_alpha(sctx->blitter, sctx->queued.named.dsa); 61 util_blitter_save_stencil_ref(sctx->blitter, &sctx->stencil_ref.state); 62 util_blitter_save_fragment_shader(sctx->blitter, sctx->shader.ps.cso); 63 util_blitter_save_sample_mask(sctx->blitter, sctx->sample_mask, sctx->ps_iter_samples); 64 util_blitter_save_scissor(sctx->blitter, &sctx->scissors[0]); 65 util_blitter_save_window_rectangles(sctx->blitter, sctx->window_rectangles_include, 66 sctx->num_window_rectangles, sctx->window_rectangles); 67 } 68 69 if (op & SI_SAVE_FRAMEBUFFER) 70 util_blitter_save_framebuffer(sctx->blitter, &sctx->framebuffer.state); 71 72 if (op & SI_SAVE_TEXTURES) { 73 util_blitter_save_fragment_sampler_states( 74 sctx->blitter, 2, (void **)sctx->samplers[PIPE_SHADER_FRAGMENT].sampler_states); 75 76 util_blitter_save_fragment_sampler_views(sctx->blitter, 2, 77 sctx->samplers[PIPE_SHADER_FRAGMENT].views); 78 } 79 80 if (op & SI_DISABLE_RENDER_COND) 81 sctx->render_cond_enabled = false; 82 83 if (sctx->screen->dpbb_allowed) { 84 sctx->dpbb_force_off = true; 85 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state); 86 } 87 88 sctx->blitter_running = true; 89} 90 91void si_blitter_end(struct si_context *sctx) 92{ 93 sctx->blitter_running = false; 94 95 if (sctx->screen->dpbb_allowed) { 96 sctx->dpbb_force_off = false; 97 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state); 98 } 99 100 sctx->render_cond_enabled = sctx->render_cond; 101 102 /* Restore shader pointers because the VS blit shader changed all 103 * non-global VS user SGPRs. */ 104 sctx->shader_pointers_dirty |= SI_DESCS_SHADER_MASK(VERTEX); 105 106 if (sctx->gfx_level >= GFX11) 107 sctx->gs_attribute_ring_pointer_dirty = true; 108 109 /* Reset SI_SGPR_SMALL_PRIM_CULL_INFO: */ 110 if (sctx->screen->use_ngg_culling) 111 si_mark_atom_dirty(sctx, &sctx->atoms.s.ngg_cull_state); 112 113 unsigned num_vbos_in_user_sgprs = si_num_vbos_in_user_sgprs(sctx->screen); 114 sctx->vertex_buffer_pointer_dirty = sctx->vb_descriptors_buffer != NULL && 115 sctx->num_vertex_elements > 116 num_vbos_in_user_sgprs; 117 sctx->vertex_buffer_user_sgprs_dirty = sctx->num_vertex_elements > 0 && 118 num_vbos_in_user_sgprs; 119 si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers); 120} 121 122static unsigned u_max_sample(struct pipe_resource *r) 123{ 124 return r->nr_samples ? r->nr_samples - 1 : 0; 125} 126 127static unsigned si_blit_dbcb_copy(struct si_context *sctx, struct si_texture *src, 128 struct si_texture *dst, unsigned planes, unsigned level_mask, 129 unsigned first_layer, unsigned last_layer, unsigned first_sample, 130 unsigned last_sample) 131{ 132 struct pipe_surface surf_tmpl = {{0}}; 133 unsigned layer, sample, checked_last_layer, max_layer; 134 unsigned fully_copied_levels = 0; 135 136 if (planes & PIPE_MASK_Z) 137 sctx->dbcb_depth_copy_enabled = true; 138 if (planes & PIPE_MASK_S) 139 sctx->dbcb_stencil_copy_enabled = true; 140 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state); 141 142 assert(sctx->dbcb_depth_copy_enabled || sctx->dbcb_stencil_copy_enabled); 143 144 sctx->decompression_enabled = true; 145 146 while (level_mask) { 147 unsigned level = u_bit_scan(&level_mask); 148 149 /* The smaller the mipmap level, the less layers there are 150 * as far as 3D textures are concerned. */ 151 max_layer = util_max_layer(&src->buffer.b.b, level); 152 checked_last_layer = MIN2(last_layer, max_layer); 153 154 surf_tmpl.u.tex.level = level; 155 156 for (layer = first_layer; layer <= checked_last_layer; layer++) { 157 struct pipe_surface *zsurf, *cbsurf; 158 159 surf_tmpl.format = src->buffer.b.b.format; 160 surf_tmpl.u.tex.first_layer = layer; 161 surf_tmpl.u.tex.last_layer = layer; 162 163 zsurf = sctx->b.create_surface(&sctx->b, &src->buffer.b.b, &surf_tmpl); 164 165 surf_tmpl.format = dst->buffer.b.b.format; 166 cbsurf = sctx->b.create_surface(&sctx->b, &dst->buffer.b.b, &surf_tmpl); 167 168 for (sample = first_sample; sample <= last_sample; sample++) { 169 if (sample != sctx->dbcb_copy_sample) { 170 sctx->dbcb_copy_sample = sample; 171 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state); 172 } 173 174 si_blitter_begin(sctx, SI_DECOMPRESS); 175 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, cbsurf, 1 << sample, 176 sctx->custom_dsa_flush, 1.0f); 177 si_blitter_end(sctx); 178 } 179 180 pipe_surface_reference(&zsurf, NULL); 181 pipe_surface_reference(&cbsurf, NULL); 182 } 183 184 if (first_layer == 0 && last_layer >= max_layer && first_sample == 0 && 185 last_sample >= u_max_sample(&src->buffer.b.b)) 186 fully_copied_levels |= 1u << level; 187 } 188 189 sctx->decompression_enabled = false; 190 sctx->dbcb_depth_copy_enabled = false; 191 sctx->dbcb_stencil_copy_enabled = false; 192 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state); 193 194 return fully_copied_levels; 195} 196 197/* Helper function for si_blit_decompress_zs_in_place. 198 */ 199static void si_blit_decompress_zs_planes_in_place(struct si_context *sctx, 200 struct si_texture *texture, unsigned planes, 201 unsigned level_mask, unsigned first_layer, 202 unsigned last_layer) 203{ 204 struct pipe_surface *zsurf, surf_tmpl = {{0}}; 205 unsigned layer, max_layer, checked_last_layer; 206 unsigned fully_decompressed_mask = 0; 207 208 if (!level_mask) 209 return; 210 211 if (planes & PIPE_MASK_S) 212 sctx->db_flush_stencil_inplace = true; 213 if (planes & PIPE_MASK_Z) 214 sctx->db_flush_depth_inplace = true; 215 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state); 216 217 surf_tmpl.format = texture->buffer.b.b.format; 218 219 sctx->decompression_enabled = true; 220 221 while (level_mask) { 222 unsigned level = u_bit_scan(&level_mask); 223 224 surf_tmpl.u.tex.level = level; 225 226 /* The smaller the mipmap level, the less layers there are 227 * as far as 3D textures are concerned. */ 228 max_layer = util_max_layer(&texture->buffer.b.b, level); 229 checked_last_layer = MIN2(last_layer, max_layer); 230 231 for (layer = first_layer; layer <= checked_last_layer; layer++) { 232 surf_tmpl.u.tex.first_layer = layer; 233 surf_tmpl.u.tex.last_layer = layer; 234 235 zsurf = sctx->b.create_surface(&sctx->b, &texture->buffer.b.b, &surf_tmpl); 236 237 si_blitter_begin(sctx, SI_DECOMPRESS); 238 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, NULL, ~0, sctx->custom_dsa_flush, 239 1.0f); 240 si_blitter_end(sctx); 241 242 pipe_surface_reference(&zsurf, NULL); 243 } 244 245 /* The texture will always be dirty if some layers aren't flushed. 246 * I don't think this case occurs often though. */ 247 if (first_layer == 0 && last_layer >= max_layer) { 248 fully_decompressed_mask |= 1u << level; 249 } 250 } 251 252 if (planes & PIPE_MASK_Z) 253 texture->dirty_level_mask &= ~fully_decompressed_mask; 254 if (planes & PIPE_MASK_S) 255 texture->stencil_dirty_level_mask &= ~fully_decompressed_mask; 256 257 sctx->decompression_enabled = false; 258 sctx->db_flush_depth_inplace = false; 259 sctx->db_flush_stencil_inplace = false; 260 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state); 261} 262 263/* Helper function of si_flush_depth_texture: decompress the given levels 264 * of Z and/or S planes in place. 265 */ 266static void si_blit_decompress_zs_in_place(struct si_context *sctx, struct si_texture *texture, 267 unsigned levels_z, unsigned levels_s, 268 unsigned first_layer, unsigned last_layer) 269{ 270 unsigned both = levels_z & levels_s; 271 272 /* First, do combined Z & S decompresses for levels that need it. */ 273 if (both) { 274 si_blit_decompress_zs_planes_in_place(sctx, texture, PIPE_MASK_Z | PIPE_MASK_S, both, 275 first_layer, last_layer); 276 levels_z &= ~both; 277 levels_s &= ~both; 278 } 279 280 /* Now do separate Z and S decompresses. */ 281 if (levels_z) { 282 si_blit_decompress_zs_planes_in_place(sctx, texture, PIPE_MASK_Z, levels_z, first_layer, 283 last_layer); 284 } 285 286 if (levels_s) { 287 si_blit_decompress_zs_planes_in_place(sctx, texture, PIPE_MASK_S, levels_s, first_layer, 288 last_layer); 289 } 290} 291 292static void si_decompress_depth(struct si_context *sctx, struct si_texture *tex, 293 unsigned required_planes, unsigned first_level, unsigned last_level, 294 unsigned first_layer, unsigned last_layer) 295{ 296 unsigned inplace_planes = 0; 297 unsigned copy_planes = 0; 298 unsigned level_mask = u_bit_consecutive(first_level, last_level - first_level + 1); 299 unsigned levels_z = 0; 300 unsigned levels_s = 0; 301 302 if (required_planes & PIPE_MASK_Z) { 303 levels_z = level_mask & tex->dirty_level_mask; 304 305 if (levels_z) { 306 if (si_can_sample_zs(tex, false)) 307 inplace_planes |= PIPE_MASK_Z; 308 else 309 copy_planes |= PIPE_MASK_Z; 310 } 311 } 312 if (required_planes & PIPE_MASK_S) { 313 levels_s = level_mask & tex->stencil_dirty_level_mask; 314 315 if (levels_s) { 316 if (si_can_sample_zs(tex, true)) 317 inplace_planes |= PIPE_MASK_S; 318 else 319 copy_planes |= PIPE_MASK_S; 320 } 321 } 322 323 if (unlikely(sctx->log)) 324 u_log_printf(sctx->log, 325 "\n------------------------------------------------\n" 326 "Decompress Depth (levels %u - %u, levels Z: 0x%x S: 0x%x)\n\n", 327 first_level, last_level, levels_z, levels_s); 328 329 /* We may have to allocate the flushed texture here when called from 330 * si_decompress_subresource. 331 */ 332 if (copy_planes && 333 (tex->flushed_depth_texture || si_init_flushed_depth_texture(&sctx->b, &tex->buffer.b.b))) { 334 struct si_texture *dst = tex->flushed_depth_texture; 335 unsigned fully_copied_levels; 336 unsigned levels = 0; 337 338 assert(tex->flushed_depth_texture); 339 340 if (util_format_is_depth_and_stencil(dst->buffer.b.b.format)) 341 copy_planes = PIPE_MASK_Z | PIPE_MASK_S; 342 343 if (copy_planes & PIPE_MASK_Z) { 344 levels |= levels_z; 345 levels_z = 0; 346 } 347 if (copy_planes & PIPE_MASK_S) { 348 levels |= levels_s; 349 levels_s = 0; 350 } 351 352 fully_copied_levels = si_blit_dbcb_copy(sctx, tex, dst, copy_planes, levels, first_layer, 353 last_layer, 0, u_max_sample(&tex->buffer.b.b)); 354 355 if (copy_planes & PIPE_MASK_Z) 356 tex->dirty_level_mask &= ~fully_copied_levels; 357 if (copy_planes & PIPE_MASK_S) 358 tex->stencil_dirty_level_mask &= ~fully_copied_levels; 359 } 360 361 if (inplace_planes) { 362 bool has_htile = si_htile_enabled(tex, first_level, inplace_planes); 363 bool tc_compat_htile = vi_tc_compat_htile_enabled(tex, first_level, inplace_planes); 364 365 /* Don't decompress if there is no HTILE or when HTILE is 366 * TC-compatible. */ 367 if (has_htile && !tc_compat_htile) { 368 si_blit_decompress_zs_in_place(sctx, tex, levels_z, levels_s, first_layer, last_layer); 369 } else { 370 /* This is only a cache flush. 371 * 372 * Only clear the mask that we are flushing, because 373 * si_make_DB_shader_coherent() treats different levels 374 * and depth and stencil differently. 375 */ 376 if (inplace_planes & PIPE_MASK_Z) 377 tex->dirty_level_mask &= ~levels_z; 378 if (inplace_planes & PIPE_MASK_S) 379 tex->stencil_dirty_level_mask &= ~levels_s; 380 } 381 382 /* We just had to completely decompress Z/S for texturing. Enable 383 * TC-compatible HTILE on the next clear, so that the decompression 384 * doesn't have to be done for this texture ever again. 385 * 386 * TC-compatible HTILE might slightly reduce Z/S performance, but 387 * the decompression is much worse. 388 */ 389 if (has_htile && !tc_compat_htile && 390 /* We can only transition the whole buffer in one clear, so no mipmapping: */ 391 tex->buffer.b.b.last_level == 0 && 392 tex->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE && 393 (inplace_planes & PIPE_MASK_Z || !tex->htile_stencil_disabled)) 394 tex->enable_tc_compatible_htile_next_clear = true; 395 396 /* Only in-place decompression needs to flush DB caches, or 397 * when we don't decompress but TC-compatible planes are dirty. 398 */ 399 si_make_DB_shader_coherent(sctx, tex->buffer.b.b.nr_samples, inplace_planes & PIPE_MASK_S, 400 tc_compat_htile); 401 } 402 /* set_framebuffer_state takes care of coherency for single-sample. 403 * The DB->CB copy uses CB for the final writes. 404 */ 405 if (copy_planes && tex->buffer.b.b.nr_samples > 1) 406 si_make_CB_shader_coherent(sctx, tex->buffer.b.b.nr_samples, false, true /* no DCC */); 407} 408 409static bool si_decompress_sampler_depth_textures(struct si_context *sctx, 410 struct si_samplers *textures) 411{ 412 unsigned i; 413 unsigned mask = textures->needs_depth_decompress_mask; 414 bool need_flush = false; 415 416 while (mask) { 417 struct pipe_sampler_view *view; 418 struct si_sampler_view *sview; 419 struct si_texture *tex; 420 421 i = u_bit_scan(&mask); 422 423 view = textures->views[i]; 424 assert(view); 425 sview = (struct si_sampler_view *)view; 426 427 tex = (struct si_texture *)view->texture; 428 assert(tex->db_compatible); 429 430 si_decompress_depth(sctx, tex, sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z, 431 view->u.tex.first_level, view->u.tex.last_level, 0, 432 util_max_layer(&tex->buffer.b.b, view->u.tex.first_level)); 433 434 if (tex->need_flush_after_depth_decompression) { 435 need_flush = true; 436 tex->need_flush_after_depth_decompression = false; 437 } 438 } 439 440 return need_flush; 441} 442 443static void si_blit_decompress_color(struct si_context *sctx, struct si_texture *tex, 444 unsigned first_level, unsigned last_level, 445 unsigned first_layer, unsigned last_layer, 446 bool need_dcc_decompress, bool need_fmask_expand) 447{ 448 void *custom_blend; 449 unsigned layer, checked_last_layer, max_layer; 450 unsigned level_mask = u_bit_consecutive(first_level, last_level - first_level + 1); 451 452 if (!need_dcc_decompress) 453 level_mask &= tex->dirty_level_mask; 454 if (!level_mask) 455 goto expand_fmask; 456 457 /* No color decompression is needed on GFX11. */ 458 assert(sctx->gfx_level < GFX11 || need_dcc_decompress); 459 460 if (unlikely(sctx->log)) 461 u_log_printf(sctx->log, 462 "\n------------------------------------------------\n" 463 "Decompress Color (levels %u - %u, mask 0x%x)\n\n", 464 first_level, last_level, level_mask); 465 466 if (need_dcc_decompress) { 467 custom_blend = sctx->custom_blend_dcc_decompress; 468 469 assert(vi_dcc_enabled(tex, first_level)); 470 471 /* disable levels without DCC */ 472 for (int i = first_level; i <= last_level; i++) { 473 if (!vi_dcc_enabled(tex, i)) 474 level_mask &= ~(1 << i); 475 } 476 } else if (tex->surface.fmask_size) { 477 custom_blend = sctx->custom_blend_fmask_decompress; 478 } else { 479 custom_blend = sctx->custom_blend_eliminate_fastclear; 480 } 481 482 sctx->decompression_enabled = true; 483 484 while (level_mask) { 485 unsigned level = u_bit_scan(&level_mask); 486 487 /* The smaller the mipmap level, the less layers there are 488 * as far as 3D textures are concerned. */ 489 max_layer = util_max_layer(&tex->buffer.b.b, level); 490 checked_last_layer = MIN2(last_layer, max_layer); 491 492 for (layer = first_layer; layer <= checked_last_layer; layer++) { 493 struct pipe_surface *cbsurf, surf_tmpl; 494 495 surf_tmpl.format = tex->buffer.b.b.format; 496 surf_tmpl.u.tex.level = level; 497 surf_tmpl.u.tex.first_layer = layer; 498 surf_tmpl.u.tex.last_layer = layer; 499 cbsurf = sctx->b.create_surface(&sctx->b, &tex->buffer.b.b, &surf_tmpl); 500 501 /* Required before and after FMASK and DCC_DECOMPRESS. */ 502 if (custom_blend == sctx->custom_blend_fmask_decompress || 503 custom_blend == sctx->custom_blend_dcc_decompress) 504 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB; 505 506 si_blitter_begin(sctx, SI_DECOMPRESS); 507 util_blitter_custom_color(sctx->blitter, cbsurf, custom_blend); 508 si_blitter_end(sctx); 509 510 if (custom_blend == sctx->custom_blend_fmask_decompress || 511 custom_blend == sctx->custom_blend_dcc_decompress) 512 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB; 513 514 /* When running FMASK decompresion with DCC, we need to run the "eliminate fast clear" pass 515 * separately because FMASK decompression doesn't eliminate DCC fast clear. This makes 516 * render->texture transitions more expensive. It can be disabled by 517 * allow_dcc_msaa_clear_to_reg_for_bpp. 518 * 519 * TODO: When we get here, change the compression to TC-compatible on the next clear 520 * to disable both the FMASK decompression and fast clear elimination passes. 521 */ 522 if (sctx->screen->allow_dcc_msaa_clear_to_reg_for_bpp[util_logbase2(tex->surface.bpe)] && 523 custom_blend == sctx->custom_blend_fmask_decompress && 524 vi_dcc_enabled(tex, level)) { 525 si_blitter_begin(sctx, SI_DECOMPRESS); 526 util_blitter_custom_color(sctx->blitter, cbsurf, sctx->custom_blend_eliminate_fastclear); 527 si_blitter_end(sctx); 528 } 529 530 pipe_surface_reference(&cbsurf, NULL); 531 } 532 533 /* The texture will always be dirty if some layers aren't flushed. 534 * I don't think this case occurs often though. */ 535 if (first_layer == 0 && last_layer >= max_layer) { 536 tex->dirty_level_mask &= ~(1 << level); 537 } 538 } 539 540 sctx->decompression_enabled = false; 541 si_make_CB_shader_coherent(sctx, tex->buffer.b.b.nr_samples, vi_dcc_enabled(tex, first_level), 542 tex->surface.u.gfx9.color.dcc.pipe_aligned); 543 544expand_fmask: 545 if (need_fmask_expand && tex->surface.fmask_offset && !tex->fmask_is_identity) { 546 assert(sctx->gfx_level < GFX11); /* no FMASK on gfx11 */ 547 si_compute_expand_fmask(&sctx->b, &tex->buffer.b.b); 548 tex->fmask_is_identity = true; 549 } 550} 551 552static void si_decompress_color_texture(struct si_context *sctx, struct si_texture *tex, 553 unsigned first_level, unsigned last_level, 554 bool need_fmask_expand) 555{ 556 /* CMASK or DCC can be discarded and we can still end up here. */ 557 if (!tex->cmask_buffer && !tex->surface.fmask_size && 558 !vi_dcc_enabled(tex, first_level)) 559 return; 560 561 si_blit_decompress_color(sctx, tex, first_level, last_level, 0, 562 util_max_layer(&tex->buffer.b.b, first_level), false, 563 need_fmask_expand); 564} 565 566static void si_decompress_sampler_color_textures(struct si_context *sctx, 567 struct si_samplers *textures) 568{ 569 unsigned i; 570 unsigned mask = textures->needs_color_decompress_mask; 571 572 while (mask) { 573 struct pipe_sampler_view *view; 574 struct si_texture *tex; 575 576 i = u_bit_scan(&mask); 577 578 view = textures->views[i]; 579 assert(view); 580 581 tex = (struct si_texture *)view->texture; 582 583 si_decompress_color_texture(sctx, tex, view->u.tex.first_level, view->u.tex.last_level, 584 false); 585 } 586} 587 588static void si_decompress_image_color_textures(struct si_context *sctx, struct si_images *images) 589{ 590 unsigned i; 591 unsigned mask = images->needs_color_decompress_mask; 592 593 while (mask) { 594 const struct pipe_image_view *view; 595 struct si_texture *tex; 596 597 i = u_bit_scan(&mask); 598 599 view = &images->views[i]; 600 assert(view->resource->target != PIPE_BUFFER); 601 602 tex = (struct si_texture *)view->resource; 603 604 si_decompress_color_texture(sctx, tex, view->u.tex.level, view->u.tex.level, 605 view->access & PIPE_IMAGE_ACCESS_WRITE); 606 } 607} 608 609static void si_check_render_feedback_texture(struct si_context *sctx, struct si_texture *tex, 610 unsigned first_level, unsigned last_level, 611 unsigned first_layer, unsigned last_layer) 612{ 613 bool render_feedback = false; 614 615 if (!vi_dcc_enabled(tex, first_level)) 616 return; 617 618 for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) { 619 struct si_surface *surf; 620 621 if (!sctx->framebuffer.state.cbufs[j]) 622 continue; 623 624 surf = (struct si_surface *)sctx->framebuffer.state.cbufs[j]; 625 626 if (tex == (struct si_texture *)surf->base.texture && surf->base.u.tex.level >= first_level && 627 surf->base.u.tex.level <= last_level && surf->base.u.tex.first_layer <= last_layer && 628 surf->base.u.tex.last_layer >= first_layer) { 629 render_feedback = true; 630 break; 631 } 632 } 633 634 if (render_feedback) 635 si_texture_disable_dcc(sctx, tex); 636} 637 638static void si_check_render_feedback_textures(struct si_context *sctx, struct si_samplers *textures, 639 uint32_t in_use_mask) 640{ 641 uint32_t mask = textures->enabled_mask & in_use_mask; 642 643 while (mask) { 644 const struct pipe_sampler_view *view; 645 struct si_texture *tex; 646 647 unsigned i = u_bit_scan(&mask); 648 649 view = textures->views[i]; 650 if (view->texture->target == PIPE_BUFFER) 651 continue; 652 653 tex = (struct si_texture *)view->texture; 654 655 si_check_render_feedback_texture(sctx, tex, view->u.tex.first_level, view->u.tex.last_level, 656 view->u.tex.first_layer, view->u.tex.last_layer); 657 } 658} 659 660static void si_check_render_feedback_images(struct si_context *sctx, struct si_images *images, 661 uint32_t in_use_mask) 662{ 663 uint32_t mask = images->enabled_mask & in_use_mask; 664 665 while (mask) { 666 const struct pipe_image_view *view; 667 struct si_texture *tex; 668 669 unsigned i = u_bit_scan(&mask); 670 671 view = &images->views[i]; 672 if (view->resource->target == PIPE_BUFFER) 673 continue; 674 675 tex = (struct si_texture *)view->resource; 676 677 si_check_render_feedback_texture(sctx, tex, view->u.tex.level, view->u.tex.level, 678 view->u.tex.first_layer, view->u.tex.last_layer); 679 } 680} 681 682static void si_check_render_feedback_resident_textures(struct si_context *sctx) 683{ 684 util_dynarray_foreach (&sctx->resident_tex_handles, struct si_texture_handle *, tex_handle) { 685 struct pipe_sampler_view *view; 686 struct si_texture *tex; 687 688 view = (*tex_handle)->view; 689 if (view->texture->target == PIPE_BUFFER) 690 continue; 691 692 tex = (struct si_texture *)view->texture; 693 694 si_check_render_feedback_texture(sctx, tex, view->u.tex.first_level, view->u.tex.last_level, 695 view->u.tex.first_layer, view->u.tex.last_layer); 696 } 697} 698 699static void si_check_render_feedback_resident_images(struct si_context *sctx) 700{ 701 util_dynarray_foreach (&sctx->resident_img_handles, struct si_image_handle *, img_handle) { 702 struct pipe_image_view *view; 703 struct si_texture *tex; 704 705 view = &(*img_handle)->view; 706 if (view->resource->target == PIPE_BUFFER) 707 continue; 708 709 tex = (struct si_texture *)view->resource; 710 711 si_check_render_feedback_texture(sctx, tex, view->u.tex.level, view->u.tex.level, 712 view->u.tex.first_layer, view->u.tex.last_layer); 713 } 714} 715 716static void si_check_render_feedback(struct si_context *sctx) 717{ 718 if (!sctx->need_check_render_feedback) 719 return; 720 721 /* There is no render feedback if color writes are disabled. 722 * (e.g. a pixel shader with image stores) 723 */ 724 if (!si_get_total_colormask(sctx)) 725 return; 726 727 for (int i = 0; i < SI_NUM_GRAPHICS_SHADERS; ++i) { 728 if (!sctx->shaders[i].cso) 729 continue; 730 731 struct si_shader_info *info = &sctx->shaders[i].cso->info; 732 si_check_render_feedback_images(sctx, &sctx->images[i], 733 u_bit_consecutive(0, info->base.num_images)); 734 si_check_render_feedback_textures(sctx, &sctx->samplers[i], 735 info->base.textures_used[0]); 736 } 737 738 si_check_render_feedback_resident_images(sctx); 739 si_check_render_feedback_resident_textures(sctx); 740 741 sctx->need_check_render_feedback = false; 742} 743 744static void si_decompress_resident_textures(struct si_context *sctx) 745{ 746 util_dynarray_foreach (&sctx->resident_tex_needs_color_decompress, struct si_texture_handle *, 747 tex_handle) { 748 struct pipe_sampler_view *view = (*tex_handle)->view; 749 struct si_texture *tex = (struct si_texture *)view->texture; 750 751 si_decompress_color_texture(sctx, tex, view->u.tex.first_level, view->u.tex.last_level, 752 false); 753 } 754 755 util_dynarray_foreach (&sctx->resident_tex_needs_depth_decompress, struct si_texture_handle *, 756 tex_handle) { 757 struct pipe_sampler_view *view = (*tex_handle)->view; 758 struct si_sampler_view *sview = (struct si_sampler_view *)view; 759 struct si_texture *tex = (struct si_texture *)view->texture; 760 761 si_decompress_depth(sctx, tex, sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z, 762 view->u.tex.first_level, view->u.tex.last_level, 0, 763 util_max_layer(&tex->buffer.b.b, view->u.tex.first_level)); 764 } 765} 766 767static void si_decompress_resident_images(struct si_context *sctx) 768{ 769 util_dynarray_foreach (&sctx->resident_img_needs_color_decompress, struct si_image_handle *, 770 img_handle) { 771 struct pipe_image_view *view = &(*img_handle)->view; 772 struct si_texture *tex = (struct si_texture *)view->resource; 773 774 si_decompress_color_texture(sctx, tex, view->u.tex.level, view->u.tex.level, 775 view->access & PIPE_IMAGE_ACCESS_WRITE); 776 } 777} 778 779void si_decompress_textures(struct si_context *sctx, unsigned shader_mask) 780{ 781 unsigned compressed_colortex_counter, mask; 782 bool need_flush = false; 783 784 if (sctx->blitter_running) 785 return; 786 787 /* Update the compressed_colortex_mask if necessary. */ 788 compressed_colortex_counter = p_atomic_read(&sctx->screen->compressed_colortex_counter); 789 if (compressed_colortex_counter != sctx->last_compressed_colortex_counter) { 790 sctx->last_compressed_colortex_counter = compressed_colortex_counter; 791 si_update_needs_color_decompress_masks(sctx); 792 } 793 794 /* Decompress color & depth textures if needed. */ 795 mask = sctx->shader_needs_decompress_mask & shader_mask; 796 while (mask) { 797 unsigned i = u_bit_scan(&mask); 798 799 if (sctx->samplers[i].needs_depth_decompress_mask) { 800 need_flush |= si_decompress_sampler_depth_textures(sctx, &sctx->samplers[i]); 801 } 802 if (sctx->samplers[i].needs_color_decompress_mask) { 803 si_decompress_sampler_color_textures(sctx, &sctx->samplers[i]); 804 } 805 if (sctx->images[i].needs_color_decompress_mask) { 806 si_decompress_image_color_textures(sctx, &sctx->images[i]); 807 } 808 } 809 810 if (sctx->gfx_level == GFX10_3 && need_flush) { 811 /* This fixes a corruption with the following sequence: 812 * - fast clear depth 813 * - decompress depth 814 * - draw 815 * (see https://gitlab.freedesktop.org/drm/amd/-/issues/1810#note_1170171) 816 */ 817 sctx->b.flush(&sctx->b, NULL, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW); 818 } 819 820 if (shader_mask & u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS)) { 821 if (sctx->uses_bindless_samplers) 822 si_decompress_resident_textures(sctx); 823 if (sctx->uses_bindless_images) 824 si_decompress_resident_images(sctx); 825 826 if (sctx->ps_uses_fbfetch) { 827 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0]; 828 si_decompress_color_texture(sctx, (struct si_texture *)cb0->texture, 829 cb0->u.tex.first_layer, cb0->u.tex.last_layer, false); 830 } 831 832 si_check_render_feedback(sctx); 833 } else if (shader_mask & (1 << PIPE_SHADER_COMPUTE)) { 834 if (sctx->cs_shader_state.program->sel.info.uses_bindless_samplers) 835 si_decompress_resident_textures(sctx); 836 if (sctx->cs_shader_state.program->sel.info.uses_bindless_images) 837 si_decompress_resident_images(sctx); 838 } 839} 840 841/* Helper for decompressing a portion of a color or depth resource before 842 * blitting if any decompression is needed. 843 * The driver doesn't decompress resources automatically while u_blitter is 844 * rendering. */ 845void si_decompress_subresource(struct pipe_context *ctx, struct pipe_resource *tex, unsigned planes, 846 unsigned level, unsigned first_layer, unsigned last_layer, 847 bool need_fmask_expand) 848{ 849 struct si_context *sctx = (struct si_context *)ctx; 850 struct si_texture *stex = (struct si_texture *)tex; 851 852 if (stex->db_compatible) { 853 planes &= PIPE_MASK_Z | PIPE_MASK_S; 854 855 if (!stex->surface.has_stencil) 856 planes &= ~PIPE_MASK_S; 857 858 /* If we've rendered into the framebuffer and it's a blitting 859 * source, make sure the decompression pass is invoked 860 * by dirtying the framebuffer. 861 */ 862 if (sctx->framebuffer.state.zsbuf && sctx->framebuffer.state.zsbuf->u.tex.level == level && 863 sctx->framebuffer.state.zsbuf->texture == tex) 864 si_update_fb_dirtiness_after_rendering(sctx); 865 866 si_decompress_depth(sctx, stex, planes, level, level, first_layer, last_layer); 867 } else if (stex->surface.fmask_size || stex->cmask_buffer || 868 vi_dcc_enabled(stex, level)) { 869 /* If we've rendered into the framebuffer and it's a blitting 870 * source, make sure the decompression pass is invoked 871 * by dirtying the framebuffer. 872 */ 873 for (unsigned i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) { 874 if (sctx->framebuffer.state.cbufs[i] && 875 sctx->framebuffer.state.cbufs[i]->u.tex.level == level && 876 sctx->framebuffer.state.cbufs[i]->texture == tex) { 877 si_update_fb_dirtiness_after_rendering(sctx); 878 break; 879 } 880 } 881 882 si_blit_decompress_color(sctx, stex, level, level, first_layer, last_layer, false, 883 need_fmask_expand); 884 } 885} 886 887struct texture_orig_info { 888 unsigned format; 889 unsigned width0; 890 unsigned height0; 891 unsigned npix_x; 892 unsigned npix_y; 893 unsigned npix0_x; 894 unsigned npix0_y; 895}; 896 897void si_resource_copy_region(struct pipe_context *ctx, struct pipe_resource *dst, 898 unsigned dst_level, unsigned dstx, unsigned dsty, unsigned dstz, 899 struct pipe_resource *src, unsigned src_level, 900 const struct pipe_box *src_box) 901{ 902 struct si_context *sctx = (struct si_context *)ctx; 903 struct si_texture *ssrc = (struct si_texture *)src; 904 struct pipe_surface *dst_view, dst_templ; 905 struct pipe_sampler_view src_templ, *src_view; 906 struct pipe_box dstbox; 907 908 /* Handle buffers first. */ 909 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) { 910 si_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width, SI_OP_SYNC_BEFORE_AFTER); 911 return; 912 } 913 914 if (si_compute_copy_image(sctx, dst, dst_level, src, src_level, dstx, dsty, dstz, 915 src_box, SI_OP_SYNC_BEFORE_AFTER)) 916 return; 917 918 assert(u_max_sample(dst) == u_max_sample(src)); 919 920 /* The driver doesn't decompress resources automatically while 921 * u_blitter is rendering. */ 922 si_decompress_subresource(ctx, src, PIPE_MASK_RGBAZS, src_level, src_box->z, 923 src_box->z + src_box->depth - 1, false); 924 925 util_blitter_default_dst_texture(&dst_templ, dst, dst_level, dstz); 926 util_blitter_default_src_texture(sctx->blitter, &src_templ, src, src_level); 927 928 assert(!util_format_is_compressed(src->format) && !util_format_is_compressed(dst->format)); 929 assert(!util_format_is_subsampled_422(src->format)); 930 931 if (!util_blitter_is_copy_supported(sctx->blitter, dst, src)) { 932 switch (ssrc->surface.bpe) { 933 case 1: 934 dst_templ.format = PIPE_FORMAT_R8_UNORM; 935 src_templ.format = PIPE_FORMAT_R8_UNORM; 936 break; 937 case 2: 938 dst_templ.format = PIPE_FORMAT_R8G8_UNORM; 939 src_templ.format = PIPE_FORMAT_R8G8_UNORM; 940 break; 941 case 4: 942 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM; 943 src_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM; 944 break; 945 case 8: 946 dst_templ.format = PIPE_FORMAT_R16G16B16A16_UINT; 947 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT; 948 break; 949 case 16: 950 dst_templ.format = PIPE_FORMAT_R32G32B32A32_UINT; 951 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT; 952 break; 953 default: 954 fprintf(stderr, "Unhandled format %s with blocksize %u\n", 955 util_format_short_name(src->format), ssrc->surface.bpe); 956 assert(0); 957 } 958 } 959 960 /* SNORM blitting has precision issues on some chips. Use the SINT 961 * equivalent instead, which doesn't force DCC decompression. 962 */ 963 if (util_format_is_snorm(dst_templ.format)) { 964 dst_templ.format = src_templ.format = util_format_snorm_to_sint(dst_templ.format); 965 } 966 967 vi_disable_dcc_if_incompatible_format(sctx, dst, dst_level, dst_templ.format); 968 vi_disable_dcc_if_incompatible_format(sctx, src, src_level, src_templ.format); 969 970 /* Initialize the surface. */ 971 dst_view = ctx->create_surface(ctx, dst, &dst_templ); 972 973 /* Initialize the sampler view. */ 974 src_view = ctx->create_sampler_view(ctx, src, &src_templ); 975 976 u_box_3d(dstx, dsty, dstz, abs(src_box->width), abs(src_box->height), abs(src_box->depth), 977 &dstbox); 978 979 /* Copy. */ 980 si_blitter_begin(sctx, SI_COPY); 981 util_blitter_blit_generic(sctx->blitter, dst_view, &dstbox, src_view, src_box, src->width0, 982 src->height0, PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL, 983 false, false, 0); 984 si_blitter_end(sctx); 985 986 pipe_surface_reference(&dst_view, NULL); 987 pipe_sampler_view_reference(&src_view, NULL); 988} 989 990static void si_do_CB_resolve(struct si_context *sctx, const struct pipe_blit_info *info, 991 struct pipe_resource *dst, unsigned dst_level, unsigned dst_z, 992 enum pipe_format format) 993{ 994 /* Required before and after CB_RESOLVE. */ 995 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB; 996 997 si_blitter_begin( 998 sctx, SI_COLOR_RESOLVE | (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND)); 999 util_blitter_custom_resolve_color(sctx->blitter, dst, dst_level, dst_z, info->src.resource, 1000 info->src.box.z, ~0, sctx->custom_blend_resolve, format); 1001 si_blitter_end(sctx); 1002 1003 /* Flush caches for possible texturing. */ 1004 si_make_CB_shader_coherent(sctx, 1, false, true /* no DCC */); 1005} 1006 1007static bool resolve_formats_compatible(enum pipe_format src, enum pipe_format dst, 1008 bool src_swaps_rgb_to_bgr, bool *need_rgb_to_bgr) 1009{ 1010 *need_rgb_to_bgr = false; 1011 1012 if (src_swaps_rgb_to_bgr) { 1013 /* We must only check the swapped format. */ 1014 enum pipe_format swapped_src = util_format_rgb_to_bgr(src); 1015 assert(swapped_src); 1016 return util_is_format_compatible(util_format_description(swapped_src), 1017 util_format_description(dst)); 1018 } 1019 1020 if (util_is_format_compatible(util_format_description(src), util_format_description(dst))) 1021 return true; 1022 1023 enum pipe_format swapped_src = util_format_rgb_to_bgr(src); 1024 *need_rgb_to_bgr = util_is_format_compatible(util_format_description(swapped_src), 1025 util_format_description(dst)); 1026 return *need_rgb_to_bgr; 1027} 1028 1029bool si_msaa_resolve_blit_via_CB(struct pipe_context *ctx, const struct pipe_blit_info *info) 1030{ 1031 struct si_context *sctx = (struct si_context *)ctx; 1032 1033 /* Gfx11 doesn't have CB_RESOLVE. */ 1034 if (sctx->gfx_level >= GFX11) 1035 return false; 1036 1037 struct si_texture *src = (struct si_texture *)info->src.resource; 1038 struct si_texture *dst = (struct si_texture *)info->dst.resource; 1039 ASSERTED struct si_texture *stmp; 1040 unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level); 1041 unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level); 1042 enum pipe_format format = info->src.format; 1043 struct pipe_resource *tmp, templ; 1044 struct pipe_blit_info blit; 1045 1046 /* Gfx11 doesn't have CB_RESOLVE. */ 1047 if (sctx->gfx_level >= GFX11) 1048 return false; 1049 1050 /* Check basic requirements for hw resolve. */ 1051 if (!(info->src.resource->nr_samples > 1 && info->dst.resource->nr_samples <= 1 && 1052 !util_format_is_pure_integer(format) && !util_format_is_depth_or_stencil(format) && 1053 util_max_layer(info->src.resource, 0) == 0)) 1054 return false; 1055 1056 /* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and 1057 * the format is R16G16. Use R16A16, which does work. 1058 */ 1059 if (format == PIPE_FORMAT_R16G16_UNORM) 1060 format = PIPE_FORMAT_R16A16_UNORM; 1061 if (format == PIPE_FORMAT_R16G16_SNORM) 1062 format = PIPE_FORMAT_R16A16_SNORM; 1063 1064 bool need_rgb_to_bgr = false; 1065 1066 /* Check the remaining requirements for hw resolve. */ 1067 if (util_max_layer(info->dst.resource, info->dst.level) == 0 && !info->scissor_enable && 1068 (info->mask & PIPE_MASK_RGBA) == PIPE_MASK_RGBA && 1069 resolve_formats_compatible(info->src.format, info->dst.format, 1070 src->swap_rgb_to_bgr, &need_rgb_to_bgr) && 1071 dst_width == info->src.resource->width0 && dst_height == info->src.resource->height0 && 1072 info->dst.box.x == 0 && info->dst.box.y == 0 && info->dst.box.width == dst_width && 1073 info->dst.box.height == dst_height && info->dst.box.depth == 1 && info->src.box.x == 0 && 1074 info->src.box.y == 0 && info->src.box.width == dst_width && 1075 info->src.box.height == dst_height && info->src.box.depth == 1 && !dst->surface.is_linear && 1076 (!dst->cmask_buffer || !dst->dirty_level_mask)) { /* dst cannot be fast-cleared */ 1077 /* Check the remaining constraints. */ 1078 if (src->surface.micro_tile_mode != dst->surface.micro_tile_mode || 1079 need_rgb_to_bgr) { 1080 /* The next fast clear will switch to this mode to 1081 * get direct hw resolve next time if the mode is 1082 * different now. 1083 * 1084 * TODO-GFX10: This does not work in GFX10 because MSAA 1085 * is restricted to 64KB_R_X and 64KB_Z_X swizzle modes. 1086 * In some cases we could change the swizzle of the 1087 * destination texture instead, but the more general 1088 * solution is to implement compute shader resolve. 1089 */ 1090 if (src->surface.micro_tile_mode != dst->surface.micro_tile_mode) 1091 src->last_msaa_resolve_target_micro_mode = dst->surface.micro_tile_mode; 1092 if (need_rgb_to_bgr) 1093 src->swap_rgb_to_bgr_on_next_clear = true; 1094 1095 goto resolve_to_temp; 1096 } 1097 1098 /* Resolving into a surface with DCC is unsupported. Since 1099 * it's being overwritten anyway, clear it to uncompressed. 1100 * This is still the fastest codepath even with this clear. 1101 */ 1102 if (vi_dcc_enabled(dst, info->dst.level)) { 1103 struct si_clear_info clear_info; 1104 1105 if (!vi_dcc_get_clear_info(sctx, dst, info->dst.level, DCC_UNCOMPRESSED, &clear_info)) 1106 goto resolve_to_temp; 1107 1108 si_execute_clears(sctx, &clear_info, 1, SI_CLEAR_TYPE_DCC); 1109 dst->dirty_level_mask &= ~(1 << info->dst.level); 1110 } 1111 1112 /* Resolve directly from src to dst. */ 1113 si_do_CB_resolve(sctx, info, info->dst.resource, info->dst.level, info->dst.box.z, format); 1114 return true; 1115 } 1116 1117resolve_to_temp: 1118 /* Shader-based resolve is VERY SLOW. Instead, resolve into 1119 * a temporary texture and blit. 1120 */ 1121 memset(&templ, 0, sizeof(templ)); 1122 templ.target = PIPE_TEXTURE_2D; 1123 templ.format = info->src.resource->format; 1124 templ.width0 = info->src.resource->width0; 1125 templ.height0 = info->src.resource->height0; 1126 templ.depth0 = 1; 1127 templ.array_size = 1; 1128 templ.usage = PIPE_USAGE_DEFAULT; 1129 templ.flags = SI_RESOURCE_FLAG_FORCE_MSAA_TILING | SI_RESOURCE_FLAG_FORCE_MICRO_TILE_MODE | 1130 SI_RESOURCE_FLAG_MICRO_TILE_MODE_SET(src->surface.micro_tile_mode) | 1131 SI_RESOURCE_FLAG_DISABLE_DCC | SI_RESOURCE_FLAG_DRIVER_INTERNAL; 1132 1133 /* The src and dst microtile modes must be the same. */ 1134 if (sctx->gfx_level <= GFX8 && src->surface.micro_tile_mode == RADEON_MICRO_MODE_DISPLAY) 1135 templ.bind = PIPE_BIND_SCANOUT; 1136 else 1137 templ.bind = 0; 1138 1139 tmp = ctx->screen->resource_create(ctx->screen, &templ); 1140 if (!tmp) 1141 return false; 1142 stmp = (struct si_texture *)tmp; 1143 /* Match the channel order of src. */ 1144 stmp->swap_rgb_to_bgr = src->swap_rgb_to_bgr; 1145 1146 assert(!stmp->surface.is_linear); 1147 assert(src->surface.micro_tile_mode == stmp->surface.micro_tile_mode); 1148 1149 /* resolve */ 1150 si_do_CB_resolve(sctx, info, tmp, 0, 0, format); 1151 1152 /* blit */ 1153 blit = *info; 1154 blit.src.resource = tmp; 1155 blit.src.box.z = 0; 1156 1157 ctx->blit(ctx, &blit); 1158 1159 pipe_resource_reference(&tmp, NULL); 1160 return true; 1161} 1162 1163static void si_blit(struct pipe_context *ctx, const struct pipe_blit_info *info) 1164{ 1165 struct si_context *sctx = (struct si_context *)ctx; 1166 struct si_texture *sdst = (struct si_texture *)info->dst.resource; 1167 1168 if (sctx->gfx_level >= GFX7 && 1169 (info->dst.resource->bind & PIPE_BIND_PRIME_BLIT_DST) && sdst->surface.is_linear && 1170 /* Use SDMA or async compute when copying to a DRI_PRIME imported linear surface. */ 1171 info->dst.box.x == 0 && info->dst.box.y == 0 && info->dst.box.z == 0 && 1172 info->src.box.x == 0 && info->src.box.y == 0 && info->src.box.z == 0 && 1173 info->dst.level == 0 && info->src.level == 0 && 1174 info->src.box.width == info->dst.resource->width0 && 1175 info->src.box.height == info->dst.resource->height0 && 1176 info->src.box.depth == 1 && 1177 util_can_blit_via_copy_region(info, true, sctx->render_cond != NULL)) { 1178 struct si_texture *ssrc = (struct si_texture *)info->src.resource; 1179 1180 /* Try SDMA first... */ 1181 if (si_sdma_copy_image(sctx, sdst, ssrc)) 1182 return; 1183 1184 /* ... and use async compute as the fallback. */ 1185 struct si_screen *sscreen = sctx->screen; 1186 1187 simple_mtx_lock(&sscreen->async_compute_context_lock); 1188 if (!sscreen->async_compute_context) 1189 si_init_aux_async_compute_ctx(sscreen); 1190 1191 if (sscreen->async_compute_context) { 1192 si_compute_copy_image((struct si_context*)sctx->screen->async_compute_context, 1193 info->dst.resource, 0, info->src.resource, 0, 0, 0, 0, 1194 &info->src.box, 0); 1195 si_flush_gfx_cs((struct si_context*)sctx->screen->async_compute_context, 0, NULL); 1196 simple_mtx_unlock(&sscreen->async_compute_context_lock); 1197 return; 1198 } 1199 1200 simple_mtx_unlock(&sscreen->async_compute_context_lock); 1201 } 1202 1203 if (unlikely(sctx->thread_trace_enabled)) 1204 sctx->sqtt_next_event = EventCmdResolveImage; 1205 1206 if (si_msaa_resolve_blit_via_CB(ctx, info)) 1207 return; 1208 1209 if (unlikely(sctx->thread_trace_enabled)) 1210 sctx->sqtt_next_event = EventCmdCopyImage; 1211 1212 /* Using compute for copying to a linear texture in GTT is much faster than 1213 * going through RBs (render backends). This improves DRI PRIME performance. 1214 */ 1215 if (util_can_blit_via_copy_region(info, false, sctx->render_cond != NULL)) { 1216 si_resource_copy_region(ctx, info->dst.resource, info->dst.level, 1217 info->dst.box.x, info->dst.box.y, info->dst.box.z, 1218 info->src.resource, info->src.level, &info->src.box); 1219 return; 1220 } 1221 1222 si_gfx_blit(ctx, info); 1223} 1224 1225void si_gfx_blit(struct pipe_context *ctx, const struct pipe_blit_info *info) 1226{ 1227 struct si_context *sctx = (struct si_context *)ctx; 1228 1229 assert(util_blitter_is_blit_supported(sctx->blitter, info)); 1230 1231 /* The driver doesn't decompress resources automatically while 1232 * u_blitter is rendering. */ 1233 vi_disable_dcc_if_incompatible_format(sctx, info->src.resource, info->src.level, 1234 info->src.format); 1235 vi_disable_dcc_if_incompatible_format(sctx, info->dst.resource, info->dst.level, 1236 info->dst.format); 1237 si_decompress_subresource(ctx, info->src.resource, PIPE_MASK_RGBAZS, info->src.level, 1238 info->src.box.z, info->src.box.z + info->src.box.depth - 1, 1239 false); 1240 1241 if (unlikely(sctx->thread_trace_enabled)) 1242 sctx->sqtt_next_event = EventCmdBlitImage; 1243 1244 si_blitter_begin(sctx, SI_BLIT | (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND)); 1245 util_blitter_blit(sctx->blitter, info); 1246 si_blitter_end(sctx); 1247} 1248 1249static bool si_generate_mipmap(struct pipe_context *ctx, struct pipe_resource *tex, 1250 enum pipe_format format, unsigned base_level, unsigned last_level, 1251 unsigned first_layer, unsigned last_layer) 1252{ 1253 struct si_context *sctx = (struct si_context *)ctx; 1254 struct si_texture *stex = (struct si_texture *)tex; 1255 1256 if (!util_blitter_is_copy_supported(sctx->blitter, tex, tex)) 1257 return false; 1258 1259 /* The driver doesn't decompress resources automatically while 1260 * u_blitter is rendering. */ 1261 vi_disable_dcc_if_incompatible_format(sctx, tex, base_level, format); 1262 si_decompress_subresource(ctx, tex, PIPE_MASK_RGBAZS, base_level, first_layer, last_layer, 1263 false); 1264 1265 /* Clear dirty_level_mask for the levels that will be overwritten. */ 1266 assert(base_level < last_level); 1267 stex->dirty_level_mask &= ~u_bit_consecutive(base_level + 1, last_level - base_level); 1268 1269 sctx->generate_mipmap_for_depth = stex->is_depth; 1270 1271 si_blitter_begin(sctx, SI_BLIT | SI_DISABLE_RENDER_COND); 1272 util_blitter_generate_mipmap(sctx->blitter, tex, format, base_level, last_level, first_layer, 1273 last_layer); 1274 si_blitter_end(sctx); 1275 1276 sctx->generate_mipmap_for_depth = false; 1277 return true; 1278} 1279 1280static void si_flush_resource(struct pipe_context *ctx, struct pipe_resource *res) 1281{ 1282 struct si_context *sctx = (struct si_context *)ctx; 1283 struct si_texture *tex = (struct si_texture *)res; 1284 1285 if (res->target == PIPE_BUFFER) 1286 return; 1287 1288 if (!tex->is_depth && (tex->cmask_buffer || vi_dcc_enabled(tex, 0))) { 1289 si_blit_decompress_color(sctx, tex, 0, res->last_level, 0, util_max_layer(res, 0), 1290 false, false); 1291 1292 if (tex->surface.display_dcc_offset && tex->displayable_dcc_dirty) { 1293 si_retile_dcc(sctx, tex); 1294 tex->displayable_dcc_dirty = false; 1295 } 1296 } 1297} 1298 1299void si_flush_implicit_resources(struct si_context *sctx) 1300{ 1301 hash_table_foreach(sctx->dirty_implicit_resources, entry) { 1302 si_flush_resource(&sctx->b, entry->data); 1303 pipe_resource_reference((struct pipe_resource **)&entry->data, NULL); 1304 } 1305 _mesa_hash_table_clear(sctx->dirty_implicit_resources, NULL); 1306} 1307 1308void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex) 1309{ 1310 assert(!tex->is_depth); 1311 1312 /* If graphics is disabled, we can't decompress DCC, but it shouldn't 1313 * be compressed either. The caller should simply discard it. 1314 */ 1315 if (!tex->surface.meta_offset || !sctx->has_graphics) 1316 return; 1317 1318 si_blit_decompress_color(sctx, tex, 0, tex->buffer.b.b.last_level, 0, 1319 util_max_layer(&tex->buffer.b.b, 0), true, false); 1320} 1321 1322void si_init_blit_functions(struct si_context *sctx) 1323{ 1324 sctx->b.resource_copy_region = si_resource_copy_region; 1325 1326 if (sctx->has_graphics) { 1327 sctx->b.blit = si_blit; 1328 sctx->b.flush_resource = si_flush_resource; 1329 sctx->b.generate_mipmap = si_generate_mipmap; 1330 } 1331} 1332