1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23#include "r600_formats.h" 24#include "r600_shader.h" 25#include "r600d.h" 26 27#include "pipe/p_shader_tokens.h" 28#include "util/u_pack_color.h" 29#include "util/u_memory.h" 30#include "util/u_framebuffer.h" 31#include "util/u_dual_blend.h" 32 33static uint32_t r600_translate_blend_function(int blend_func) 34{ 35 switch (blend_func) { 36 case PIPE_BLEND_ADD: 37 return V_028804_COMB_DST_PLUS_SRC; 38 case PIPE_BLEND_SUBTRACT: 39 return V_028804_COMB_SRC_MINUS_DST; 40 case PIPE_BLEND_REVERSE_SUBTRACT: 41 return V_028804_COMB_DST_MINUS_SRC; 42 case PIPE_BLEND_MIN: 43 return V_028804_COMB_MIN_DST_SRC; 44 case PIPE_BLEND_MAX: 45 return V_028804_COMB_MAX_DST_SRC; 46 default: 47 R600_ERR("Unknown blend function %d\n", blend_func); 48 assert(0); 49 break; 50 } 51 return 0; 52} 53 54static uint32_t r600_translate_blend_factor(int blend_fact) 55{ 56 switch (blend_fact) { 57 case PIPE_BLENDFACTOR_ONE: 58 return V_028804_BLEND_ONE; 59 case PIPE_BLENDFACTOR_SRC_COLOR: 60 return V_028804_BLEND_SRC_COLOR; 61 case PIPE_BLENDFACTOR_SRC_ALPHA: 62 return V_028804_BLEND_SRC_ALPHA; 63 case PIPE_BLENDFACTOR_DST_ALPHA: 64 return V_028804_BLEND_DST_ALPHA; 65 case PIPE_BLENDFACTOR_DST_COLOR: 66 return V_028804_BLEND_DST_COLOR; 67 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE: 68 return V_028804_BLEND_SRC_ALPHA_SATURATE; 69 case PIPE_BLENDFACTOR_CONST_COLOR: 70 return V_028804_BLEND_CONST_COLOR; 71 case PIPE_BLENDFACTOR_CONST_ALPHA: 72 return V_028804_BLEND_CONST_ALPHA; 73 case PIPE_BLENDFACTOR_ZERO: 74 return V_028804_BLEND_ZERO; 75 case PIPE_BLENDFACTOR_INV_SRC_COLOR: 76 return V_028804_BLEND_ONE_MINUS_SRC_COLOR; 77 case PIPE_BLENDFACTOR_INV_SRC_ALPHA: 78 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA; 79 case PIPE_BLENDFACTOR_INV_DST_ALPHA: 80 return V_028804_BLEND_ONE_MINUS_DST_ALPHA; 81 case PIPE_BLENDFACTOR_INV_DST_COLOR: 82 return V_028804_BLEND_ONE_MINUS_DST_COLOR; 83 case PIPE_BLENDFACTOR_INV_CONST_COLOR: 84 return V_028804_BLEND_ONE_MINUS_CONST_COLOR; 85 case PIPE_BLENDFACTOR_INV_CONST_ALPHA: 86 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA; 87 case PIPE_BLENDFACTOR_SRC1_COLOR: 88 return V_028804_BLEND_SRC1_COLOR; 89 case PIPE_BLENDFACTOR_SRC1_ALPHA: 90 return V_028804_BLEND_SRC1_ALPHA; 91 case PIPE_BLENDFACTOR_INV_SRC1_COLOR: 92 return V_028804_BLEND_INV_SRC1_COLOR; 93 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA: 94 return V_028804_BLEND_INV_SRC1_ALPHA; 95 default: 96 R600_ERR("Bad blend factor %d not supported!\n", blend_fact); 97 assert(0); 98 break; 99 } 100 return 0; 101} 102 103static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples) 104{ 105 switch (dim) { 106 default: 107 case PIPE_TEXTURE_1D: 108 return V_038000_SQ_TEX_DIM_1D; 109 case PIPE_TEXTURE_1D_ARRAY: 110 return V_038000_SQ_TEX_DIM_1D_ARRAY; 111 case PIPE_TEXTURE_2D: 112 case PIPE_TEXTURE_RECT: 113 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA : 114 V_038000_SQ_TEX_DIM_2D; 115 case PIPE_TEXTURE_2D_ARRAY: 116 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA : 117 V_038000_SQ_TEX_DIM_2D_ARRAY; 118 case PIPE_TEXTURE_3D: 119 return V_038000_SQ_TEX_DIM_3D; 120 case PIPE_TEXTURE_CUBE: 121 case PIPE_TEXTURE_CUBE_ARRAY: 122 return V_038000_SQ_TEX_DIM_CUBEMAP; 123 } 124} 125 126static uint32_t r600_translate_dbformat(enum pipe_format format) 127{ 128 switch (format) { 129 case PIPE_FORMAT_Z16_UNORM: 130 return V_028010_DEPTH_16; 131 case PIPE_FORMAT_Z24X8_UNORM: 132 return V_028010_DEPTH_X8_24; 133 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 134 return V_028010_DEPTH_8_24; 135 case PIPE_FORMAT_Z32_FLOAT: 136 return V_028010_DEPTH_32_FLOAT; 137 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 138 return V_028010_DEPTH_X24_8_32_FLOAT; 139 default: 140 return ~0U; 141 } 142} 143 144static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format) 145{ 146 return r600_translate_texformat(screen, format, NULL, NULL, NULL, 147 FALSE) != ~0U; 148} 149 150static bool r600_is_colorbuffer_format_supported(enum amd_gfx_level chip, enum pipe_format format) 151{ 152 return r600_translate_colorformat(chip, format, FALSE) != ~0U && 153 r600_translate_colorswap(format, FALSE) != ~0U; 154} 155 156static bool r600_is_zs_format_supported(enum pipe_format format) 157{ 158 return r600_translate_dbformat(format) != ~0U; 159} 160 161bool r600_is_format_supported(struct pipe_screen *screen, 162 enum pipe_format format, 163 enum pipe_texture_target target, 164 unsigned sample_count, 165 unsigned storage_sample_count, 166 unsigned usage) 167{ 168 struct r600_screen *rscreen = (struct r600_screen*)screen; 169 unsigned retval = 0; 170 171 if (target >= PIPE_MAX_TEXTURE_TYPES) { 172 R600_ERR("r600: unsupported texture type %d\n", target); 173 return false; 174 } 175 176 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count)) 177 return false; 178 179 if (sample_count > 1) { 180 if (!rscreen->has_msaa) 181 return false; 182 183 /* R11G11B10 is broken on R6xx. */ 184 if (rscreen->b.gfx_level == R600 && 185 format == PIPE_FORMAT_R11G11B10_FLOAT) 186 return false; 187 188 /* MSAA integer colorbuffers hang. */ 189 if (util_format_is_pure_integer(format) && 190 !util_format_is_depth_or_stencil(format)) 191 return false; 192 193 switch (sample_count) { 194 case 2: 195 case 4: 196 case 8: 197 break; 198 default: 199 return false; 200 } 201 } 202 203 if (usage & PIPE_BIND_SAMPLER_VIEW) { 204 if (target == PIPE_BUFFER) { 205 if (r600_is_buffer_format_supported(format, false)) 206 retval |= PIPE_BIND_SAMPLER_VIEW; 207 } else { 208 if (r600_is_sampler_format_supported(screen, format)) 209 retval |= PIPE_BIND_SAMPLER_VIEW; 210 } 211 } 212 213 if ((usage & (PIPE_BIND_RENDER_TARGET | 214 PIPE_BIND_DISPLAY_TARGET | 215 PIPE_BIND_SCANOUT | 216 PIPE_BIND_SHARED | 217 PIPE_BIND_BLENDABLE)) && 218 r600_is_colorbuffer_format_supported(rscreen->b.gfx_level, format)) { 219 retval |= usage & 220 (PIPE_BIND_RENDER_TARGET | 221 PIPE_BIND_DISPLAY_TARGET | 222 PIPE_BIND_SCANOUT | 223 PIPE_BIND_SHARED); 224 if (!util_format_is_pure_integer(format) && 225 !util_format_is_depth_or_stencil(format)) 226 retval |= usage & PIPE_BIND_BLENDABLE; 227 } 228 229 if ((usage & PIPE_BIND_DEPTH_STENCIL) && 230 r600_is_zs_format_supported(format)) { 231 retval |= PIPE_BIND_DEPTH_STENCIL; 232 } 233 234 if ((usage & PIPE_BIND_VERTEX_BUFFER) && 235 r600_is_buffer_format_supported(format, true)) { 236 retval |= PIPE_BIND_VERTEX_BUFFER; 237 } 238 239 if (usage & PIPE_BIND_INDEX_BUFFER && 240 r600_is_index_format_supported(format)) { 241 retval |= PIPE_BIND_INDEX_BUFFER; 242 } 243 244 if ((usage & PIPE_BIND_LINEAR) && 245 !util_format_is_compressed(format) && 246 !(usage & PIPE_BIND_DEPTH_STENCIL)) 247 retval |= PIPE_BIND_LINEAR; 248 249 return retval == usage; 250} 251 252static void r600_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a) 253{ 254 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; 255 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a; 256 float offset_units = state->offset_units; 257 float offset_scale = state->offset_scale; 258 uint32_t pa_su_poly_offset_db_fmt_cntl = 0; 259 260 if (!state->offset_units_unscaled) { 261 switch (state->zs_format) { 262 case PIPE_FORMAT_Z24X8_UNORM: 263 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 264 offset_units *= 2.0f; 265 pa_su_poly_offset_db_fmt_cntl = 266 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24); 267 break; 268 case PIPE_FORMAT_Z16_UNORM: 269 offset_units *= 4.0f; 270 pa_su_poly_offset_db_fmt_cntl = 271 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16); 272 break; 273 default: 274 pa_su_poly_offset_db_fmt_cntl = 275 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) | 276 S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1); 277 } 278 } 279 280 radeon_set_context_reg_seq(cs, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 4); 281 radeon_emit(cs, fui(offset_scale)); 282 radeon_emit(cs, fui(offset_units)); 283 radeon_emit(cs, fui(offset_scale)); 284 radeon_emit(cs, fui(offset_units)); 285 286 radeon_set_context_reg(cs, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 287 pa_su_poly_offset_db_fmt_cntl); 288} 289 290static uint32_t r600_get_blend_control(const struct pipe_blend_state *state, unsigned i) 291{ 292 int j = state->independent_blend_enable ? i : 0; 293 294 unsigned eqRGB = state->rt[j].rgb_func; 295 unsigned srcRGB = state->rt[j].rgb_src_factor; 296 unsigned dstRGB = state->rt[j].rgb_dst_factor; 297 298 unsigned eqA = state->rt[j].alpha_func; 299 unsigned srcA = state->rt[j].alpha_src_factor; 300 unsigned dstA = state->rt[j].alpha_dst_factor; 301 uint32_t bc = 0; 302 303 if (!state->rt[j].blend_enable) 304 return 0; 305 306 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB)); 307 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB)); 308 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB)); 309 310 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { 311 bc |= S_028804_SEPARATE_ALPHA_BLEND(1); 312 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA)); 313 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA)); 314 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA)); 315 } 316 return bc; 317} 318 319static void *r600_create_blend_state_mode(struct pipe_context *ctx, 320 const struct pipe_blend_state *state, 321 int mode) 322{ 323 struct r600_context *rctx = (struct r600_context *)ctx; 324 uint32_t color_control = 0, target_mask = 0; 325 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state); 326 327 if (!blend) { 328 return NULL; 329 } 330 331 r600_init_command_buffer(&blend->buffer, 20); 332 r600_init_command_buffer(&blend->buffer_no_blend, 20); 333 334 /* R600 does not support per-MRT blends */ 335 if (rctx->b.family > CHIP_R600) 336 color_control |= S_028808_PER_MRT_BLEND(1); 337 338 if (state->logicop_enable) { 339 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20); 340 } else { 341 color_control |= (0xcc << 16); 342 } 343 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */ 344 if (state->independent_blend_enable) { 345 for (int i = 0; i < 8; i++) { 346 if (state->rt[i].blend_enable) { 347 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i); 348 } 349 target_mask |= (state->rt[i].colormask << (4 * i)); 350 } 351 } else { 352 for (int i = 0; i < 8; i++) { 353 if (state->rt[0].blend_enable) { 354 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i); 355 } 356 target_mask |= (state->rt[0].colormask << (4 * i)); 357 } 358 } 359 360 if (target_mask) 361 color_control |= S_028808_SPECIAL_OP(mode); 362 else 363 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE); 364 365 /* only MRT0 has dual src blend */ 366 blend->dual_src_blend = util_blend_state_is_dual(state, 0); 367 blend->cb_target_mask = target_mask; 368 blend->cb_color_control = color_control; 369 blend->cb_color_control_no_blend = color_control & C_028808_TARGET_BLEND_ENABLE; 370 blend->alpha_to_one = state->alpha_to_one; 371 372 r600_store_context_reg(&blend->buffer, R_028D44_DB_ALPHA_TO_MASK, 373 S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) | 374 S_028D44_ALPHA_TO_MASK_OFFSET0(2) | 375 S_028D44_ALPHA_TO_MASK_OFFSET1(2) | 376 S_028D44_ALPHA_TO_MASK_OFFSET2(2) | 377 S_028D44_ALPHA_TO_MASK_OFFSET3(2)); 378 379 /* Copy over the registers set so far into buffer_no_blend. */ 380 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4); 381 blend->buffer_no_blend.num_dw = blend->buffer.num_dw; 382 383 /* Only add blend registers if blending is enabled. */ 384 if (!G_028808_TARGET_BLEND_ENABLE(color_control)) { 385 return blend; 386 } 387 388 /* The first R600 does not support per-MRT blends */ 389 r600_store_context_reg(&blend->buffer, R_028804_CB_BLEND_CONTROL, 390 r600_get_blend_control(state, 0)); 391 392 if (rctx->b.family > CHIP_R600) { 393 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8); 394 for (int i = 0; i < 8; i++) { 395 r600_store_value(&blend->buffer, r600_get_blend_control(state, i)); 396 } 397 } 398 return blend; 399} 400 401static void *r600_create_blend_state(struct pipe_context *ctx, 402 const struct pipe_blend_state *state) 403{ 404 return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL); 405} 406 407static void *r600_create_dsa_state(struct pipe_context *ctx, 408 const struct pipe_depth_stencil_alpha_state *state) 409{ 410 unsigned db_depth_control, alpha_test_control, alpha_ref; 411 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state); 412 413 if (!dsa) { 414 return NULL; 415 } 416 417 r600_init_command_buffer(&dsa->buffer, 3); 418 419 dsa->valuemask[0] = state->stencil[0].valuemask; 420 dsa->valuemask[1] = state->stencil[1].valuemask; 421 dsa->writemask[0] = state->stencil[0].writemask; 422 dsa->writemask[1] = state->stencil[1].writemask; 423 dsa->zwritemask = state->depth_writemask; 424 425 db_depth_control = S_028800_Z_ENABLE(state->depth_enabled) | 426 S_028800_Z_WRITE_ENABLE(state->depth_writemask) | 427 S_028800_ZFUNC(state->depth_func); 428 429 /* stencil */ 430 if (state->stencil[0].enabled) { 431 db_depth_control |= S_028800_STENCIL_ENABLE(1); 432 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */ 433 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op)); 434 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op)); 435 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op)); 436 437 if (state->stencil[1].enabled) { 438 db_depth_control |= S_028800_BACKFACE_ENABLE(1); 439 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */ 440 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op)); 441 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op)); 442 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op)); 443 } 444 } 445 446 /* alpha */ 447 alpha_test_control = 0; 448 alpha_ref = 0; 449 if (state->alpha_enabled) { 450 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha_func); 451 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1); 452 alpha_ref = fui(state->alpha_ref_value); 453 } 454 dsa->sx_alpha_test_control = alpha_test_control & 0xff; 455 dsa->alpha_ref = alpha_ref; 456 457 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control); 458 return dsa; 459} 460 461static void *r600_create_rs_state(struct pipe_context *ctx, 462 const struct pipe_rasterizer_state *state) 463{ 464 struct r600_context *rctx = (struct r600_context *)ctx; 465 unsigned tmp, sc_mode_cntl, spi_interp; 466 float psize_min, psize_max; 467 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state); 468 469 if (!rs) { 470 return NULL; 471 } 472 473 r600_init_command_buffer(&rs->buffer, 30); 474 475 rs->scissor_enable = state->scissor; 476 rs->clip_halfz = state->clip_halfz; 477 rs->flatshade = state->flatshade; 478 rs->sprite_coord_enable = state->sprite_coord_enable; 479 rs->rasterizer_discard = state->rasterizer_discard; 480 rs->two_side = state->light_twoside; 481 rs->clip_plane_enable = state->clip_plane_enable; 482 rs->pa_sc_line_stipple = state->line_stipple_enable ? 483 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) | 484 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0; 485 rs->pa_cl_clip_cntl = 486 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) | 487 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) | 488 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_far) | 489 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1); 490 if (rctx->b.gfx_level == R700) { 491 rs->pa_cl_clip_cntl |= 492 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard); 493 } 494 rs->multisample_enable = state->multisample; 495 496 /* offset */ 497 rs->offset_units = state->offset_units; 498 rs->offset_scale = state->offset_scale * 16.0f; 499 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri; 500 rs->offset_units_unscaled = state->offset_units_unscaled; 501 502 if (state->point_size_per_vertex) { 503 psize_min = util_get_min_point_size(state); 504 psize_max = 8192; 505 } else { 506 /* Force the point size to be as if the vertex output was disabled. */ 507 psize_min = state->point_size; 508 psize_max = state->point_size; 509 } 510 511 sc_mode_cntl = S_028A4C_MSAA_ENABLE(state->multisample) | 512 S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable) | 513 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) | 514 S_028A4C_PS_ITER_SAMPLE(state->multisample && rctx->ps_iter_samples > 1); 515 if (rctx->b.family == CHIP_RV770) { 516 /* workaround possible rendering corruption on RV770 with hyperz together with sample shading */ 517 sc_mode_cntl |= S_028A4C_TILE_COVER_DISABLE(state->multisample && rctx->ps_iter_samples > 1); 518 } 519 if (rctx->b.gfx_level >= R700) { 520 sc_mode_cntl |= S_028A4C_FORCE_EOV_REZ_ENABLE(1) | 521 S_028A4C_R700_ZMM_LINE_OFFSET(1) | 522 S_028A4C_R700_VPORT_SCISSOR_ENABLE(1); 523 } else { 524 sc_mode_cntl |= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1); 525 } 526 527 spi_interp = S_0286D4_FLAT_SHADE_ENA(1); 528 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) | 529 S_0286D4_PNT_SPRITE_OVRD_X(2) | 530 S_0286D4_PNT_SPRITE_OVRD_Y(3) | 531 S_0286D4_PNT_SPRITE_OVRD_Z(0) | 532 S_0286D4_PNT_SPRITE_OVRD_W(1); 533 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) { 534 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1); 535 } 536 537 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3); 538 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */ 539 tmp = r600_pack_float_12p4(state->point_size/2); 540 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */ 541 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp)); 542 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */ 543 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) | 544 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2))); 545 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */ 546 S_028A08_WIDTH(r600_pack_float_12p4(state->line_width/2))); 547 548 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp); 549 r600_store_context_reg(&rs->buffer, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl); 550 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL, 551 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) | 552 S_028C08_QUANT_MODE(V_028C08_X_1_256TH)); 553 r600_store_context_reg(&rs->buffer, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp)); 554 555 rs->pa_su_sc_mode_cntl = S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) | 556 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) | 557 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) | 558 S_028814_FACE(!state->front_ccw) | 559 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) | 560 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) | 561 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) | 562 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL || 563 state->fill_back != PIPE_POLYGON_MODE_FILL) | 564 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) | 565 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)); 566 if (rctx->b.gfx_level == R700) { 567 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL, rs->pa_su_sc_mode_cntl); 568 } 569 if (rctx->b.gfx_level == R600) { 570 r600_store_context_reg(&rs->buffer, R_028350_SX_MISC, 571 S_028350_MULTIPASS(state->rasterizer_discard)); 572 } 573 return rs; 574} 575 576static unsigned r600_tex_filter(unsigned filter, unsigned max_aniso) 577{ 578 if (filter == PIPE_TEX_FILTER_LINEAR) 579 return max_aniso > 1 ? V_03C000_SQ_TEX_XY_FILTER_ANISO_BILINEAR 580 : V_03C000_SQ_TEX_XY_FILTER_BILINEAR; 581 else 582 return max_aniso > 1 ? V_03C000_SQ_TEX_XY_FILTER_ANISO_POINT 583 : V_03C000_SQ_TEX_XY_FILTER_POINT; 584} 585 586static void *r600_create_sampler_state(struct pipe_context *ctx, 587 const struct pipe_sampler_state *state) 588{ 589 struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen; 590 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state); 591 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso 592 : state->max_anisotropy; 593 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso); 594 595 if (!ss) { 596 return NULL; 597 } 598 599 ss->seamless_cube_map = state->seamless_cube_map; 600 ss->border_color_use = sampler_state_needs_border_color(state); 601 602 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */ 603 ss->tex_sampler_words[0] = 604 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) | 605 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) | 606 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) | 607 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter, max_aniso)) | 608 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter, max_aniso)) | 609 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) | 610 S_03C000_MAX_ANISO_RATIO(max_aniso_ratio) | 611 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) | 612 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0); 613 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */ 614 ss->tex_sampler_words[1] = 615 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) | 616 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) | 617 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)); 618 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */ 619 ss->tex_sampler_words[2] = S_03C008_TYPE(1); 620 621 if (ss->border_color_use) { 622 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color)); 623 } 624 return ss; 625} 626 627static struct pipe_sampler_view * 628texture_buffer_sampler_view(struct r600_pipe_sampler_view *view, 629 unsigned width0, unsigned height0) 630 631{ 632 struct r600_texture *tmp = (struct r600_texture*)view->base.texture; 633 int stride = util_format_get_blocksize(view->base.format); 634 unsigned format, num_format, format_comp, endian; 635 uint64_t offset = view->base.u.buf.offset; 636 unsigned size = view->base.u.buf.size; 637 638 r600_vertex_data_type(view->base.format, 639 &format, &num_format, &format_comp, 640 &endian); 641 642 view->tex_resource = &tmp->resource; 643 view->skip_mip_address_reloc = true; 644 645 view->tex_resource_words[0] = offset; 646 view->tex_resource_words[1] = size - 1; 647 view->tex_resource_words[2] = S_038008_BASE_ADDRESS_HI(offset >> 32UL) | 648 S_038008_STRIDE(stride) | 649 S_038008_DATA_FORMAT(format) | 650 S_038008_NUM_FORMAT_ALL(num_format) | 651 S_038008_FORMAT_COMP_ALL(format_comp) | 652 S_038008_ENDIAN_SWAP(endian); 653 view->tex_resource_words[3] = 0; 654 /* 655 * in theory dword 4 is for number of elements, for use with resinfo, 656 * but it seems to utterly fail to work, the amd gpu shader analyser 657 * uses a const buffer to store the element sizes for buffer txq 658 */ 659 view->tex_resource_words[4] = 0; 660 view->tex_resource_words[5] = 0; 661 view->tex_resource_words[6] = S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_BUFFER); 662 return &view->base; 663} 664 665struct pipe_sampler_view * 666r600_create_sampler_view_custom(struct pipe_context *ctx, 667 struct pipe_resource *texture, 668 const struct pipe_sampler_view *state, 669 unsigned width_first_level, unsigned height_first_level) 670{ 671 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view); 672 struct r600_texture *tmp = (struct r600_texture*)texture; 673 unsigned format, endian; 674 uint32_t word4 = 0, yuv_format = 0, pitch = 0; 675 unsigned char swizzle[4], array_mode = 0; 676 unsigned width, height, depth, offset_level, last_level; 677 bool do_endian_swap = FALSE; 678 679 if (!view) 680 return NULL; 681 682 /* initialize base object */ 683 view->base = *state; 684 view->base.texture = NULL; 685 pipe_reference(NULL, &texture->reference); 686 view->base.texture = texture; 687 view->base.reference.count = 1; 688 view->base.context = ctx; 689 690 if (texture->target == PIPE_BUFFER) 691 return texture_buffer_sampler_view(view, texture->width0, 1); 692 693 swizzle[0] = state->swizzle_r; 694 swizzle[1] = state->swizzle_g; 695 swizzle[2] = state->swizzle_b; 696 swizzle[3] = state->swizzle_a; 697 698 if (R600_BIG_ENDIAN) 699 do_endian_swap = !tmp->db_compatible; 700 701 format = r600_translate_texformat(ctx->screen, state->format, 702 swizzle, 703 &word4, &yuv_format, do_endian_swap); 704 assert(format != ~0); 705 if (format == ~0) { 706 FREE(view); 707 return NULL; 708 } 709 710 if (state->format == PIPE_FORMAT_X24S8_UINT || 711 state->format == PIPE_FORMAT_S8X24_UINT || 712 state->format == PIPE_FORMAT_X32_S8X24_UINT || 713 state->format == PIPE_FORMAT_S8_UINT) 714 view->is_stencil_sampler = true; 715 716 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) { 717 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) { 718 FREE(view); 719 return NULL; 720 } 721 tmp = tmp->flushed_depth_texture; 722 } 723 724 endian = r600_colorformat_endian_swap(format, do_endian_swap); 725 726 offset_level = state->u.tex.first_level; 727 last_level = state->u.tex.last_level - offset_level; 728 width = width_first_level; 729 height = height_first_level; 730 depth = u_minify(texture->depth0, offset_level); 731 pitch = tmp->surface.u.legacy.level[offset_level].nblk_x * util_format_get_blockwidth(state->format); 732 733 if (texture->target == PIPE_TEXTURE_1D_ARRAY) { 734 height = 1; 735 depth = texture->array_size; 736 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) { 737 depth = texture->array_size; 738 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY) 739 depth = texture->array_size / 6; 740 741 switch (tmp->surface.u.legacy.level[offset_level].mode) { 742 default: 743 case RADEON_SURF_MODE_LINEAR_ALIGNED: 744 array_mode = V_038000_ARRAY_LINEAR_ALIGNED; 745 break; 746 case RADEON_SURF_MODE_1D: 747 array_mode = V_038000_ARRAY_1D_TILED_THIN1; 748 break; 749 case RADEON_SURF_MODE_2D: 750 array_mode = V_038000_ARRAY_2D_TILED_THIN1; 751 break; 752 } 753 754 view->tex_resource = &tmp->resource; 755 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) | 756 S_038000_TILE_MODE(array_mode) | 757 S_038000_TILE_TYPE(tmp->non_disp_tiling) | 758 S_038000_PITCH((pitch / 8) - 1) | 759 S_038000_TEX_WIDTH(width - 1)); 760 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) | 761 S_038004_TEX_DEPTH(depth - 1) | 762 S_038004_DATA_FORMAT(format)); 763 view->tex_resource_words[2] = tmp->surface.u.legacy.level[offset_level].offset_256B; 764 if (offset_level >= tmp->resource.b.b.last_level) { 765 view->tex_resource_words[3] = tmp->surface.u.legacy.level[offset_level].offset_256B; 766 } else { 767 view->tex_resource_words[3] = tmp->surface.u.legacy.level[offset_level + 1].offset_256B; 768 } 769 view->tex_resource_words[4] = (word4 | 770 S_038010_REQUEST_SIZE(1) | 771 S_038010_ENDIAN_SWAP(endian) | 772 S_038010_BASE_LEVEL(0)); 773 view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) | 774 S_038014_LAST_ARRAY(state->u.tex.last_layer)); 775 if (texture->nr_samples > 1) { 776 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */ 777 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples)); 778 } else { 779 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level); 780 } 781 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) | 782 S_038018_MAX_ANISO(4 /* max 16 samples */)); 783 return &view->base; 784} 785 786static struct pipe_sampler_view * 787r600_create_sampler_view(struct pipe_context *ctx, 788 struct pipe_resource *tex, 789 const struct pipe_sampler_view *state) 790{ 791 return r600_create_sampler_view_custom(ctx, tex, state, 792 u_minify(tex->width0, state->u.tex.first_level), 793 u_minify(tex->height0, state->u.tex.first_level)); 794} 795 796static void r600_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom) 797{ 798 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; 799 struct pipe_clip_state *state = &rctx->clip_state.state; 800 801 radeon_set_context_reg_seq(cs, R_028E20_PA_CL_UCP0_X, 6*4); 802 radeon_emit_array(cs, (unsigned*)state, 6*4); 803} 804 805static void r600_set_polygon_stipple(struct pipe_context *ctx, 806 const struct pipe_poly_stipple *state) 807{ 808} 809 810static void r600_init_color_surface(struct r600_context *rctx, 811 struct r600_surface *surf, 812 bool force_cmask_fmask) 813{ 814 struct r600_screen *rscreen = rctx->screen; 815 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture; 816 unsigned level = surf->base.u.tex.level; 817 unsigned pitch, slice; 818 unsigned color_info; 819 unsigned color_view; 820 unsigned format, swap, ntype, endian; 821 unsigned offset; 822 const struct util_format_description *desc; 823 int i; 824 bool blend_bypass = 0, blend_clamp = 0, do_endian_swap = FALSE; 825 826 if (rtex->db_compatible && !r600_can_sample_zs(rtex, false)) { 827 r600_init_flushed_depth_texture(&rctx->b.b, surf->base.texture, NULL); 828 rtex = rtex->flushed_depth_texture; 829 assert(rtex); 830 } 831 832 offset = (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256; 833 color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) | 834 S_028080_SLICE_MAX(surf->base.u.tex.last_layer); 835 836 pitch = rtex->surface.u.legacy.level[level].nblk_x / 8 - 1; 837 slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64; 838 if (slice) { 839 slice = slice - 1; 840 } 841 color_info = 0; 842 switch (rtex->surface.u.legacy.level[level].mode) { 843 default: 844 case RADEON_SURF_MODE_LINEAR_ALIGNED: 845 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED); 846 break; 847 case RADEON_SURF_MODE_1D: 848 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1); 849 break; 850 case RADEON_SURF_MODE_2D: 851 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1); 852 break; 853 } 854 855 desc = util_format_description(surf->base.format); 856 857 for (i = 0; i < 4; i++) { 858 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { 859 break; 860 } 861 } 862 863 ntype = V_0280A0_NUMBER_UNORM; 864 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) 865 ntype = V_0280A0_NUMBER_SRGB; 866 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) { 867 if (desc->channel[i].normalized) 868 ntype = V_0280A0_NUMBER_SNORM; 869 else if (desc->channel[i].pure_integer) 870 ntype = V_0280A0_NUMBER_SINT; 871 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) { 872 if (desc->channel[i].normalized) 873 ntype = V_0280A0_NUMBER_UNORM; 874 else if (desc->channel[i].pure_integer) 875 ntype = V_0280A0_NUMBER_UINT; 876 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) { 877 ntype = V_0280A0_NUMBER_FLOAT; 878 } 879 880 if (R600_BIG_ENDIAN) 881 do_endian_swap = !rtex->db_compatible; 882 883 format = r600_translate_colorformat(rctx->b.gfx_level, surf->base.format, 884 do_endian_swap); 885 assert(format != ~0); 886 887 swap = r600_translate_colorswap(surf->base.format, do_endian_swap); 888 assert(swap != ~0); 889 890 endian = r600_colorformat_endian_swap(format, do_endian_swap); 891 892 /* blend clamp should be set for all NORM/SRGB types */ 893 if (ntype == V_0280A0_NUMBER_UNORM || ntype == V_0280A0_NUMBER_SNORM || 894 ntype == V_0280A0_NUMBER_SRGB) 895 blend_clamp = 1; 896 897 /* set blend bypass according to docs if SINT/UINT or 898 8/24 COLOR variants */ 899 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT || 900 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 || 901 format == V_0280A0_COLOR_X24_8_32_FLOAT) { 902 blend_clamp = 0; 903 blend_bypass = 1; 904 } 905 906 surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT; 907 908 color_info |= S_0280A0_FORMAT(format) | 909 S_0280A0_COMP_SWAP(swap) | 910 S_0280A0_BLEND_BYPASS(blend_bypass) | 911 S_0280A0_BLEND_CLAMP(blend_clamp) | 912 S_0280A0_SIMPLE_FLOAT(1) | 913 S_0280A0_NUMBER_TYPE(ntype) | 914 S_0280A0_ENDIAN(endian); 915 916 /* EXPORT_NORM is an optimization that can be enabled for better 917 * performance in certain cases 918 */ 919 if (rctx->b.gfx_level == R600) { 920 /* EXPORT_NORM can be enabled if: 921 * - 11-bit or smaller UNORM/SNORM/SRGB 922 * - BLEND_CLAMP is enabled 923 * - BLEND_FLOAT32 is disabled 924 */ 925 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS && 926 (desc->channel[i].size < 12 && 927 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT && 928 ntype != V_0280A0_NUMBER_UINT && 929 ntype != V_0280A0_NUMBER_SINT) && 930 G_0280A0_BLEND_CLAMP(color_info) && 931 /* XXX this condition is always true since BLEND_FLOAT32 is never set (bug?). */ 932 !G_0280A0_BLEND_FLOAT32(color_info)) { 933 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM); 934 surf->export_16bpc = true; 935 } 936 } else { 937 /* EXPORT_NORM can be enabled if: 938 * - 11-bit or smaller UNORM/SNORM/SRGB 939 * - 16-bit or smaller FLOAT 940 */ 941 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS && 942 ((desc->channel[i].size < 12 && 943 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT && 944 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) || 945 (desc->channel[i].size < 17 && 946 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) { 947 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM); 948 surf->export_16bpc = true; 949 } 950 } 951 952 /* These might not always be initialized to zero. */ 953 surf->cb_color_base = offset >> 8; 954 surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) | 955 S_028060_SLICE_TILE_MAX(slice); 956 surf->cb_color_fmask = surf->cb_color_base; 957 surf->cb_color_cmask = surf->cb_color_base; 958 surf->cb_color_mask = 0; 959 960 r600_resource_reference(&surf->cb_buffer_cmask, &rtex->resource); 961 r600_resource_reference(&surf->cb_buffer_fmask, &rtex->resource); 962 963 if (rtex->cmask.size) { 964 surf->cb_color_cmask = rtex->cmask.offset >> 8; 965 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask.slice_tile_max); 966 967 if (rtex->fmask.size) { 968 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE); 969 surf->cb_color_fmask = rtex->fmask.offset >> 8; 970 surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(rtex->fmask.slice_tile_max); 971 } else { /* cmask only */ 972 color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE); 973 } 974 } else if (force_cmask_fmask) { 975 /* Allocate dummy FMASK and CMASK if they aren't allocated already. 976 * 977 * R6xx needs FMASK and CMASK for the destination buffer of color resolve, 978 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated, 979 * because it's not an MSAA buffer. 980 */ 981 struct r600_cmask_info cmask; 982 struct r600_fmask_info fmask; 983 984 r600_texture_get_cmask_info(&rscreen->b, rtex, &cmask); 985 r600_texture_get_fmask_info(&rscreen->b, rtex, 8, &fmask); 986 987 /* CMASK. */ 988 if (!rctx->dummy_cmask || 989 rctx->dummy_cmask->b.b.width0 < cmask.size || 990 (1 << rctx->dummy_cmask->buf->alignment_log2) % cmask.alignment != 0) { 991 struct pipe_transfer *transfer; 992 void *ptr; 993 994 r600_resource_reference(&rctx->dummy_cmask, NULL); 995 rctx->dummy_cmask = (struct r600_resource*) 996 r600_aligned_buffer_create(&rscreen->b.b, 0, 997 PIPE_USAGE_DEFAULT, 998 cmask.size, cmask.alignment); 999 1000 if (unlikely(!rctx->dummy_cmask)) { 1001 surf->color_initialized = false; 1002 return; 1003 } 1004 1005 /* Set the contents to 0xCC. */ 1006 ptr = pipe_buffer_map(&rctx->b.b, &rctx->dummy_cmask->b.b, PIPE_MAP_WRITE, &transfer); 1007 memset(ptr, 0xCC, cmask.size); 1008 pipe_buffer_unmap(&rctx->b.b, transfer); 1009 } 1010 r600_resource_reference(&surf->cb_buffer_cmask, rctx->dummy_cmask); 1011 1012 /* FMASK. */ 1013 if (!rctx->dummy_fmask || 1014 rctx->dummy_fmask->b.b.width0 < fmask.size || 1015 (1 << rctx->dummy_fmask->buf->alignment_log2) % fmask.alignment != 0) { 1016 r600_resource_reference(&rctx->dummy_fmask, NULL); 1017 rctx->dummy_fmask = (struct r600_resource*) 1018 r600_aligned_buffer_create(&rscreen->b.b, 0, 1019 PIPE_USAGE_DEFAULT, 1020 fmask.size, fmask.alignment); 1021 1022 if (unlikely(!rctx->dummy_fmask)) { 1023 surf->color_initialized = false; 1024 return; 1025 } 1026 } 1027 r600_resource_reference(&surf->cb_buffer_fmask, rctx->dummy_fmask); 1028 1029 /* Init the registers. */ 1030 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE); 1031 surf->cb_color_cmask = 0; 1032 surf->cb_color_fmask = 0; 1033 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) | 1034 S_028100_FMASK_TILE_MAX(fmask.slice_tile_max); 1035 } 1036 1037 surf->cb_color_info = color_info; 1038 surf->cb_color_view = color_view; 1039 surf->color_initialized = true; 1040} 1041 1042static void r600_init_depth_surface(struct r600_context *rctx, 1043 struct r600_surface *surf) 1044{ 1045 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture; 1046 unsigned level, pitch, slice, format, offset, array_mode; 1047 1048 level = surf->base.u.tex.level; 1049 offset = (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256; 1050 pitch = rtex->surface.u.legacy.level[level].nblk_x / 8 - 1; 1051 slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64; 1052 if (slice) { 1053 slice = slice - 1; 1054 } 1055 switch (rtex->surface.u.legacy.level[level].mode) { 1056 case RADEON_SURF_MODE_2D: 1057 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1; 1058 break; 1059 case RADEON_SURF_MODE_1D: 1060 case RADEON_SURF_MODE_LINEAR_ALIGNED: 1061 default: 1062 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1; 1063 break; 1064 } 1065 1066 format = r600_translate_dbformat(surf->base.format); 1067 assert(format != ~0); 1068 1069 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format); 1070 surf->db_depth_base = offset >> 8; 1071 surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) | 1072 S_028004_SLICE_MAX(surf->base.u.tex.last_layer); 1073 surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice); 1074 surf->db_prefetch_limit = (rtex->surface.u.legacy.level[level].nblk_y / 8) - 1; 1075 1076 if (r600_htile_enabled(rtex, level)) { 1077 surf->db_htile_data_base = rtex->htile_offset >> 8; 1078 surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) | 1079 S_028D24_HTILE_HEIGHT(1) | 1080 S_028D24_FULL_CACHE(1); 1081 /* preload is not working properly on r6xx/r7xx */ 1082 surf->db_depth_info |= S_028010_TILE_SURFACE_ENABLE(1); 1083 } 1084 1085 surf->depth_initialized = true; 1086} 1087 1088static void r600_set_framebuffer_state(struct pipe_context *ctx, 1089 const struct pipe_framebuffer_state *state) 1090{ 1091 struct r600_context *rctx = (struct r600_context *)ctx; 1092 struct r600_surface *surf; 1093 struct r600_texture *rtex; 1094 unsigned i; 1095 uint32_t target_mask = 0; 1096 1097 /* Flush TC when changing the framebuffer state, because the only 1098 * client not using TC that can change textures is the framebuffer. 1099 * Other places don't typically have to flush TC. 1100 */ 1101 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | 1102 R600_CONTEXT_FLUSH_AND_INV | 1103 R600_CONTEXT_FLUSH_AND_INV_CB | 1104 R600_CONTEXT_FLUSH_AND_INV_CB_META | 1105 R600_CONTEXT_FLUSH_AND_INV_DB | 1106 R600_CONTEXT_FLUSH_AND_INV_DB_META | 1107 R600_CONTEXT_INV_TEX_CACHE; 1108 1109 /* Set the new state. */ 1110 util_copy_framebuffer_state(&rctx->framebuffer.state, state); 1111 1112 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0; 1113 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] && 1114 util_format_is_pure_integer(state->cbufs[0]->format); 1115 rctx->framebuffer.compressed_cb_mask = 0; 1116 rctx->framebuffer.is_msaa_resolve = state->nr_cbufs == 2 && 1117 state->cbufs[0] && state->cbufs[1] && 1118 state->cbufs[0]->texture->nr_samples > 1 && 1119 state->cbufs[1]->texture->nr_samples <= 1; 1120 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state); 1121 1122 /* Colorbuffers. */ 1123 for (i = 0; i < state->nr_cbufs; i++) { 1124 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */ 1125 bool force_cmask_fmask = rctx->b.gfx_level == R600 && 1126 rctx->framebuffer.is_msaa_resolve && 1127 i == 1; 1128 1129 surf = (struct r600_surface*)state->cbufs[i]; 1130 if (!surf) 1131 continue; 1132 1133 rtex = (struct r600_texture*)surf->base.texture; 1134 r600_context_add_resource_size(ctx, state->cbufs[i]->texture); 1135 1136 target_mask |= (0xf << (i * 4)); 1137 1138 if (!surf->color_initialized || force_cmask_fmask) { 1139 r600_init_color_surface(rctx, surf, force_cmask_fmask); 1140 if (force_cmask_fmask) { 1141 /* re-initialize later without compression */ 1142 surf->color_initialized = false; 1143 } 1144 } 1145 1146 if (!surf->export_16bpc) { 1147 rctx->framebuffer.export_16bpc = false; 1148 } 1149 1150 if (rtex->fmask.size) { 1151 rctx->framebuffer.compressed_cb_mask |= 1 << i; 1152 } 1153 } 1154 1155 /* Update alpha-test state dependencies. 1156 * Alpha-test is done on the first colorbuffer only. */ 1157 if (state->nr_cbufs) { 1158 bool alphatest_bypass = false; 1159 1160 surf = (struct r600_surface*)state->cbufs[0]; 1161 if (surf) { 1162 alphatest_bypass = surf->alphatest_bypass; 1163 } 1164 1165 if (rctx->alphatest_state.bypass != alphatest_bypass) { 1166 rctx->alphatest_state.bypass = alphatest_bypass; 1167 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom); 1168 } 1169 } 1170 1171 /* ZS buffer. */ 1172 if (state->zsbuf) { 1173 surf = (struct r600_surface*)state->zsbuf; 1174 1175 r600_context_add_resource_size(ctx, state->zsbuf->texture); 1176 1177 if (!surf->depth_initialized) { 1178 r600_init_depth_surface(rctx, surf); 1179 } 1180 1181 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) { 1182 rctx->poly_offset_state.zs_format = state->zsbuf->format; 1183 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom); 1184 } 1185 1186 if (rctx->db_state.rsurf != surf) { 1187 rctx->db_state.rsurf = surf; 1188 r600_mark_atom_dirty(rctx, &rctx->db_state.atom); 1189 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom); 1190 } 1191 } else if (rctx->db_state.rsurf) { 1192 rctx->db_state.rsurf = NULL; 1193 r600_mark_atom_dirty(rctx, &rctx->db_state.atom); 1194 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom); 1195 } 1196 1197 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs || 1198 rctx->cb_misc_state.bound_cbufs_target_mask != target_mask) { 1199 rctx->cb_misc_state.bound_cbufs_target_mask = target_mask; 1200 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs; 1201 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom); 1202 } 1203 1204 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) { 1205 rctx->alphatest_state.bypass = false; 1206 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom); 1207 } 1208 1209 /* Calculate the CS size. */ 1210 rctx->framebuffer.atom.num_dw = 1211 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/; 1212 1213 if (rctx->framebuffer.state.nr_cbufs) { 1214 rctx->framebuffer.atom.num_dw += 15 * rctx->framebuffer.state.nr_cbufs; 1215 rctx->framebuffer.atom.num_dw += 3 * (2 + rctx->framebuffer.state.nr_cbufs); 1216 } 1217 if (rctx->framebuffer.state.zsbuf) { 1218 rctx->framebuffer.atom.num_dw += 16; 1219 } else { 1220 rctx->framebuffer.atom.num_dw += 3; 1221 } 1222 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770) { 1223 rctx->framebuffer.atom.num_dw += 2; 1224 } 1225 1226 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom); 1227 1228 r600_set_sample_locations_constant_buffer(rctx); 1229 rctx->framebuffer.do_update_surf_dirtiness = true; 1230} 1231 1232static const uint32_t sample_locs_2x[] = { 1233 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4), 1234 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4), 1235}; 1236static const unsigned max_dist_2x = 4; 1237 1238static const uint32_t sample_locs_4x[] = { 1239 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6), 1240 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6), 1241}; 1242static const unsigned max_dist_4x = 6; 1243static const uint32_t sample_locs_8x[] = { 1244 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3), 1245 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7), 1246}; 1247static const unsigned max_dist_8x = 7; 1248 1249static void r600_get_sample_position(struct pipe_context *ctx, 1250 unsigned sample_count, 1251 unsigned sample_index, 1252 float *out_value) 1253{ 1254 int offset, index; 1255 struct { 1256 int idx:4; 1257 } val; 1258 switch (sample_count) { 1259 case 1: 1260 default: 1261 out_value[0] = out_value[1] = 0.5; 1262 break; 1263 case 2: 1264 offset = 4 * (sample_index * 2); 1265 val.idx = (sample_locs_2x[0] >> offset) & 0xf; 1266 out_value[0] = (float)(val.idx + 8) / 16.0f; 1267 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf; 1268 out_value[1] = (float)(val.idx + 8) / 16.0f; 1269 break; 1270 case 4: 1271 offset = 4 * (sample_index * 2); 1272 val.idx = (sample_locs_4x[0] >> offset) & 0xf; 1273 out_value[0] = (float)(val.idx + 8) / 16.0f; 1274 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf; 1275 out_value[1] = (float)(val.idx + 8) / 16.0f; 1276 break; 1277 case 8: 1278 offset = 4 * (sample_index % 4 * 2); 1279 index = (sample_index / 4); 1280 val.idx = (sample_locs_8x[index] >> offset) & 0xf; 1281 out_value[0] = (float)(val.idx + 8) / 16.0f; 1282 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf; 1283 out_value[1] = (float)(val.idx + 8) / 16.0f; 1284 break; 1285 } 1286} 1287 1288static void r600_emit_msaa_state(struct r600_context *rctx, int nr_samples) 1289{ 1290 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; 1291 unsigned max_dist = 0; 1292 1293 if (rctx->b.family == CHIP_R600) { 1294 switch (nr_samples) { 1295 default: 1296 nr_samples = 0; 1297 break; 1298 case 2: 1299 radeon_set_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]); 1300 max_dist = max_dist_2x; 1301 break; 1302 case 4: 1303 radeon_set_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]); 1304 max_dist = max_dist_4x; 1305 break; 1306 case 8: 1307 radeon_set_config_reg_seq(cs, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 2); 1308 radeon_emit(cs, sample_locs_8x[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */ 1309 radeon_emit(cs, sample_locs_8x[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */ 1310 max_dist = max_dist_8x; 1311 break; 1312 } 1313 } else { 1314 switch (nr_samples) { 1315 default: 1316 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2); 1317 radeon_emit(cs, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */ 1318 radeon_emit(cs, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */ 1319 nr_samples = 0; 1320 break; 1321 case 2: 1322 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2); 1323 radeon_emit(cs, sample_locs_2x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */ 1324 radeon_emit(cs, sample_locs_2x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */ 1325 max_dist = max_dist_2x; 1326 break; 1327 case 4: 1328 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2); 1329 radeon_emit(cs, sample_locs_4x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */ 1330 radeon_emit(cs, sample_locs_4x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */ 1331 max_dist = max_dist_4x; 1332 break; 1333 case 8: 1334 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2); 1335 radeon_emit(cs, sample_locs_8x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */ 1336 radeon_emit(cs, sample_locs_8x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */ 1337 max_dist = max_dist_8x; 1338 break; 1339 } 1340 } 1341 1342 if (nr_samples > 1) { 1343 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2); 1344 radeon_emit(cs, S_028C00_LAST_PIXEL(1) | 1345 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */ 1346 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) | 1347 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */ 1348 } else { 1349 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2); 1350 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */ 1351 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */ 1352 } 1353} 1354 1355static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom) 1356{ 1357 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; 1358 struct pipe_framebuffer_state *state = &rctx->framebuffer.state; 1359 unsigned nr_cbufs = state->nr_cbufs; 1360 struct r600_surface **cb = (struct r600_surface**)&state->cbufs[0]; 1361 unsigned i, sbu = 0; 1362 1363 /* Colorbuffers. */ 1364 radeon_set_context_reg_seq(cs, R_0280A0_CB_COLOR0_INFO, 8); 1365 for (i = 0; i < nr_cbufs; i++) { 1366 radeon_emit(cs, cb[i] ? cb[i]->cb_color_info : 0); 1367 } 1368 /* set CB_COLOR1_INFO for possible dual-src blending */ 1369 if (rctx->framebuffer.dual_src_blend && i == 1 && cb[0]) { 1370 radeon_emit(cs, cb[0]->cb_color_info); 1371 i++; 1372 } 1373 for (; i < 8; i++) { 1374 radeon_emit(cs, 0); 1375 } 1376 1377 if (nr_cbufs) { 1378 for (i = 0; i < nr_cbufs; i++) { 1379 unsigned reloc; 1380 1381 if (!cb[i]) 1382 continue; 1383 1384 /* COLOR_BASE */ 1385 radeon_set_context_reg(cs, R_028040_CB_COLOR0_BASE + i*4, cb[i]->cb_color_base); 1386 1387 reloc = radeon_add_to_buffer_list(&rctx->b, 1388 &rctx->b.gfx, 1389 (struct r600_resource*)cb[i]->base.texture, 1390 RADEON_USAGE_READWRITE | 1391 (cb[i]->base.texture->nr_samples > 1 ? 1392 RADEON_PRIO_COLOR_BUFFER_MSAA : 1393 RADEON_PRIO_COLOR_BUFFER)); 1394 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); 1395 radeon_emit(cs, reloc); 1396 1397 /* FMASK */ 1398 radeon_set_context_reg(cs, R_0280E0_CB_COLOR0_FRAG + i*4, cb[i]->cb_color_fmask); 1399 1400 reloc = radeon_add_to_buffer_list(&rctx->b, 1401 &rctx->b.gfx, 1402 cb[i]->cb_buffer_fmask, 1403 RADEON_USAGE_READWRITE | 1404 (cb[i]->base.texture->nr_samples > 1 ? 1405 RADEON_PRIO_COLOR_BUFFER_MSAA : 1406 RADEON_PRIO_COLOR_BUFFER)); 1407 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); 1408 radeon_emit(cs, reloc); 1409 1410 /* CMASK */ 1411 radeon_set_context_reg(cs, R_0280C0_CB_COLOR0_TILE + i*4, cb[i]->cb_color_cmask); 1412 1413 reloc = radeon_add_to_buffer_list(&rctx->b, 1414 &rctx->b.gfx, 1415 cb[i]->cb_buffer_cmask, 1416 RADEON_USAGE_READWRITE | 1417 (cb[i]->base.texture->nr_samples > 1 ? 1418 RADEON_PRIO_COLOR_BUFFER_MSAA : 1419 RADEON_PRIO_COLOR_BUFFER)); 1420 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); 1421 radeon_emit(cs, reloc); 1422 } 1423 1424 radeon_set_context_reg_seq(cs, R_028060_CB_COLOR0_SIZE, nr_cbufs); 1425 for (i = 0; i < nr_cbufs; i++) { 1426 radeon_emit(cs, cb[i] ? cb[i]->cb_color_size : 0); 1427 } 1428 1429 radeon_set_context_reg_seq(cs, R_028080_CB_COLOR0_VIEW, nr_cbufs); 1430 for (i = 0; i < nr_cbufs; i++) { 1431 radeon_emit(cs, cb[i] ? cb[i]->cb_color_view : 0); 1432 } 1433 1434 radeon_set_context_reg_seq(cs, R_028100_CB_COLOR0_MASK, nr_cbufs); 1435 for (i = 0; i < nr_cbufs; i++) { 1436 radeon_emit(cs, cb[i] ? cb[i]->cb_color_mask : 0); 1437 } 1438 1439 sbu |= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs); 1440 } 1441 1442 /* SURFACE_BASE_UPDATE */ 1443 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) { 1444 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0)); 1445 radeon_emit(cs, sbu); 1446 sbu = 0; 1447 } 1448 1449 /* Zbuffer. */ 1450 if (state->zsbuf) { 1451 struct r600_surface *surf = (struct r600_surface*)state->zsbuf; 1452 unsigned reloc = radeon_add_to_buffer_list(&rctx->b, 1453 &rctx->b.gfx, 1454 (struct r600_resource*)state->zsbuf->texture, 1455 RADEON_USAGE_READWRITE | 1456 (surf->base.texture->nr_samples > 1 ? 1457 RADEON_PRIO_DEPTH_BUFFER_MSAA : 1458 RADEON_PRIO_DEPTH_BUFFER)); 1459 1460 radeon_set_context_reg_seq(cs, R_028000_DB_DEPTH_SIZE, 2); 1461 radeon_emit(cs, surf->db_depth_size); /* R_028000_DB_DEPTH_SIZE */ 1462 radeon_emit(cs, surf->db_depth_view); /* R_028004_DB_DEPTH_VIEW */ 1463 radeon_set_context_reg_seq(cs, R_02800C_DB_DEPTH_BASE, 2); 1464 radeon_emit(cs, surf->db_depth_base); /* R_02800C_DB_DEPTH_BASE */ 1465 radeon_emit(cs, surf->db_depth_info); /* R_028010_DB_DEPTH_INFO */ 1466 1467 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); 1468 radeon_emit(cs, reloc); 1469 1470 radeon_set_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit); 1471 1472 sbu |= SURFACE_BASE_UPDATE_DEPTH; 1473 } else { 1474 radeon_set_context_reg(cs, R_028010_DB_DEPTH_INFO, S_028010_FORMAT(V_028010_DEPTH_INVALID)); 1475 } 1476 1477 /* SURFACE_BASE_UPDATE */ 1478 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) { 1479 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0)); 1480 radeon_emit(cs, sbu); 1481 sbu = 0; 1482 } 1483 1484 /* Framebuffer dimensions. */ 1485 radeon_set_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2); 1486 radeon_emit(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) | 1487 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */ 1488 radeon_emit(cs, S_028244_BR_X(state->width) | 1489 S_028244_BR_Y(state->height)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */ 1490 1491 if (rctx->framebuffer.is_msaa_resolve) { 1492 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1); 1493 } else { 1494 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This 1495 * will assure that the alpha-test will work even if there is 1496 * no colorbuffer bound. */ 1497 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1498 (1ull << MAX2(nr_cbufs, 1)) - 1); 1499 } 1500 1501 r600_emit_msaa_state(rctx, rctx->framebuffer.nr_samples); 1502} 1503 1504static void r600_set_min_samples(struct pipe_context *ctx, unsigned min_samples) 1505{ 1506 struct r600_context *rctx = (struct r600_context *)ctx; 1507 1508 if (rctx->ps_iter_samples == min_samples) 1509 return; 1510 1511 rctx->ps_iter_samples = min_samples; 1512 if (rctx->framebuffer.nr_samples > 1) { 1513 r600_mark_atom_dirty(rctx, &rctx->rasterizer_state.atom); 1514 if (rctx->b.gfx_level == R600) 1515 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom); 1516 } 1517} 1518 1519static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom) 1520{ 1521 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; 1522 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom; 1523 1524 if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) { 1525 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2); 1526 if (rctx->b.gfx_level == R600) { 1527 radeon_emit(cs, 0xff); /* R_028238_CB_TARGET_MASK */ 1528 radeon_emit(cs, 0xff); /* R_02823C_CB_SHADER_MASK */ 1529 } else { 1530 radeon_emit(cs, 0xf); /* R_028238_CB_TARGET_MASK */ 1531 radeon_emit(cs, 0xf); /* R_02823C_CB_SHADER_MASK */ 1532 } 1533 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control); 1534 } else { 1535 unsigned fb_colormask = a->bound_cbufs_target_mask; 1536 unsigned ps_colormask = a->ps_color_export_mask; 1537 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1; 1538 1539 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2); 1540 radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */ 1541 /* Always enable the first color output to make sure alpha-test works even without one. */ 1542 radeon_emit(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */ 1543 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, 1544 a->cb_color_control | 1545 S_028808_MULTIWRITE_ENABLE(multiwrite)); 1546 } 1547} 1548 1549static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom) 1550{ 1551 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; 1552 struct r600_db_state *a = (struct r600_db_state*)atom; 1553 1554 if (a->rsurf && a->rsurf->db_htile_surface) { 1555 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture; 1556 unsigned reloc_idx; 1557 1558 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value)); 1559 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface); 1560 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base); 1561 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, &rtex->resource, 1562 RADEON_USAGE_READWRITE | RADEON_PRIO_SEPARATE_META); 1563 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); 1564 radeon_emit(cs, reloc_idx); 1565 } else { 1566 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, 0); 1567 } 1568} 1569 1570static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom) 1571{ 1572 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; 1573 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom; 1574 unsigned db_render_control = 0; 1575 unsigned db_render_override = 1576 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) | 1577 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE); 1578 1579 if (rctx->b.gfx_level >= R700) { 1580 switch (a->ps_conservative_z) { 1581 default: /* fall through */ 1582 case TGSI_FS_DEPTH_LAYOUT_ANY: 1583 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_ANY_Z); 1584 break; 1585 case TGSI_FS_DEPTH_LAYOUT_GREATER: 1586 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_GREATER_THAN_Z); 1587 break; 1588 case TGSI_FS_DEPTH_LAYOUT_LESS: 1589 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_LESS_THAN_Z); 1590 break; 1591 } 1592 } 1593 1594 if (rctx->b.num_occlusion_queries > 0 && 1595 !a->occlusion_queries_disabled) { 1596 if (rctx->b.gfx_level >= R700) { 1597 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1); 1598 } 1599 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1); 1600 } else { 1601 db_render_control |= S_028D0C_ZPASS_INCREMENT_DISABLE(1); 1602 } 1603 1604 if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_surface) { 1605 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */ 1606 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_OFF); 1607 /* This is to fix a lockup when hyperz and alpha test are enabled at 1608 * the same time somehow GPU get confuse on which order to pick for 1609 * z test 1610 */ 1611 if (rctx->alphatest_state.sx_alpha_test_control) { 1612 db_render_override |= S_028D10_FORCE_SHADER_Z_ORDER(1); 1613 } 1614 } else { 1615 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE); 1616 } 1617 if (rctx->b.gfx_level == R600 && rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0) { 1618 /* sample shading and hyperz causes lockups on R6xx chips */ 1619 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE); 1620 } 1621 if (a->flush_depthstencil_through_cb) { 1622 assert(a->copy_depth || a->copy_stencil); 1623 1624 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) | 1625 S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) | 1626 S_028D0C_COPY_CENTROID(1) | 1627 S_028D0C_COPY_SAMPLE(a->copy_sample); 1628 1629 if (rctx->b.gfx_level == R600) 1630 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1); 1631 1632 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 || 1633 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635) 1634 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE); 1635 } else if (a->flush_depth_inplace || a->flush_stencil_inplace) { 1636 db_render_control |= S_028D0C_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) | 1637 S_028D0C_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace); 1638 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1); 1639 } 1640 if (a->htile_clear) { 1641 db_render_control |= S_028D0C_DEPTH_CLEAR_ENABLE(1); 1642 } 1643 1644 /* RV770 workaround for a hang with 8x MSAA. */ 1645 if (rctx->b.family == CHIP_RV770 && a->log_samples == 3) { 1646 db_render_override |= S_028D10_MAX_TILES_IN_DTT(6); 1647 } 1648 1649 radeon_set_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2); 1650 radeon_emit(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */ 1651 radeon_emit(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */ 1652 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control); 1653} 1654 1655static void r600_emit_config_state(struct r600_context *rctx, struct r600_atom *atom) 1656{ 1657 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; 1658 struct r600_config_state *a = (struct r600_config_state*)atom; 1659 1660 radeon_set_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1); 1661 radeon_set_config_reg(cs, R_008C08_SQ_GPR_RESOURCE_MGMT_2, a->sq_gpr_resource_mgmt_2); 1662} 1663 1664static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom) 1665{ 1666 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; 1667 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask; 1668 1669 while (dirty_mask) { 1670 struct pipe_vertex_buffer *vb; 1671 struct r600_resource *rbuffer; 1672 unsigned offset; 1673 unsigned buffer_index = u_bit_scan(&dirty_mask); 1674 1675 vb = &rctx->vertex_buffer_state.vb[buffer_index]; 1676 rbuffer = (struct r600_resource*)vb->buffer.resource; 1677 assert(rbuffer); 1678 1679 offset = vb->buffer_offset; 1680 1681 /* fetch resources start at index 320 (OFFSET_FS) */ 1682 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0)); 1683 radeon_emit(cs, (R600_FETCH_CONSTANTS_OFFSET_FS + buffer_index) * 7); 1684 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */ 1685 radeon_emit(cs, rbuffer->b.b.width0 - offset - 1); /* RESOURCEi_WORD1 */ 1686 radeon_emit(cs, /* RESOURCEi_WORD2 */ 1687 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) | 1688 S_038008_STRIDE(vb->stride)); 1689 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */ 1690 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */ 1691 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */ 1692 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */ 1693 1694 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); 1695 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer, 1696 RADEON_USAGE_READ | RADEON_PRIO_VERTEX_BUFFER)); 1697 } 1698} 1699 1700static void r600_emit_constant_buffers(struct r600_context *rctx, 1701 struct r600_constbuf_state *state, 1702 unsigned buffer_id_base, 1703 unsigned reg_alu_constbuf_size, 1704 unsigned reg_alu_const_cache) 1705{ 1706 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; 1707 uint32_t dirty_mask = state->dirty_mask; 1708 1709 while (dirty_mask) { 1710 struct pipe_constant_buffer *cb; 1711 struct r600_resource *rbuffer; 1712 unsigned offset; 1713 unsigned buffer_index = ffs(dirty_mask) - 1; 1714 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER); 1715 cb = &state->cb[buffer_index]; 1716 rbuffer = (struct r600_resource*)cb->buffer; 1717 assert(rbuffer); 1718 1719 offset = cb->buffer_offset; 1720 1721 if (!gs_ring_buffer) { 1722 assert(buffer_index < R600_MAX_HW_CONST_BUFFERS); 1723 radeon_set_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4, 1724 DIV_ROUND_UP(cb->buffer_size, 256)); 1725 radeon_set_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8); 1726 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); 1727 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer, 1728 RADEON_USAGE_READ | RADEON_PRIO_CONST_BUFFER)); 1729 } 1730 1731 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0)); 1732 radeon_emit(cs, (buffer_id_base + buffer_index) * 7); 1733 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */ 1734 radeon_emit(cs, cb->buffer_size - 1); /* RESOURCEi_WORD1 */ 1735 radeon_emit(cs, /* RESOURCEi_WORD2 */ 1736 S_038008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) | 1737 S_038008_STRIDE(gs_ring_buffer ? 4 : 16)); 1738 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */ 1739 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */ 1740 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */ 1741 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */ 1742 1743 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); 1744 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer, 1745 RADEON_USAGE_READ | RADEON_PRIO_CONST_BUFFER)); 1746 1747 dirty_mask &= ~(1 << buffer_index); 1748 } 1749 state->dirty_mask = 0; 1750} 1751 1752static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom) 1753{ 1754 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], 1755 R600_FETCH_CONSTANTS_OFFSET_VS, 1756 R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 1757 R_028980_ALU_CONST_CACHE_VS_0); 1758} 1759 1760static void r600_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom) 1761{ 1762 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY], 1763 R600_FETCH_CONSTANTS_OFFSET_GS, 1764 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 1765 R_0289C0_ALU_CONST_CACHE_GS_0); 1766} 1767 1768static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom) 1769{ 1770 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT], 1771 R600_FETCH_CONSTANTS_OFFSET_PS, 1772 R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 1773 R_028940_ALU_CONST_CACHE_PS_0); 1774} 1775 1776static void r600_emit_sampler_views(struct r600_context *rctx, 1777 struct r600_samplerview_state *state, 1778 unsigned resource_id_base) 1779{ 1780 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; 1781 uint32_t dirty_mask = state->dirty_mask; 1782 1783 while (dirty_mask) { 1784 struct r600_pipe_sampler_view *rview; 1785 unsigned resource_index = u_bit_scan(&dirty_mask); 1786 unsigned reloc; 1787 1788 rview = state->views[resource_index]; 1789 assert(rview); 1790 1791 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0)); 1792 radeon_emit(cs, (resource_id_base + resource_index) * 7); 1793 radeon_emit_array(cs, rview->tex_resource_words, 7); 1794 1795 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource, 1796 RADEON_USAGE_READ | 1797 r600_get_sampler_view_priority(rview->tex_resource)); 1798 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); 1799 radeon_emit(cs, reloc); 1800 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); 1801 radeon_emit(cs, reloc); 1802 } 1803 state->dirty_mask = 0; 1804} 1805 1806 1807static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom) 1808{ 1809 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, R600_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS); 1810} 1811 1812static void r600_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom) 1813{ 1814 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, R600_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS); 1815} 1816 1817static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom) 1818{ 1819 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS); 1820} 1821 1822static void r600_emit_sampler_states(struct r600_context *rctx, 1823 struct r600_textures_info *texinfo, 1824 unsigned resource_id_base, 1825 unsigned border_color_reg) 1826{ 1827 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; 1828 uint32_t dirty_mask = texinfo->states.dirty_mask; 1829 1830 while (dirty_mask) { 1831 struct r600_pipe_sampler_state *rstate; 1832 struct r600_pipe_sampler_view *rview; 1833 unsigned i = u_bit_scan(&dirty_mask); 1834 1835 rstate = texinfo->states.states[i]; 1836 assert(rstate); 1837 rview = texinfo->views.views[i]; 1838 1839 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable 1840 * filtering between layers. 1841 */ 1842 enum pipe_texture_target target = PIPE_BUFFER; 1843 if (rview) 1844 target = rview->base.texture->target; 1845 if (target == PIPE_TEXTURE_1D_ARRAY || 1846 target == PIPE_TEXTURE_2D_ARRAY) { 1847 rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1); 1848 texinfo->is_array_sampler[i] = true; 1849 } else { 1850 rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE; 1851 texinfo->is_array_sampler[i] = false; 1852 } 1853 1854 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0)); 1855 radeon_emit(cs, (resource_id_base + i) * 3); 1856 radeon_emit_array(cs, rstate->tex_sampler_words, 3); 1857 1858 if (rstate->border_color_use) { 1859 unsigned offset; 1860 1861 offset = border_color_reg; 1862 offset += i * 16; 1863 radeon_set_config_reg_seq(cs, offset, 4); 1864 radeon_emit_array(cs, rstate->border_color.ui, 4); 1865 } 1866 } 1867 texinfo->states.dirty_mask = 0; 1868} 1869 1870static void r600_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom) 1871{ 1872 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED); 1873} 1874 1875static void r600_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom) 1876{ 1877 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED); 1878} 1879 1880static void r600_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom) 1881{ 1882 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED); 1883} 1884 1885static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom) 1886{ 1887 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; 1888 unsigned tmp; 1889 1890 tmp = S_009508_DISABLE_CUBE_ANISO(1) | 1891 S_009508_SYNC_GRADIENT(1) | 1892 S_009508_SYNC_WALKER(1) | 1893 S_009508_SYNC_ALIGNER(1); 1894 if (!rctx->seamless_cube_map.enabled) { 1895 tmp |= S_009508_DISABLE_CUBE_WRAP(1); 1896 } 1897 radeon_set_config_reg(cs, R_009508_TA_CNTL_AUX, tmp); 1898} 1899 1900static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a) 1901{ 1902 struct r600_sample_mask *s = (struct r600_sample_mask*)a; 1903 uint8_t mask = s->sample_mask; 1904 1905 radeon_set_context_reg(&rctx->b.gfx.cs, R_028C48_PA_SC_AA_MASK, 1906 mask | (mask << 8) | (mask << 16) | (mask << 24)); 1907} 1908 1909static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a) 1910{ 1911 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; 1912 struct r600_cso_state *state = (struct r600_cso_state*)a; 1913 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso; 1914 1915 if (!shader) 1916 return; 1917 1918 radeon_set_context_reg(cs, R_028894_SQ_PGM_START_FS, shader->offset >> 8); 1919 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); 1920 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer, 1921 RADEON_USAGE_READ | 1922 RADEON_PRIO_SHADER_BINARY)); 1923} 1924 1925static void r600_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a) 1926{ 1927 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; 1928 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a; 1929 1930 uint32_t v2 = 0, primid = 0; 1931 1932 if (rctx->vs_shader->current->shader.vs_as_gs_a) { 1933 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A); 1934 primid = 1; 1935 } 1936 1937 if (state->geom_enable) { 1938 uint32_t cut_val; 1939 1940 if (rctx->gs_shader->gs_max_out_vertices <= 128) 1941 cut_val = V_028A40_GS_CUT_128; 1942 else if (rctx->gs_shader->gs_max_out_vertices <= 256) 1943 cut_val = V_028A40_GS_CUT_256; 1944 else if (rctx->gs_shader->gs_max_out_vertices <= 512) 1945 cut_val = V_028A40_GS_CUT_512; 1946 else 1947 cut_val = V_028A40_GS_CUT_1024; 1948 1949 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) | 1950 S_028A40_CUT_MODE(cut_val); 1951 1952 if (rctx->gs_shader->current->shader.gs_prim_id_input) 1953 primid = 1; 1954 } 1955 1956 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2); 1957 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid); 1958} 1959 1960static void r600_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a) 1961{ 1962 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; 1963 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a; 1964 struct r600_resource *rbuffer; 1965 1966 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1)); 1967 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); 1968 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH)); 1969 1970 if (state->enable) { 1971 rbuffer =(struct r600_resource*)state->esgs_ring.buffer; 1972 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE, 0); 1973 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); 1974 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer, 1975 RADEON_USAGE_READWRITE | 1976 RADEON_PRIO_SHADER_RINGS)); 1977 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 1978 state->esgs_ring.buffer_size >> 8); 1979 1980 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer; 1981 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE, 0); 1982 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); 1983 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer, 1984 RADEON_USAGE_READWRITE | 1985 RADEON_PRIO_SHADER_RINGS)); 1986 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 1987 state->gsvs_ring.buffer_size >> 8); 1988 } else { 1989 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0); 1990 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0); 1991 } 1992 1993 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1)); 1994 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); 1995 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH)); 1996} 1997 1998/* Adjust GPR allocation on R6xx/R7xx */ 1999bool r600_adjust_gprs(struct r600_context *rctx) 2000{ 2001 unsigned num_gprs[R600_NUM_HW_STAGES]; 2002 unsigned new_gprs[R600_NUM_HW_STAGES]; 2003 unsigned cur_gprs[R600_NUM_HW_STAGES]; 2004 unsigned def_gprs[R600_NUM_HW_STAGES]; 2005 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs; 2006 unsigned max_gprs; 2007 unsigned tmp, tmp2; 2008 unsigned i; 2009 bool need_recalc = false, use_default = true; 2010 2011 /* hardware will reserve twice num_clause_temp_gprs */ 2012 max_gprs = def_num_clause_temp_gprs * 2; 2013 for (i = 0; i < R600_NUM_HW_STAGES; i++) { 2014 def_gprs[i] = rctx->default_gprs[i]; 2015 max_gprs += def_gprs[i]; 2016 } 2017 2018 cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1); 2019 cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1); 2020 cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2); 2021 cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2); 2022 2023 num_gprs[R600_HW_STAGE_PS] = rctx->ps_shader->current->shader.bc.ngpr; 2024 if (rctx->gs_shader) { 2025 num_gprs[R600_HW_STAGE_ES] = rctx->vs_shader->current->shader.bc.ngpr; 2026 num_gprs[R600_HW_STAGE_GS] = rctx->gs_shader->current->shader.bc.ngpr; 2027 num_gprs[R600_HW_STAGE_VS] = rctx->gs_shader->current->gs_copy_shader->shader.bc.ngpr; 2028 } else { 2029 num_gprs[R600_HW_STAGE_ES] = 0; 2030 num_gprs[R600_HW_STAGE_GS] = 0; 2031 num_gprs[R600_HW_STAGE_VS] = rctx->vs_shader->current->shader.bc.ngpr; 2032 } 2033 2034 for (i = 0; i < R600_NUM_HW_STAGES; i++) { 2035 new_gprs[i] = num_gprs[i]; 2036 if (new_gprs[i] > cur_gprs[i]) 2037 need_recalc = true; 2038 if (new_gprs[i] > def_gprs[i]) 2039 use_default = false; 2040 } 2041 2042 /* the sum of all SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS must <= to max_gprs */ 2043 if (!need_recalc) 2044 return true; 2045 2046 /* try to use switch back to default */ 2047 if (!use_default) { 2048 /* always privilege vs stage so that at worst we have the 2049 * pixel stage producing wrong output (not the vertex 2050 * stage) */ 2051 new_gprs[R600_HW_STAGE_PS] = max_gprs - def_num_clause_temp_gprs * 2; 2052 for (i = R600_HW_STAGE_VS; i < R600_NUM_HW_STAGES; i++) 2053 new_gprs[R600_HW_STAGE_PS] -= new_gprs[i]; 2054 } else { 2055 for (i = 0; i < R600_NUM_HW_STAGES; i++) 2056 new_gprs[i] = def_gprs[i]; 2057 } 2058 2059 /* SQ_PGM_RESOURCES_*.NUM_GPRS must always be program to a value <= 2060 * SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS otherwise the GPU will lockup 2061 * Also if a shader use more gpr than SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS 2062 * it will lockup. So in this case just discard the draw command 2063 * and don't change the current gprs repartitions. 2064 */ 2065 for (i = 0; i < R600_NUM_HW_STAGES; i++) { 2066 if (num_gprs[i] > new_gprs[i]) { 2067 R600_ERR("shaders require too many register (%d + %d + %d + %d) " 2068 "for a combined maximum of %d\n", 2069 num_gprs[R600_HW_STAGE_PS], num_gprs[R600_HW_STAGE_VS], num_gprs[R600_HW_STAGE_ES], num_gprs[R600_HW_STAGE_GS], max_gprs); 2070 return false; 2071 } 2072 } 2073 2074 /* in some case we endup recomputing the current value */ 2075 tmp = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) | 2076 S_008C04_NUM_VS_GPRS(new_gprs[R600_HW_STAGE_VS]) | 2077 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs); 2078 2079 tmp2 = S_008C08_NUM_ES_GPRS(new_gprs[R600_HW_STAGE_ES]) | 2080 S_008C08_NUM_GS_GPRS(new_gprs[R600_HW_STAGE_GS]); 2081 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp || rctx->config_state.sq_gpr_resource_mgmt_2 != tmp2) { 2082 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp; 2083 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp2; 2084 r600_mark_atom_dirty(rctx, &rctx->config_state.atom); 2085 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE; 2086 } 2087 return true; 2088} 2089 2090void r600_init_atom_start_cs(struct r600_context *rctx) 2091{ 2092 int ps_prio; 2093 int vs_prio; 2094 int gs_prio; 2095 int es_prio; 2096 int num_ps_gprs; 2097 int num_vs_gprs; 2098 int num_gs_gprs; 2099 int num_es_gprs; 2100 int num_temp_gprs; 2101 int num_ps_threads; 2102 int num_vs_threads; 2103 int num_gs_threads; 2104 int num_es_threads; 2105 int num_ps_stack_entries; 2106 int num_vs_stack_entries; 2107 int num_gs_stack_entries; 2108 int num_es_stack_entries; 2109 enum radeon_family family; 2110 struct r600_command_buffer *cb = &rctx->start_cs_cmd; 2111 uint32_t tmp, i; 2112 2113 r600_init_command_buffer(cb, 256); 2114 2115 /* R6xx requires this packet at the start of each command buffer */ 2116 if (rctx->b.gfx_level == R600) { 2117 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0)); 2118 r600_store_value(cb, 0); 2119 } 2120 /* All asics require this one */ 2121 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); 2122 r600_store_value(cb, 0x80000000); 2123 r600_store_value(cb, 0x80000000); 2124 2125 /* We're setting config registers here. */ 2126 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0)); 2127 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4)); 2128 2129 /* This enables pipeline stat & streamout queries. 2130 * They are only disabled by blits. 2131 */ 2132 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0)); 2133 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0)); 2134 2135 family = rctx->b.family; 2136 ps_prio = 0; 2137 vs_prio = 1; 2138 gs_prio = 2; 2139 es_prio = 3; 2140 switch (family) { 2141 case CHIP_R600: 2142 num_ps_gprs = 192; 2143 num_vs_gprs = 56; 2144 num_temp_gprs = 4; 2145 num_gs_gprs = 0; 2146 num_es_gprs = 0; 2147 num_ps_threads = 136; 2148 num_vs_threads = 48; 2149 num_gs_threads = 4; 2150 num_es_threads = 4; 2151 num_ps_stack_entries = 128; 2152 num_vs_stack_entries = 128; 2153 num_gs_stack_entries = 0; 2154 num_es_stack_entries = 0; 2155 break; 2156 case CHIP_RV630: 2157 case CHIP_RV635: 2158 num_ps_gprs = 84; 2159 num_vs_gprs = 36; 2160 num_temp_gprs = 4; 2161 num_gs_gprs = 0; 2162 num_es_gprs = 0; 2163 num_ps_threads = 144; 2164 num_vs_threads = 40; 2165 num_gs_threads = 4; 2166 num_es_threads = 4; 2167 num_ps_stack_entries = 40; 2168 num_vs_stack_entries = 40; 2169 num_gs_stack_entries = 32; 2170 num_es_stack_entries = 16; 2171 break; 2172 case CHIP_RV610: 2173 case CHIP_RV620: 2174 case CHIP_RS780: 2175 case CHIP_RS880: 2176 default: 2177 num_ps_gprs = 84; 2178 num_vs_gprs = 36; 2179 num_temp_gprs = 4; 2180 num_gs_gprs = 0; 2181 num_es_gprs = 0; 2182 /* use limits 40 VS and at least 16 ES/GS */ 2183 num_ps_threads = 120; 2184 num_vs_threads = 40; 2185 num_gs_threads = 16; 2186 num_es_threads = 16; 2187 num_ps_stack_entries = 40; 2188 num_vs_stack_entries = 40; 2189 num_gs_stack_entries = 32; 2190 num_es_stack_entries = 16; 2191 break; 2192 case CHIP_RV670: 2193 num_ps_gprs = 144; 2194 num_vs_gprs = 40; 2195 num_temp_gprs = 4; 2196 num_gs_gprs = 0; 2197 num_es_gprs = 0; 2198 num_ps_threads = 136; 2199 num_vs_threads = 48; 2200 num_gs_threads = 4; 2201 num_es_threads = 4; 2202 num_ps_stack_entries = 40; 2203 num_vs_stack_entries = 40; 2204 num_gs_stack_entries = 32; 2205 num_es_stack_entries = 16; 2206 break; 2207 case CHIP_RV770: 2208 num_ps_gprs = 130; 2209 num_vs_gprs = 56; 2210 num_temp_gprs = 4; 2211 num_gs_gprs = 31; 2212 num_es_gprs = 31; 2213 num_ps_threads = 180; 2214 num_vs_threads = 60; 2215 num_gs_threads = 4; 2216 num_es_threads = 4; 2217 num_ps_stack_entries = 128; 2218 num_vs_stack_entries = 128; 2219 num_gs_stack_entries = 128; 2220 num_es_stack_entries = 128; 2221 break; 2222 case CHIP_RV730: 2223 case CHIP_RV740: 2224 num_ps_gprs = 84; 2225 num_vs_gprs = 36; 2226 num_temp_gprs = 4; 2227 num_gs_gprs = 0; 2228 num_es_gprs = 0; 2229 num_ps_threads = 180; 2230 num_vs_threads = 60; 2231 num_gs_threads = 4; 2232 num_es_threads = 4; 2233 num_ps_stack_entries = 128; 2234 num_vs_stack_entries = 128; 2235 num_gs_stack_entries = 0; 2236 num_es_stack_entries = 0; 2237 break; 2238 case CHIP_RV710: 2239 num_ps_gprs = 192; 2240 num_vs_gprs = 56; 2241 num_temp_gprs = 4; 2242 num_gs_gprs = 0; 2243 num_es_gprs = 0; 2244 num_ps_threads = 136; 2245 num_vs_threads = 48; 2246 num_gs_threads = 4; 2247 num_es_threads = 4; 2248 num_ps_stack_entries = 128; 2249 num_vs_stack_entries = 128; 2250 num_gs_stack_entries = 0; 2251 num_es_stack_entries = 0; 2252 break; 2253 } 2254 2255 rctx->default_gprs[R600_HW_STAGE_PS] = num_ps_gprs; 2256 rctx->default_gprs[R600_HW_STAGE_VS] = num_vs_gprs; 2257 rctx->default_gprs[R600_HW_STAGE_GS] = 0; 2258 rctx->default_gprs[R600_HW_STAGE_ES] = 0; 2259 2260 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs; 2261 2262 /* SQ_CONFIG */ 2263 tmp = 0; 2264 switch (family) { 2265 case CHIP_RV610: 2266 case CHIP_RV620: 2267 case CHIP_RS780: 2268 case CHIP_RS880: 2269 case CHIP_RV710: 2270 break; 2271 default: 2272 tmp |= S_008C00_VC_ENABLE(1); 2273 break; 2274 } 2275 tmp |= S_008C00_DX9_CONSTS(0); 2276 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1); 2277 tmp |= S_008C00_PS_PRIO(ps_prio); 2278 tmp |= S_008C00_VS_PRIO(vs_prio); 2279 tmp |= S_008C00_GS_PRIO(gs_prio); 2280 tmp |= S_008C00_ES_PRIO(es_prio); 2281 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp); 2282 2283 /* SQ_GPR_RESOURCE_MGMT_2 */ 2284 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs); 2285 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs); 2286 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4); 2287 r600_store_value(cb, tmp); 2288 2289 /* SQ_THREAD_RESOURCE_MGMT */ 2290 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads); 2291 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads); 2292 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads); 2293 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads); 2294 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */ 2295 2296 /* SQ_STACK_RESOURCE_MGMT_1 */ 2297 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries); 2298 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries); 2299 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */ 2300 2301 /* SQ_STACK_RESOURCE_MGMT_2 */ 2302 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries); 2303 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries); 2304 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */ 2305 2306 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0); 2307 2308 if (rctx->b.gfx_level >= R700) { 2309 r600_store_context_reg(cb, R_028A50_VGT_ENHANCE, 4); 2310 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000); 2311 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0); 2312 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204); 2313 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0); 2314 } else { 2315 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0); 2316 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000); 2317 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204); 2318 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1); 2319 } 2320 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9); 2321 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */ 2322 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */ 2323 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */ 2324 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */ 2325 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */ 2326 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */ 2327 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */ 2328 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */ 2329 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */ 2330 2331 /* to avoid GPU doing any preloading of constant from random address */ 2332 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16); 2333 for (i = 0; i < 16; i++) 2334 r600_store_value(cb, 0); 2335 2336 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16); 2337 for (i = 0; i < 16; i++) 2338 r600_store_value(cb, 0); 2339 2340 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16); 2341 for (i = 0; i < 16; i++) 2342 r600_store_value(cb, 0); 2343 2344 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13); 2345 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */ 2346 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */ 2347 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */ 2348 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */ 2349 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */ 2350 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */ 2351 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */ 2352 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */ 2353 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */ 2354 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */ 2355 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */ 2356 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */ 2357 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */ 2358 2359 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0); 2360 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0); 2361 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0); 2362 2363 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2); 2364 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */ 2365 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */ 2366 2367 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0); 2368 2369 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0); 2370 2371 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0); 2372 2373 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3); 2374 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */ 2375 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */ 2376 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */ 2377 2378 r600_store_context_reg_seq(cb, R_028D28_DB_SRESULTS_COMPARE_STATE0, 3); 2379 r600_store_value(cb, 0); /* R_028D28_DB_SRESULTS_COMPARE_STATE0 */ 2380 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */ 2381 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */ 2382 2383 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0); 2384 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0); 2385 2386 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0); 2387 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF); 2388 2389 if (rctx->b.gfx_level >= R700) { 2390 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA); 2391 } 2392 2393 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4); 2394 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */ 2395 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */ 2396 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */ 2397 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */ 2398 2399 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2); 2400 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */ 2401 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */ 2402 2403 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2); 2404 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */ 2405 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */ 2406 2407 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 5); 2408 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */ 2409 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */ 2410 r600_store_value(cb, 0); /* R_0288D4_SQ_PGM_CF_OFFSET_GS */ 2411 r600_store_value(cb, 0); /* R_0288D8_SQ_PGM_CF_OFFSET_ES */ 2412 r600_store_value(cb, 0); /* R_0288DC_SQ_PGM_CF_OFFSET_FS */ 2413 2414 r600_store_context_reg(cb, R_0288E0_SQ_VTX_SEMANTIC_CLEAR, ~0); 2415 2416 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2); 2417 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */ 2418 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */ 2419 2420 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0); 2421 2422 if (rctx->b.gfx_level == R700) 2423 r600_store_context_reg(cb, R_028350_SX_MISC, 0); 2424 if (rctx->b.gfx_level == R700 && rctx->screen->b.has_streamout) 2425 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf)); 2426 2427 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0); 2428 if (rctx->screen->b.has_streamout) { 2429 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0); 2430 } 2431 2432 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF); 2433 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF); 2434 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (64 * 4), 0x1000FFF); 2435} 2436 2437void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader) 2438{ 2439 struct r600_context *rctx = (struct r600_context *)ctx; 2440 struct r600_command_buffer *cb = &shader->command_buffer; 2441 struct r600_shader *rshader = &shader->shader; 2442 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control; 2443 int pos_index = -1, face_index = -1, fixed_pt_position_index = -1; 2444 unsigned tmp, sid, ufi = 0; 2445 int need_linear = 0; 2446 unsigned z_export = 0, stencil_export = 0, mask_export = 0; 2447 2448 /* Pull any state we use out of rctx. Make sure that any additional 2449 * state added to this list is also checked in the caller in 2450 * r600_update_derived_state(). 2451 */ 2452 bool sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0; 2453 bool flatshade = rctx->rasterizer ? rctx->rasterizer->flatshade : 0; 2454 bool msaa = rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0; 2455 2456 if (!cb->buf) { 2457 r600_init_command_buffer(cb, 64); 2458 } else { 2459 cb->num_dw = 0; 2460 } 2461 2462 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, rshader->ninput); 2463 for (i = 0; i < rshader->ninput; i++) { 2464 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION) 2465 pos_index = i; 2466 if (rshader->input[i].name == TGSI_SEMANTIC_FACE && face_index == -1) 2467 face_index = i; 2468 if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEID) 2469 fixed_pt_position_index = i; 2470 2471 sid = rshader->input[i].spi_sid; 2472 2473 tmp = S_028644_SEMANTIC(sid); 2474 2475 /* D3D 9 behaviour. GL is undefined */ 2476 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR && rshader->input[i].sid == 0) 2477 tmp |= S_028644_DEFAULT_VAL(3); 2478 2479 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION || 2480 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT || 2481 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR && flatshade)) 2482 tmp |= S_028644_FLAT_SHADE(1); 2483 2484 if (rshader->input[i].name == TGSI_SEMANTIC_PCOORD || 2485 (rshader->input[i].name == TGSI_SEMANTIC_TEXCOORD && 2486 sprite_coord_enable & (1 << rshader->input[i].sid))) { 2487 tmp |= S_028644_PT_SPRITE_TEX(1); 2488 } 2489 2490 if (rshader->input[i].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) 2491 tmp |= S_028644_SEL_CENTROID(1); 2492 2493 if (rshader->input[i].interpolate_location == TGSI_INTERPOLATE_LOC_SAMPLE) 2494 tmp |= S_028644_SEL_SAMPLE(1); 2495 2496 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) { 2497 need_linear = 1; 2498 tmp |= S_028644_SEL_LINEAR(1); 2499 } 2500 2501 r600_store_value(cb, tmp); 2502 } 2503 2504 db_shader_control = 0; 2505 for (i = 0; i < rshader->noutput; i++) { 2506 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION) 2507 z_export = 1; 2508 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL) 2509 stencil_export = 1; 2510 if (rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK && msaa) 2511 mask_export = 1; 2512 } 2513 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export); 2514 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export); 2515 db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export); 2516 if (rshader->uses_kill) 2517 db_shader_control |= S_02880C_KILL_ENABLE(1); 2518 2519 exports_ps = 0; 2520 for (i = 0; i < rshader->noutput; i++) { 2521 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION || 2522 rshader->output[i].name == TGSI_SEMANTIC_STENCIL || 2523 rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) { 2524 exports_ps |= 1; 2525 } 2526 } 2527 num_cout = rshader->nr_ps_color_exports; 2528 exports_ps |= S_028854_EXPORT_COLORS(num_cout); 2529 if (!exports_ps) { 2530 /* always at least export 1 component per pixel */ 2531 exports_ps = 2; 2532 } 2533 2534 shader->nr_ps_color_outputs = num_cout; 2535 shader->ps_color_export_mask = rshader->ps_color_export_mask; 2536 2537 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) | 2538 S_0286CC_PERSP_GRADIENT_ENA(1)| 2539 S_0286CC_LINEAR_GRADIENT_ENA(need_linear); 2540 spi_input_z = 0; 2541 if (pos_index != -1) { 2542 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) | 2543 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) | 2544 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) | 2545 S_0286CC_BARYC_SAMPLE_CNTL(1)) | 2546 S_0286CC_POSITION_SAMPLE(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_SAMPLE); 2547 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1); 2548 } 2549 2550 spi_ps_in_control_1 = 0; 2551 if (face_index != -1) { 2552 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) | 2553 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr); 2554 } 2555 if (fixed_pt_position_index != -1) { 2556 spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) | 2557 S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr); 2558 } 2559 2560 /* HW bug in original R600 */ 2561 if (rctx->b.family == CHIP_R600) 2562 ufi = 1; 2563 2564 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2); 2565 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */ 2566 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */ 2567 2568 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z); 2569 2570 r600_store_context_reg_seq(cb, R_028850_SQ_PGM_RESOURCES_PS, 2); 2571 r600_store_value(cb, /* R_028850_SQ_PGM_RESOURCES_PS*/ 2572 S_028850_NUM_GPRS(rshader->bc.ngpr) | 2573 /* 2574 * docs are misleading about the dx10_clamp bit. This only affects 2575 * instructions using CLAMP dst modifier, in which case they will 2576 * return 0 with this set for a NaN (otherwise NaN). 2577 */ 2578 S_028850_DX10_CLAMP(1) | 2579 S_028850_STACK_SIZE(rshader->bc.nstack) | 2580 S_028850_UNCACHED_FIRST_INST(ufi)); 2581 r600_store_value(cb, exports_ps); /* R_028854_SQ_PGM_EXPORTS_PS */ 2582 2583 r600_store_context_reg(cb, R_028840_SQ_PGM_START_PS, 0); 2584 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */ 2585 2586 /* only set some bits here, the other bits are set in the dsa state */ 2587 shader->db_shader_control = db_shader_control; 2588 shader->ps_depth_export = z_export | stencil_export | mask_export; 2589 2590 shader->sprite_coord_enable = sprite_coord_enable; 2591 shader->flatshade = flatshade; 2592 shader->msaa = msaa; 2593} 2594 2595void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader) 2596{ 2597 struct r600_command_buffer *cb = &shader->command_buffer; 2598 struct r600_shader *rshader = &shader->shader; 2599 unsigned spi_vs_out_id[10] = {}; 2600 unsigned i, tmp, nparams = 0; 2601 2602 for (i = 0; i < rshader->noutput; i++) { 2603 if (rshader->output[i].spi_sid) { 2604 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8); 2605 spi_vs_out_id[nparams / 4] |= tmp; 2606 nparams++; 2607 } 2608 } 2609 2610 r600_init_command_buffer(cb, 32); 2611 2612 r600_store_context_reg_seq(cb, R_028614_SPI_VS_OUT_ID_0, 10); 2613 for (i = 0; i < 10; i++) { 2614 r600_store_value(cb, spi_vs_out_id[i]); 2615 } 2616 2617 /* Certain attributes (position, psize, etc.) don't count as params. 2618 * VS is required to export at least one param and r600_shader_from_tgsi() 2619 * takes care of adding a dummy export. 2620 */ 2621 if (nparams < 1) 2622 nparams = 1; 2623 2624 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG, 2625 S_0286C4_VS_EXPORT_COUNT(nparams - 1)); 2626 r600_store_context_reg(cb, R_028868_SQ_PGM_RESOURCES_VS, 2627 S_028868_NUM_GPRS(rshader->bc.ngpr) | 2628 S_028868_DX10_CLAMP(1) | 2629 S_028868_STACK_SIZE(rshader->bc.nstack)); 2630 if (rshader->vs_position_window_space) { 2631 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 2632 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1)); 2633 } else { 2634 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 2635 S_028818_VTX_W0_FMT(1) | 2636 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) | 2637 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) | 2638 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1)); 2639 2640 } 2641 r600_store_context_reg(cb, R_028858_SQ_PGM_START_VS, 0); 2642 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */ 2643 2644 shader->pa_cl_vs_out_cntl = 2645 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) | 2646 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) | 2647 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) | 2648 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) | 2649 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) | 2650 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer) | 2651 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport); 2652} 2653 2654#define RV610_GSVS_ALIGN 32 2655#define R600_GSVS_ALIGN 16 2656 2657void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader) 2658{ 2659 struct r600_context *rctx = (struct r600_context *)ctx; 2660 struct r600_command_buffer *cb = &shader->command_buffer; 2661 struct r600_shader *rshader = &shader->shader; 2662 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader; 2663 unsigned gsvs_itemsize = 2664 (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2; 2665 2666 /* some r600s needs gsvs itemsize aligned to cacheline size 2667 this was fixed in rs780 and above. */ 2668 switch (rctx->b.family) { 2669 case CHIP_RV610: 2670 gsvs_itemsize = align(gsvs_itemsize, RV610_GSVS_ALIGN); 2671 break; 2672 case CHIP_R600: 2673 case CHIP_RV630: 2674 case CHIP_RV670: 2675 case CHIP_RV620: 2676 case CHIP_RV635: 2677 gsvs_itemsize = align(gsvs_itemsize, R600_GSVS_ALIGN); 2678 break; 2679 default: 2680 break; 2681 } 2682 2683 r600_init_command_buffer(cb, 64); 2684 2685 /* VGT_GS_MODE is written by r600_emit_shader_stages */ 2686 r600_store_context_reg(cb, R_028AB8_VGT_VTX_CNT_EN, 1); 2687 2688 if (rctx->b.gfx_level >= R700) { 2689 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT, 2690 S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices)); 2691 } 2692 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE, 2693 r600_conv_prim_to_gs_out(shader->selector->gs_output_prim)); 2694 2695 r600_store_context_reg(cb, R_0288C8_SQ_GS_VERT_ITEMSIZE, 2696 cp_shader->ring_item_sizes[0] >> 2); 2697 2698 r600_store_context_reg(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 2699 (rshader->ring_item_sizes[0]) >> 2); 2700 2701 r600_store_context_reg(cb, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 2702 gsvs_itemsize); 2703 2704 /* FIXME calculate these values somehow ??? */ 2705 r600_store_config_reg_seq(cb, R_0088C8_VGT_GS_PER_ES, 2); 2706 r600_store_value(cb, 0x80); /* GS_PER_ES */ 2707 r600_store_value(cb, 0x100); /* ES_PER_GS */ 2708 r600_store_config_reg_seq(cb, R_0088E8_VGT_GS_PER_VS, 1); 2709 r600_store_value(cb, 0x2); /* GS_PER_VS */ 2710 2711 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_GS, 2712 S_02887C_NUM_GPRS(rshader->bc.ngpr) | 2713 S_02887C_DX10_CLAMP(1) | 2714 S_02887C_STACK_SIZE(rshader->bc.nstack)); 2715 r600_store_context_reg(cb, R_02886C_SQ_PGM_START_GS, 0); 2716 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */ 2717} 2718 2719void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader) 2720{ 2721 struct r600_command_buffer *cb = &shader->command_buffer; 2722 struct r600_shader *rshader = &shader->shader; 2723 2724 r600_init_command_buffer(cb, 32); 2725 2726 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES, 2727 S_028890_NUM_GPRS(rshader->bc.ngpr) | 2728 S_028890_DX10_CLAMP(1) | 2729 S_028890_STACK_SIZE(rshader->bc.nstack)); 2730 r600_store_context_reg(cb, R_028880_SQ_PGM_START_ES, 0); 2731 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */ 2732} 2733 2734 2735void *r600_create_resolve_blend(struct r600_context *rctx) 2736{ 2737 struct pipe_blend_state blend; 2738 unsigned i; 2739 2740 memset(&blend, 0, sizeof(blend)); 2741 blend.independent_blend_enable = true; 2742 for (i = 0; i < 2; i++) { 2743 blend.rt[i].colormask = 0xf; 2744 blend.rt[i].blend_enable = 1; 2745 blend.rt[i].rgb_func = PIPE_BLEND_ADD; 2746 blend.rt[i].alpha_func = PIPE_BLEND_ADD; 2747 blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO; 2748 blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO; 2749 blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO; 2750 blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO; 2751 } 2752 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX); 2753} 2754 2755void *r700_create_resolve_blend(struct r600_context *rctx) 2756{ 2757 struct pipe_blend_state blend; 2758 2759 memset(&blend, 0, sizeof(blend)); 2760 blend.independent_blend_enable = true; 2761 blend.rt[0].colormask = 0xf; 2762 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX); 2763} 2764 2765void *r600_create_decompress_blend(struct r600_context *rctx) 2766{ 2767 struct pipe_blend_state blend; 2768 2769 memset(&blend, 0, sizeof(blend)); 2770 blend.independent_blend_enable = true; 2771 blend.rt[0].colormask = 0xf; 2772 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_EXPAND_SAMPLES); 2773} 2774 2775void *r600_create_db_flush_dsa(struct r600_context *rctx) 2776{ 2777 struct pipe_depth_stencil_alpha_state dsa; 2778 boolean quirk = false; 2779 2780 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 || 2781 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635) 2782 quirk = true; 2783 2784 memset(&dsa, 0, sizeof(dsa)); 2785 2786 if (quirk) { 2787 dsa.depth_enabled = 1; 2788 dsa.depth_func = PIPE_FUNC_LEQUAL; 2789 dsa.stencil[0].enabled = 1; 2790 dsa.stencil[0].func = PIPE_FUNC_ALWAYS; 2791 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP; 2792 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR; 2793 dsa.stencil[0].writemask = 0xff; 2794 } 2795 2796 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa); 2797} 2798 2799void r600_update_db_shader_control(struct r600_context * rctx) 2800{ 2801 bool dual_export; 2802 unsigned db_shader_control; 2803 uint8_t ps_conservative_z; 2804 2805 if (!rctx->ps_shader) { 2806 return; 2807 } 2808 2809 dual_export = rctx->framebuffer.export_16bpc && 2810 !rctx->ps_shader->current->ps_depth_export; 2811 2812 db_shader_control = rctx->ps_shader->current->db_shader_control | 2813 S_02880C_DUAL_EXPORT_ENABLE(dual_export); 2814 2815 ps_conservative_z = rctx->ps_shader->current->shader.ps_conservative_z; 2816 2817 /* When alpha test is enabled we can't trust the hw to make the proper 2818 * decision on the order in which ztest should be run related to fragment 2819 * shader execution. 2820 * 2821 * If alpha test is enabled perform z test after fragment. RE_Z (early 2822 * z test but no write to the zbuffer) seems to cause lockup on r6xx/r7xx 2823 */ 2824 if (rctx->alphatest_state.sx_alpha_test_control) { 2825 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z); 2826 } else { 2827 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z); 2828 } 2829 2830 if (db_shader_control != rctx->db_misc_state.db_shader_control || 2831 ps_conservative_z != rctx->db_misc_state.ps_conservative_z) { 2832 rctx->db_misc_state.db_shader_control = db_shader_control; 2833 rctx->db_misc_state.ps_conservative_z = ps_conservative_z; 2834 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom); 2835 } 2836} 2837 2838static inline unsigned r600_array_mode(unsigned mode) 2839{ 2840 switch (mode) { 2841 default: 2842 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_0280A0_ARRAY_LINEAR_ALIGNED; 2843 break; 2844 case RADEON_SURF_MODE_1D: return V_0280A0_ARRAY_1D_TILED_THIN1; 2845 break; 2846 case RADEON_SURF_MODE_2D: return V_0280A0_ARRAY_2D_TILED_THIN1; 2847 } 2848} 2849 2850static boolean r600_dma_copy_tile(struct r600_context *rctx, 2851 struct pipe_resource *dst, 2852 unsigned dst_level, 2853 unsigned dst_x, 2854 unsigned dst_y, 2855 unsigned dst_z, 2856 struct pipe_resource *src, 2857 unsigned src_level, 2858 unsigned src_x, 2859 unsigned src_y, 2860 unsigned src_z, 2861 unsigned copy_height, 2862 unsigned pitch, 2863 unsigned bpp) 2864{ 2865 struct radeon_cmdbuf *cs = &rctx->b.dma.cs; 2866 struct r600_texture *rsrc = (struct r600_texture*)src; 2867 struct r600_texture *rdst = (struct r600_texture*)dst; 2868 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size; 2869 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode; 2870 uint64_t base, addr; 2871 2872 dst_mode = rdst->surface.u.legacy.level[dst_level].mode; 2873 src_mode = rsrc->surface.u.legacy.level[src_level].mode; 2874 assert(dst_mode != src_mode); 2875 2876 y = 0; 2877 lbpp = util_logbase2(bpp); 2878 pitch_tile_max = ((pitch / bpp) / 8) - 1; 2879 2880 if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED) { 2881 /* T2L */ 2882 array_mode = r600_array_mode(src_mode); 2883 slice_tile_max = (rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.u.legacy.level[src_level].nblk_y) / (8*8); 2884 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0; 2885 /* linear height must be the same as the slice tile max height, it's ok even 2886 * if the linear destination/source have smaller heigh as the size of the 2887 * dma packet will be using the copy_height which is always smaller or equal 2888 * to the linear height 2889 */ 2890 height = u_minify(rsrc->resource.b.b.height0, src_level); 2891 detile = 1; 2892 x = src_x; 2893 y = src_y; 2894 z = src_z; 2895 base = (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 256; 2896 addr = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256; 2897 addr += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z; 2898 addr += dst_y * pitch + dst_x * bpp; 2899 } else { 2900 /* L2T */ 2901 array_mode = r600_array_mode(dst_mode); 2902 slice_tile_max = (rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[dst_level].nblk_y) / (8*8); 2903 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0; 2904 /* linear height must be the same as the slice tile max height, it's ok even 2905 * if the linear destination/source have smaller heigh as the size of the 2906 * dma packet will be using the copy_height which is always smaller or equal 2907 * to the linear height 2908 */ 2909 height = u_minify(rdst->resource.b.b.height0, dst_level); 2910 detile = 0; 2911 x = dst_x; 2912 y = dst_y; 2913 z = dst_z; 2914 base = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256; 2915 addr = (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 256; 2916 addr += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_z; 2917 addr += src_y * pitch + src_x * bpp; 2918 } 2919 /* check that we are in dw/base alignment constraint */ 2920 if (addr % 4 || base % 256) { 2921 return FALSE; 2922 } 2923 2924 /* It's a r6xx/r7xx limitation, the blit must be on 8 boundary for number 2925 * line in the blit. Compute max 8 line we can copy in the size limit 2926 */ 2927 cheight = ((R600_DMA_COPY_MAX_SIZE_DW * 4) / pitch) & 0xfffffff8; 2928 ncopy = (copy_height / cheight) + !!(copy_height % cheight); 2929 r600_need_dma_space(&rctx->b, ncopy * 7, &rdst->resource, &rsrc->resource); 2930 2931 for (i = 0; i < ncopy; i++) { 2932 cheight = cheight > copy_height ? copy_height : cheight; 2933 size = (cheight * pitch) / 4; 2934 /* emit reloc before writing cs so that cs is always in consistent state */ 2935 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource, RADEON_USAGE_READ); 2936 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource, RADEON_USAGE_WRITE); 2937 radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, 1, 0, size)); 2938 radeon_emit(cs, base >> 8); 2939 radeon_emit(cs, (detile << 31) | (array_mode << 27) | 2940 (lbpp << 24) | ((height - 1) << 10) | 2941 pitch_tile_max); 2942 radeon_emit(cs, (slice_tile_max << 12) | (z << 0)); 2943 radeon_emit(cs, (x << 3) | (y << 17)); 2944 radeon_emit(cs, addr & 0xfffffffc); 2945 radeon_emit(cs, (addr >> 32UL) & 0xff); 2946 copy_height -= cheight; 2947 addr += cheight * pitch; 2948 y += cheight; 2949 } 2950 return TRUE; 2951} 2952 2953static void r600_dma_copy(struct pipe_context *ctx, 2954 struct pipe_resource *dst, 2955 unsigned dst_level, 2956 unsigned dstx, unsigned dsty, unsigned dstz, 2957 struct pipe_resource *src, 2958 unsigned src_level, 2959 const struct pipe_box *src_box) 2960{ 2961 struct r600_context *rctx = (struct r600_context *)ctx; 2962 struct r600_texture *rsrc = (struct r600_texture*)src; 2963 struct r600_texture *rdst = (struct r600_texture*)dst; 2964 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height; 2965 unsigned src_w, dst_w; 2966 unsigned src_x, src_y; 2967 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz; 2968 2969 if (rctx->b.dma.cs.priv == NULL) { 2970 goto fallback; 2971 } 2972 2973 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) { 2974 if (dst_x % 4 || src_box->x % 4 || src_box->width % 4) 2975 goto fallback; 2976 2977 r600_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width); 2978 return; 2979 } 2980 2981 if (src_box->depth > 1 || 2982 !r600_prepare_for_dma_blit(&rctx->b, rdst, dst_level, dstx, dsty, 2983 dstz, rsrc, src_level, src_box)) 2984 goto fallback; 2985 2986 src_x = util_format_get_nblocksx(src->format, src_box->x); 2987 dst_x = util_format_get_nblocksx(src->format, dst_x); 2988 src_y = util_format_get_nblocksy(src->format, src_box->y); 2989 dst_y = util_format_get_nblocksy(src->format, dst_y); 2990 2991 bpp = rdst->surface.bpe; 2992 dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.bpe; 2993 src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.bpe; 2994 src_w = u_minify(rsrc->resource.b.b.width0, src_level); 2995 dst_w = u_minify(rdst->resource.b.b.width0, dst_level); 2996 copy_height = src_box->height / rsrc->surface.blk_h; 2997 2998 dst_mode = rdst->surface.u.legacy.level[dst_level].mode; 2999 src_mode = rsrc->surface.u.legacy.level[src_level].mode; 3000 3001 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) { 3002 /* strict requirement on r6xx/r7xx */ 3003 goto fallback; 3004 } 3005 /* lot of constraint on alignment this should capture them all */ 3006 if (src_pitch % 8 || src_box->y % 8 || dst_y % 8) { 3007 goto fallback; 3008 } 3009 3010 if (src_mode == dst_mode) { 3011 uint64_t dst_offset, src_offset, size; 3012 3013 /* simple dma blit would do NOTE code here assume : 3014 * src_box.x/y == 0 3015 * dst_x/y == 0 3016 * dst_pitch == src_pitch 3017 */ 3018 src_offset= (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 256; 3019 src_offset += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_box->z; 3020 src_offset += src_y * src_pitch + src_x * bpp; 3021 dst_offset = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256; 3022 dst_offset += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z; 3023 dst_offset += dst_y * dst_pitch + dst_x * bpp; 3024 size = src_box->height * src_pitch; 3025 /* must be dw aligned */ 3026 if (dst_offset % 4 || src_offset % 4 || size % 4) { 3027 goto fallback; 3028 } 3029 r600_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset, size); 3030 } else { 3031 if (!r600_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z, 3032 src, src_level, src_x, src_y, src_box->z, 3033 copy_height, dst_pitch, bpp)) { 3034 goto fallback; 3035 } 3036 } 3037 return; 3038 3039fallback: 3040 r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz, 3041 src, src_level, src_box); 3042} 3043 3044void r600_init_state_functions(struct r600_context *rctx) 3045{ 3046 unsigned id = 1; 3047 unsigned i; 3048 /* !!! 3049 * To avoid GPU lockup registers must be emited in a specific order 3050 * (no kidding ...). The order below is important and have been 3051 * partialy infered from analyzing fglrx command stream. 3052 * 3053 * Don't reorder atom without carefully checking the effect (GPU lockup 3054 * or piglit regression). 3055 * !!! 3056 */ 3057 3058 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, r600_emit_framebuffer_state, 0); 3059 3060 /* shader const */ 3061 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0); 3062 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0); 3063 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, r600_emit_ps_constant_buffers, 0); 3064 3065 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change 3066 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map) 3067 */ 3068 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, r600_emit_vs_sampler_states, 0); 3069 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, r600_emit_gs_sampler_states, 0); 3070 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, r600_emit_ps_sampler_states, 0); 3071 /* resource */ 3072 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, r600_emit_vs_sampler_views, 0); 3073 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, r600_emit_gs_sampler_views, 0); 3074 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, r600_emit_ps_sampler_views, 0); 3075 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, r600_emit_vertex_buffers, 0); 3076 3077 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10); 3078 3079 r600_init_atom(rctx, &rctx->seamless_cube_map.atom, id++, r600_emit_seamless_cube_map, 3); 3080 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, r600_emit_sample_mask, 3); 3081 rctx->sample_mask.sample_mask = ~0; 3082 3083 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6); 3084 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6); 3085 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0); 3086 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 7); 3087 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6); 3088 r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26); 3089 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 7); 3090 r600_init_atom(rctx, &rctx->db_state.atom, id++, r600_emit_db_state, 11); 3091 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0); 3092 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, r600_emit_polygon_offset, 9); 3093 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0); 3094 r600_add_atom(rctx, &rctx->b.scissors.atom, id++); 3095 r600_add_atom(rctx, &rctx->b.viewports.atom, id++); 3096 r600_init_atom(rctx, &rctx->config_state.atom, id++, r600_emit_config_state, 3); 3097 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4); 3098 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, r600_emit_vertex_fetch_shader, 5); 3099 r600_add_atom(rctx, &rctx->b.render_cond_atom, id++); 3100 r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++); 3101 r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++); 3102 for (i = 0; i < R600_NUM_HW_STAGES; i++) 3103 r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0); 3104 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, r600_emit_shader_stages, 0); 3105 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, r600_emit_gs_rings, 0); 3106 3107 rctx->b.b.create_blend_state = r600_create_blend_state; 3108 rctx->b.b.create_depth_stencil_alpha_state = r600_create_dsa_state; 3109 rctx->b.b.create_rasterizer_state = r600_create_rs_state; 3110 rctx->b.b.create_sampler_state = r600_create_sampler_state; 3111 rctx->b.b.create_sampler_view = r600_create_sampler_view; 3112 rctx->b.b.set_framebuffer_state = r600_set_framebuffer_state; 3113 rctx->b.b.set_polygon_stipple = r600_set_polygon_stipple; 3114 rctx->b.b.set_min_samples = r600_set_min_samples; 3115 rctx->b.b.get_sample_position = r600_get_sample_position; 3116 rctx->b.dma_copy = r600_dma_copy; 3117} 3118/* this function must be last */ 3119