1/*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 */
25
26/**
27 * This file contains helpers for writing commands to commands streams.
28 */
29
30#ifndef R600_CS_H
31#define R600_CS_H
32
33#include "r600_pipe_common.h"
34#include "r600d_common.h"
35
36/**
37 * Return true if there is enough memory in VRAM and GTT for the buffers
38 * added so far.
39 *
40 * \param vram      VRAM memory size not added to the buffer list yet
41 * \param gtt       GTT memory size not added to the buffer list yet
42 */
43static inline bool
44radeon_cs_memory_below_limit(struct r600_common_screen *screen,
45			     struct radeon_cmdbuf *cs,
46			     uint64_t vram, uint64_t gtt)
47{
48	vram += (uint64_t)cs->used_vram_kb * 1024;
49	gtt += (uint64_t)cs->used_gart_kb * 1024;
50
51	/* Anything that goes above the VRAM size should go to GTT. */
52	if (vram > (uint64_t)screen->info.vram_size_kb * 1024)
53		gtt += vram - (uint64_t)screen->info.vram_size_kb * 1024;
54
55	/* Now we just need to check if we have enough GTT. */
56	return gtt < (uint64_t)screen->info.gart_size_kb * 1024 * 0.7;
57}
58
59/**
60 * Add a buffer to the buffer list for the given command stream (CS).
61 *
62 * All buffers used by a CS must be added to the list. This tells the kernel
63 * driver which buffers are used by GPU commands. Other buffers can
64 * be swapped out (not accessible) during execution.
65 *
66 * The buffer list becomes empty after every context flush and must be
67 * rebuilt.
68 */
69static inline unsigned radeon_add_to_buffer_list(struct r600_common_context *rctx,
70						 struct r600_ring *ring,
71						 struct r600_resource *rbo,
72						 unsigned usage)
73{
74	assert(usage);
75	return rctx->ws->cs_add_buffer(
76		&ring->cs, rbo->buf,
77		usage | RADEON_USAGE_SYNCHRONIZED,
78		rbo->domains) * 4;
79}
80
81/**
82 * Same as above, but also checks memory usage and flushes the context
83 * accordingly.
84 *
85 * When this SHOULD NOT be used:
86 *
87 * - if r600_context_add_resource_size has been called for the buffer
88 *   followed by *_need_cs_space for checking the memory usage
89 *
90 * - if r600_need_dma_space has been called for the buffer
91 *
92 * - when emitting state packets and draw packets (because preceding packets
93 *   can't be re-emitted at that point)
94 *
95 * - if shader resource "enabled_mask" is not up-to-date or there is
96 *   a different constraint disallowing a context flush
97 */
98static inline unsigned
99radeon_add_to_buffer_list_check_mem(struct r600_common_context *rctx,
100				    struct r600_ring *ring,
101				    struct r600_resource *rbo,
102				    unsigned usage,
103				    bool check_mem)
104{
105	if (check_mem &&
106	    !radeon_cs_memory_below_limit(rctx->screen, &ring->cs,
107					  rctx->vram + rbo->vram_usage,
108					  rctx->gtt + rbo->gart_usage))
109		ring->flush(rctx, PIPE_FLUSH_ASYNC, NULL);
110
111	return radeon_add_to_buffer_list(rctx, ring, rbo, usage);
112}
113
114static inline void r600_emit_reloc(struct r600_common_context *rctx,
115				   struct r600_ring *ring, struct r600_resource *rbo,
116				   unsigned usage)
117{
118	struct radeon_cmdbuf *cs = &ring->cs;
119	bool has_vm = ((struct r600_common_screen*)rctx->b.screen)->info.r600_has_virtual_memory;
120	unsigned reloc = radeon_add_to_buffer_list(rctx, ring, rbo, usage);
121
122	if (!has_vm) {
123		radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
124		radeon_emit(cs, reloc);
125	}
126}
127
128static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
129{
130	assert(reg < R600_CONTEXT_REG_OFFSET);
131	assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
132	radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));
133	radeon_emit(cs, (reg - R600_CONFIG_REG_OFFSET) >> 2);
134}
135
136static inline void radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
137{
138	radeon_set_config_reg_seq(cs, reg, 1);
139	radeon_emit(cs, value);
140}
141
142static inline void radeon_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
143{
144	assert(reg >= R600_CONTEXT_REG_OFFSET);
145	assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
146	radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0));
147	radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2);
148}
149
150static inline void radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
151{
152	radeon_set_context_reg_seq(cs, reg, 1);
153	radeon_emit(cs, value);
154}
155
156static inline void radeon_set_context_reg_idx(struct radeon_cmdbuf *cs,
157					      unsigned reg, unsigned idx,
158					      unsigned value)
159{
160	assert(reg >= R600_CONTEXT_REG_OFFSET);
161	assert(cs->current.cdw + 3 <= cs->current.max_dw);
162	radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0));
163	radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2 | (idx << 28));
164	radeon_emit(cs, value);
165}
166
167static inline void radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
168{
169	assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
170	assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
171	radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0));
172	radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2);
173}
174
175static inline void radeon_set_sh_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
176{
177	radeon_set_sh_reg_seq(cs, reg, 1);
178	radeon_emit(cs, value);
179}
180
181static inline void radeon_set_uconfig_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
182{
183	assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
184	assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
185	radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0));
186	radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
187}
188
189static inline void radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
190{
191	radeon_set_uconfig_reg_seq(cs, reg, 1);
192	radeon_emit(cs, value);
193}
194
195static inline void radeon_set_uconfig_reg_idx(struct radeon_cmdbuf *cs,
196					      unsigned reg, unsigned idx,
197					      unsigned value)
198{
199	assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
200	assert(cs->current.cdw + 3 <= cs->current.max_dw);
201	radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, 1, 0));
202	radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28));
203	radeon_emit(cs, value);
204}
205
206#endif
207