1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23#include "r600_formats.h" 24#include "r600_shader.h" 25#include "r600_query.h" 26#include "evergreend.h" 27 28#include "pipe/p_shader_tokens.h" 29#include "util/u_pack_color.h" 30#include "util/u_memory.h" 31#include "util/u_framebuffer.h" 32#include "util/u_dual_blend.h" 33#include "evergreen_compute.h" 34#include "util/u_math.h" 35 36static inline unsigned evergreen_array_mode(unsigned mode) 37{ 38 switch (mode) { 39 default: 40 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_028C70_ARRAY_LINEAR_ALIGNED; 41 break; 42 case RADEON_SURF_MODE_1D: return V_028C70_ARRAY_1D_TILED_THIN1; 43 break; 44 case RADEON_SURF_MODE_2D: return V_028C70_ARRAY_2D_TILED_THIN1; 45 } 46} 47 48static uint32_t eg_num_banks(uint32_t nbanks) 49{ 50 switch (nbanks) { 51 case 2: 52 return 0; 53 case 4: 54 return 1; 55 case 8: 56 default: 57 return 2; 58 case 16: 59 return 3; 60 } 61} 62 63 64static unsigned eg_tile_split(unsigned tile_split) 65{ 66 switch (tile_split) { 67 case 64: tile_split = 0; break; 68 case 128: tile_split = 1; break; 69 case 256: tile_split = 2; break; 70 case 512: tile_split = 3; break; 71 default: 72 case 1024: tile_split = 4; break; 73 case 2048: tile_split = 5; break; 74 case 4096: tile_split = 6; break; 75 } 76 return tile_split; 77} 78 79static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect) 80{ 81 switch (macro_tile_aspect) { 82 default: 83 case 1: macro_tile_aspect = 0; break; 84 case 2: macro_tile_aspect = 1; break; 85 case 4: macro_tile_aspect = 2; break; 86 case 8: macro_tile_aspect = 3; break; 87 } 88 return macro_tile_aspect; 89} 90 91static unsigned eg_bank_wh(unsigned bankwh) 92{ 93 switch (bankwh) { 94 default: 95 case 1: bankwh = 0; break; 96 case 2: bankwh = 1; break; 97 case 4: bankwh = 2; break; 98 case 8: bankwh = 3; break; 99 } 100 return bankwh; 101} 102 103static uint32_t r600_translate_blend_function(int blend_func) 104{ 105 switch (blend_func) { 106 case PIPE_BLEND_ADD: 107 return V_028780_COMB_DST_PLUS_SRC; 108 case PIPE_BLEND_SUBTRACT: 109 return V_028780_COMB_SRC_MINUS_DST; 110 case PIPE_BLEND_REVERSE_SUBTRACT: 111 return V_028780_COMB_DST_MINUS_SRC; 112 case PIPE_BLEND_MIN: 113 return V_028780_COMB_MIN_DST_SRC; 114 case PIPE_BLEND_MAX: 115 return V_028780_COMB_MAX_DST_SRC; 116 default: 117 R600_ERR("Unknown blend function %d\n", blend_func); 118 assert(0); 119 break; 120 } 121 return 0; 122} 123 124static uint32_t r600_translate_blend_factor(int blend_fact) 125{ 126 switch (blend_fact) { 127 case PIPE_BLENDFACTOR_ONE: 128 return V_028780_BLEND_ONE; 129 case PIPE_BLENDFACTOR_SRC_COLOR: 130 return V_028780_BLEND_SRC_COLOR; 131 case PIPE_BLENDFACTOR_SRC_ALPHA: 132 return V_028780_BLEND_SRC_ALPHA; 133 case PIPE_BLENDFACTOR_DST_ALPHA: 134 return V_028780_BLEND_DST_ALPHA; 135 case PIPE_BLENDFACTOR_DST_COLOR: 136 return V_028780_BLEND_DST_COLOR; 137 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE: 138 return V_028780_BLEND_SRC_ALPHA_SATURATE; 139 case PIPE_BLENDFACTOR_CONST_COLOR: 140 return V_028780_BLEND_CONST_COLOR; 141 case PIPE_BLENDFACTOR_CONST_ALPHA: 142 return V_028780_BLEND_CONST_ALPHA; 143 case PIPE_BLENDFACTOR_ZERO: 144 return V_028780_BLEND_ZERO; 145 case PIPE_BLENDFACTOR_INV_SRC_COLOR: 146 return V_028780_BLEND_ONE_MINUS_SRC_COLOR; 147 case PIPE_BLENDFACTOR_INV_SRC_ALPHA: 148 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA; 149 case PIPE_BLENDFACTOR_INV_DST_ALPHA: 150 return V_028780_BLEND_ONE_MINUS_DST_ALPHA; 151 case PIPE_BLENDFACTOR_INV_DST_COLOR: 152 return V_028780_BLEND_ONE_MINUS_DST_COLOR; 153 case PIPE_BLENDFACTOR_INV_CONST_COLOR: 154 return V_028780_BLEND_ONE_MINUS_CONST_COLOR; 155 case PIPE_BLENDFACTOR_INV_CONST_ALPHA: 156 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA; 157 case PIPE_BLENDFACTOR_SRC1_COLOR: 158 return V_028780_BLEND_SRC1_COLOR; 159 case PIPE_BLENDFACTOR_SRC1_ALPHA: 160 return V_028780_BLEND_SRC1_ALPHA; 161 case PIPE_BLENDFACTOR_INV_SRC1_COLOR: 162 return V_028780_BLEND_INV_SRC1_COLOR; 163 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA: 164 return V_028780_BLEND_INV_SRC1_ALPHA; 165 default: 166 R600_ERR("Bad blend factor %d not supported!\n", blend_fact); 167 assert(0); 168 break; 169 } 170 return 0; 171} 172 173static unsigned r600_tex_dim(struct r600_texture *rtex, 174 unsigned view_target, unsigned nr_samples) 175{ 176 unsigned res_target = rtex->resource.b.b.target; 177 178 if (view_target == PIPE_TEXTURE_CUBE || 179 view_target == PIPE_TEXTURE_CUBE_ARRAY) 180 res_target = view_target; 181 /* If interpreting cubemaps as something else, set 2D_ARRAY. */ 182 else if (res_target == PIPE_TEXTURE_CUBE || 183 res_target == PIPE_TEXTURE_CUBE_ARRAY) 184 res_target = PIPE_TEXTURE_2D_ARRAY; 185 186 switch (res_target) { 187 default: 188 case PIPE_TEXTURE_1D: 189 return V_030000_SQ_TEX_DIM_1D; 190 case PIPE_TEXTURE_1D_ARRAY: 191 return V_030000_SQ_TEX_DIM_1D_ARRAY; 192 case PIPE_TEXTURE_2D: 193 case PIPE_TEXTURE_RECT: 194 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_MSAA : 195 V_030000_SQ_TEX_DIM_2D; 196 case PIPE_TEXTURE_2D_ARRAY: 197 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA : 198 V_030000_SQ_TEX_DIM_2D_ARRAY; 199 case PIPE_TEXTURE_3D: 200 return V_030000_SQ_TEX_DIM_3D; 201 case PIPE_TEXTURE_CUBE: 202 case PIPE_TEXTURE_CUBE_ARRAY: 203 return V_030000_SQ_TEX_DIM_CUBEMAP; 204 } 205} 206 207static uint32_t r600_translate_dbformat(enum pipe_format format) 208{ 209 switch (format) { 210 case PIPE_FORMAT_Z16_UNORM: 211 return V_028040_Z_16; 212 case PIPE_FORMAT_Z24X8_UNORM: 213 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 214 case PIPE_FORMAT_X8Z24_UNORM: 215 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 216 return V_028040_Z_24; 217 case PIPE_FORMAT_Z32_FLOAT: 218 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 219 return V_028040_Z_32_FLOAT; 220 default: 221 return ~0U; 222 } 223} 224 225static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format) 226{ 227 return r600_translate_texformat(screen, format, NULL, NULL, NULL, 228 FALSE) != ~0U; 229} 230 231static bool r600_is_colorbuffer_format_supported(enum amd_gfx_level chip, enum pipe_format format) 232{ 233 return r600_translate_colorformat(chip, format, FALSE) != ~0U && 234 r600_translate_colorswap(format, FALSE) != ~0U; 235} 236 237static bool r600_is_zs_format_supported(enum pipe_format format) 238{ 239 return r600_translate_dbformat(format) != ~0U; 240} 241 242bool evergreen_is_format_supported(struct pipe_screen *screen, 243 enum pipe_format format, 244 enum pipe_texture_target target, 245 unsigned sample_count, 246 unsigned storage_sample_count, 247 unsigned usage) 248{ 249 struct r600_screen *rscreen = (struct r600_screen*)screen; 250 unsigned retval = 0; 251 252 if (target >= PIPE_MAX_TEXTURE_TYPES) { 253 R600_ERR("r600: unsupported texture type %d\n", target); 254 return false; 255 } 256 257 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count)) 258 return false; 259 260 if (sample_count > 1) { 261 if (!rscreen->has_msaa) 262 return false; 263 264 switch (sample_count) { 265 case 2: 266 case 4: 267 case 8: 268 break; 269 default: 270 return false; 271 } 272 } 273 274 if (usage & PIPE_BIND_SAMPLER_VIEW) { 275 if (target == PIPE_BUFFER) { 276 if (r600_is_buffer_format_supported(format, false)) 277 retval |= PIPE_BIND_SAMPLER_VIEW; 278 } else { 279 if (r600_is_sampler_format_supported(screen, format)) 280 retval |= PIPE_BIND_SAMPLER_VIEW; 281 } 282 } 283 284 if ((usage & (PIPE_BIND_RENDER_TARGET | 285 PIPE_BIND_DISPLAY_TARGET | 286 PIPE_BIND_SCANOUT | 287 PIPE_BIND_SHARED | 288 PIPE_BIND_BLENDABLE)) && 289 r600_is_colorbuffer_format_supported(rscreen->b.gfx_level, format)) { 290 retval |= usage & 291 (PIPE_BIND_RENDER_TARGET | 292 PIPE_BIND_DISPLAY_TARGET | 293 PIPE_BIND_SCANOUT | 294 PIPE_BIND_SHARED); 295 if (!util_format_is_pure_integer(format) && 296 !util_format_is_depth_or_stencil(format)) 297 retval |= usage & PIPE_BIND_BLENDABLE; 298 } 299 300 if ((usage & PIPE_BIND_DEPTH_STENCIL) && 301 r600_is_zs_format_supported(format)) { 302 retval |= PIPE_BIND_DEPTH_STENCIL; 303 } 304 305 if ((usage & PIPE_BIND_VERTEX_BUFFER) && 306 r600_is_buffer_format_supported(format, true)) { 307 retval |= PIPE_BIND_VERTEX_BUFFER; 308 } 309 310 if (usage & PIPE_BIND_INDEX_BUFFER && 311 r600_is_index_format_supported(format)) { 312 retval |= PIPE_BIND_INDEX_BUFFER; 313 } 314 315 if ((usage & PIPE_BIND_LINEAR) && 316 !util_format_is_compressed(format) && 317 !(usage & PIPE_BIND_DEPTH_STENCIL)) 318 retval |= PIPE_BIND_LINEAR; 319 320 return retval == usage; 321} 322 323static void *evergreen_create_blend_state_mode(struct pipe_context *ctx, 324 const struct pipe_blend_state *state, int mode) 325{ 326 uint32_t color_control = 0, target_mask = 0; 327 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state); 328 329 if (!blend) { 330 return NULL; 331 } 332 333 r600_init_command_buffer(&blend->buffer, 20); 334 r600_init_command_buffer(&blend->buffer_no_blend, 20); 335 336 if (state->logicop_enable) { 337 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20); 338 } else { 339 color_control |= (0xcc << 16); 340 } 341 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */ 342 if (state->independent_blend_enable) { 343 for (int i = 0; i < 8; i++) { 344 target_mask |= (state->rt[i].colormask << (4 * i)); 345 } 346 } else { 347 for (int i = 0; i < 8; i++) { 348 target_mask |= (state->rt[0].colormask << (4 * i)); 349 } 350 } 351 352 /* only have dual source on MRT0 */ 353 blend->dual_src_blend = util_blend_state_is_dual(state, 0); 354 blend->cb_target_mask = target_mask; 355 blend->alpha_to_one = state->alpha_to_one; 356 357 if (target_mask) 358 color_control |= S_028808_MODE(mode); 359 else 360 color_control |= S_028808_MODE(V_028808_CB_DISABLE); 361 362 363 r600_store_context_reg(&blend->buffer, R_028808_CB_COLOR_CONTROL, color_control); 364 r600_store_context_reg(&blend->buffer, R_028B70_DB_ALPHA_TO_MASK, 365 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) | 366 S_028B70_ALPHA_TO_MASK_OFFSET0(2) | 367 S_028B70_ALPHA_TO_MASK_OFFSET1(2) | 368 S_028B70_ALPHA_TO_MASK_OFFSET2(2) | 369 S_028B70_ALPHA_TO_MASK_OFFSET3(2)); 370 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8); 371 372 /* Copy over the dwords set so far into buffer_no_blend. 373 * Only the CB_BLENDi_CONTROL registers must be set after this. */ 374 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4); 375 blend->buffer_no_blend.num_dw = blend->buffer.num_dw; 376 377 for (int i = 0; i < 8; i++) { 378 /* state->rt entries > 0 only written if independent blending */ 379 const int j = state->independent_blend_enable ? i : 0; 380 381 unsigned eqRGB = state->rt[j].rgb_func; 382 unsigned srcRGB = state->rt[j].rgb_src_factor; 383 unsigned dstRGB = state->rt[j].rgb_dst_factor; 384 unsigned eqA = state->rt[j].alpha_func; 385 unsigned srcA = state->rt[j].alpha_src_factor; 386 unsigned dstA = state->rt[j].alpha_dst_factor; 387 uint32_t bc = 0; 388 389 r600_store_value(&blend->buffer_no_blend, 0); 390 391 if (!state->rt[j].blend_enable) { 392 r600_store_value(&blend->buffer, 0); 393 continue; 394 } 395 396 bc |= S_028780_BLEND_CONTROL_ENABLE(1); 397 bc |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB)); 398 bc |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB)); 399 bc |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB)); 400 401 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { 402 bc |= S_028780_SEPARATE_ALPHA_BLEND(1); 403 bc |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA)); 404 bc |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA)); 405 bc |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA)); 406 } 407 r600_store_value(&blend->buffer, bc); 408 } 409 return blend; 410} 411 412static void *evergreen_create_blend_state(struct pipe_context *ctx, 413 const struct pipe_blend_state *state) 414{ 415 416 return evergreen_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL); 417} 418 419static void *evergreen_create_dsa_state(struct pipe_context *ctx, 420 const struct pipe_depth_stencil_alpha_state *state) 421{ 422 unsigned db_depth_control, alpha_test_control, alpha_ref; 423 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state); 424 425 if (!dsa) { 426 return NULL; 427 } 428 429 r600_init_command_buffer(&dsa->buffer, 3); 430 431 dsa->valuemask[0] = state->stencil[0].valuemask; 432 dsa->valuemask[1] = state->stencil[1].valuemask; 433 dsa->writemask[0] = state->stencil[0].writemask; 434 dsa->writemask[1] = state->stencil[1].writemask; 435 dsa->zwritemask = state->depth_writemask; 436 437 db_depth_control = S_028800_Z_ENABLE(state->depth_enabled) | 438 S_028800_Z_WRITE_ENABLE(state->depth_writemask) | 439 S_028800_ZFUNC(state->depth_func); 440 441 /* stencil */ 442 if (state->stencil[0].enabled) { 443 db_depth_control |= S_028800_STENCIL_ENABLE(1); 444 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */ 445 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op)); 446 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op)); 447 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op)); 448 449 if (state->stencil[1].enabled) { 450 db_depth_control |= S_028800_BACKFACE_ENABLE(1); 451 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */ 452 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op)); 453 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op)); 454 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op)); 455 } 456 } 457 458 /* alpha */ 459 alpha_test_control = 0; 460 alpha_ref = 0; 461 if (state->alpha_enabled) { 462 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha_func); 463 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1); 464 alpha_ref = fui(state->alpha_ref_value); 465 } 466 dsa->sx_alpha_test_control = alpha_test_control & 0xff; 467 dsa->alpha_ref = alpha_ref; 468 469 /* misc */ 470 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control); 471 return dsa; 472} 473 474static void *evergreen_create_rs_state(struct pipe_context *ctx, 475 const struct pipe_rasterizer_state *state) 476{ 477 struct r600_context *rctx = (struct r600_context *)ctx; 478 unsigned tmp, spi_interp; 479 float psize_min, psize_max; 480 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state); 481 482 if (!rs) { 483 return NULL; 484 } 485 486 r600_init_command_buffer(&rs->buffer, 30); 487 488 rs->scissor_enable = state->scissor; 489 rs->clip_halfz = state->clip_halfz; 490 rs->flatshade = state->flatshade; 491 rs->sprite_coord_enable = state->sprite_coord_enable; 492 rs->rasterizer_discard = state->rasterizer_discard; 493 rs->two_side = state->light_twoside; 494 rs->clip_plane_enable = state->clip_plane_enable; 495 rs->pa_sc_line_stipple = state->line_stipple_enable ? 496 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) | 497 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0; 498 rs->pa_cl_clip_cntl = 499 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) | 500 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) | 501 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_far) | 502 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1) | 503 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard); 504 rs->multisample_enable = state->multisample; 505 506 /* offset */ 507 rs->offset_units = state->offset_units; 508 rs->offset_scale = state->offset_scale * 16.0f; 509 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri; 510 rs->offset_units_unscaled = state->offset_units_unscaled; 511 512 if (state->point_size_per_vertex) { 513 psize_min = util_get_min_point_size(state); 514 psize_max = 8192; 515 } else { 516 /* Force the point size to be as if the vertex output was disabled. */ 517 psize_min = state->point_size; 518 psize_max = state->point_size; 519 } 520 521 spi_interp = S_0286D4_FLAT_SHADE_ENA(1); 522 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) | 523 S_0286D4_PNT_SPRITE_OVRD_X(2) | 524 S_0286D4_PNT_SPRITE_OVRD_Y(3) | 525 S_0286D4_PNT_SPRITE_OVRD_Z(0) | 526 S_0286D4_PNT_SPRITE_OVRD_W(1); 527 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) { 528 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1); 529 } 530 531 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3); 532 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */ 533 tmp = r600_pack_float_12p4(state->point_size/2); 534 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */ 535 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp)); 536 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */ 537 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) | 538 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2))); 539 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */ 540 S_028A08_WIDTH((unsigned)(state->line_width * 8))); 541 542 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp); 543 r600_store_context_reg(&rs->buffer, R_028A48_PA_SC_MODE_CNTL_0, 544 S_028A48_MSAA_ENABLE(state->multisample) | 545 S_028A48_VPORT_SCISSOR_ENABLE(1) | 546 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable)); 547 548 if (rctx->b.gfx_level == CAYMAN) { 549 r600_store_context_reg(&rs->buffer, CM_R_028BE4_PA_SU_VTX_CNTL, 550 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) | 551 S_028C08_QUANT_MODE(V_028C08_X_1_256TH)); 552 } else { 553 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL, 554 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) | 555 S_028C08_QUANT_MODE(V_028C08_X_1_256TH)); 556 } 557 558 r600_store_context_reg(&rs->buffer, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp)); 559 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL, 560 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) | 561 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) | 562 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) | 563 S_028814_FACE(!state->front_ccw) | 564 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) | 565 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) | 566 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) | 567 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL || 568 state->fill_back != PIPE_POLYGON_MODE_FILL) | 569 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) | 570 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back))); 571 return rs; 572} 573 574static void *evergreen_create_sampler_state(struct pipe_context *ctx, 575 const struct pipe_sampler_state *state) 576{ 577 struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen; 578 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state); 579 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso 580 : state->max_anisotropy; 581 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso); 582 bool trunc_coord = state->min_img_filter == PIPE_TEX_FILTER_NEAREST && 583 state->mag_img_filter == PIPE_TEX_FILTER_NEAREST; 584 float max_lod = state->max_lod; 585 586 if (!ss) { 587 return NULL; 588 } 589 590 /* If the min_mip_filter is NONE, then the texture has no mipmapping and 591 * MIP_FILTER will also be set to NONE. However, if more then one LOD is 592 * configured, then the texture lookup seems to fail for some specific texture 593 * formats. Forcing the number of LODs to one in this case fixes it. */ 594 if (state->min_mip_filter == PIPE_TEX_MIPFILTER_NONE) 595 max_lod = state->min_lod; 596 597 ss->border_color_use = sampler_state_needs_border_color(state); 598 599 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */ 600 ss->tex_sampler_words[0] = 601 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) | 602 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) | 603 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) | 604 S_03C000_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) | 605 S_03C000_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) | 606 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) | 607 S_03C000_MAX_ANISO_RATIO(max_aniso_ratio) | 608 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) | 609 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0); 610 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */ 611 ss->tex_sampler_words[1] = 612 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) | 613 S_03C004_MAX_LOD(S_FIXED(CLAMP(max_lod, 0, 15), 8)); 614 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */ 615 ss->tex_sampler_words[2] = 616 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) | 617 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) | 618 S_03C008_TRUNCATE_COORD(trunc_coord) | 619 S_03C008_TYPE(1); 620 621 if (ss->border_color_use) { 622 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color)); 623 } 624 return ss; 625} 626 627struct eg_buf_res_params { 628 enum pipe_format pipe_format; 629 unsigned offset; 630 unsigned size; 631 unsigned char swizzle[4]; 632 bool uncached; 633 bool force_swizzle; 634 bool size_in_bytes; 635}; 636 637static void evergreen_fill_buffer_resource_words(struct r600_context *rctx, 638 struct pipe_resource *buffer, 639 struct eg_buf_res_params *params, 640 bool *skip_mip_address_reloc, 641 unsigned tex_resource_words[8]) 642{ 643 struct r600_texture *tmp = (struct r600_texture*)buffer; 644 uint64_t va; 645 int stride = util_format_get_blocksize(params->pipe_format); 646 unsigned format, num_format, format_comp, endian; 647 unsigned swizzle_res; 648 const struct util_format_description *desc; 649 650 r600_vertex_data_type(params->pipe_format, 651 &format, &num_format, &format_comp, 652 &endian); 653 654 desc = util_format_description(params->pipe_format); 655 656 if (params->force_swizzle) 657 swizzle_res = r600_get_swizzle_combined(params->swizzle, NULL, TRUE); 658 else 659 swizzle_res = r600_get_swizzle_combined(desc->swizzle, params->swizzle, TRUE); 660 661 va = tmp->resource.gpu_address + params->offset; 662 *skip_mip_address_reloc = true; 663 tex_resource_words[0] = va; 664 tex_resource_words[1] = params->size - 1; 665 tex_resource_words[2] = S_030008_BASE_ADDRESS_HI(va >> 32UL) | 666 S_030008_STRIDE(stride) | 667 S_030008_DATA_FORMAT(format) | 668 S_030008_NUM_FORMAT_ALL(num_format) | 669 S_030008_FORMAT_COMP_ALL(format_comp) | 670 S_030008_ENDIAN_SWAP(endian); 671 tex_resource_words[3] = swizzle_res | S_03000C_UNCACHED(params->uncached); 672 /* 673 * dword 4 is for number of elements, for use with resinfo, 674 * albeit the amd gpu shader analyser 675 * uses a const buffer to store the element sizes for buffer txq 676 */ 677 tex_resource_words[4] = params->size_in_bytes ? params->size : (params->size / stride); 678 679 tex_resource_words[5] = tex_resource_words[6] = 0; 680 tex_resource_words[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER); 681} 682 683static struct pipe_sampler_view * 684texture_buffer_sampler_view(struct r600_context *rctx, 685 struct r600_pipe_sampler_view *view, 686 unsigned width0, unsigned height0) 687{ 688 struct r600_texture *tmp = (struct r600_texture*)view->base.texture; 689 struct eg_buf_res_params params; 690 691 memset(¶ms, 0, sizeof(params)); 692 693 params.pipe_format = view->base.format; 694 params.offset = view->base.u.buf.offset; 695 params.size = view->base.u.buf.size; 696 params.swizzle[0] = view->base.swizzle_r; 697 params.swizzle[1] = view->base.swizzle_g; 698 params.swizzle[2] = view->base.swizzle_b; 699 params.swizzle[3] = view->base.swizzle_a; 700 701 evergreen_fill_buffer_resource_words(rctx, view->base.texture, 702 ¶ms, &view->skip_mip_address_reloc, 703 view->tex_resource_words); 704 view->tex_resource = &tmp->resource; 705 706 if (tmp->resource.gpu_address) 707 list_addtail(&view->list, &rctx->texture_buffers); 708 return &view->base; 709} 710 711struct eg_tex_res_params { 712 enum pipe_format pipe_format; 713 int force_level; 714 unsigned width0; 715 unsigned height0; 716 unsigned first_level; 717 unsigned last_level; 718 unsigned first_layer; 719 unsigned last_layer; 720 unsigned target; 721 unsigned char swizzle[4]; 722}; 723 724static int evergreen_fill_tex_resource_words(struct r600_context *rctx, 725 struct pipe_resource *texture, 726 struct eg_tex_res_params *params, 727 bool *skip_mip_address_reloc, 728 unsigned tex_resource_words[8]) 729{ 730 struct r600_screen *rscreen = (struct r600_screen*)rctx->b.b.screen; 731 struct r600_texture *tmp = (struct r600_texture*)texture; 732 unsigned format, endian; 733 uint32_t word4 = 0, yuv_format = 0, pitch = 0; 734 unsigned char array_mode = 0, non_disp_tiling = 0; 735 unsigned height, depth, width; 736 unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh; 737 struct legacy_surf_level *surflevel; 738 unsigned base_level, first_level, last_level; 739 unsigned dim, last_layer; 740 uint64_t va; 741 bool do_endian_swap = FALSE; 742 743 tile_split = tmp->surface.u.legacy.tile_split; 744 surflevel = tmp->surface.u.legacy.level; 745 746 /* Texturing with separate depth and stencil. */ 747 if (tmp->db_compatible) { 748 switch (params->pipe_format) { 749 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 750 params->pipe_format = PIPE_FORMAT_Z32_FLOAT; 751 break; 752 case PIPE_FORMAT_X8Z24_UNORM: 753 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 754 /* Z24 is always stored like this for DB 755 * compatibility. 756 */ 757 params->pipe_format = PIPE_FORMAT_Z24X8_UNORM; 758 break; 759 case PIPE_FORMAT_X24S8_UINT: 760 case PIPE_FORMAT_S8X24_UINT: 761 case PIPE_FORMAT_X32_S8X24_UINT: 762 params->pipe_format = PIPE_FORMAT_S8_UINT; 763 tile_split = tmp->surface.u.legacy.stencil_tile_split; 764 surflevel = tmp->surface.u.legacy.zs.stencil_level; 765 break; 766 default:; 767 } 768 } 769 770 if (R600_BIG_ENDIAN) 771 do_endian_swap = !tmp->db_compatible; 772 773 format = r600_translate_texformat(rctx->b.b.screen, params->pipe_format, 774 params->swizzle, 775 &word4, &yuv_format, do_endian_swap); 776 assert(format != ~0); 777 if (format == ~0) { 778 return -1; 779 } 780 781 endian = r600_colorformat_endian_swap(format, do_endian_swap); 782 783 base_level = 0; 784 first_level = params->first_level; 785 last_level = params->last_level; 786 width = params->width0; 787 height = params->height0; 788 depth = texture->depth0; 789 790 if (params->force_level) { 791 base_level = params->force_level; 792 first_level = 0; 793 last_level = 0; 794 width = u_minify(width, params->force_level); 795 height = u_minify(height, params->force_level); 796 depth = u_minify(depth, params->force_level); 797 } 798 799 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(params->pipe_format); 800 non_disp_tiling = tmp->non_disp_tiling; 801 802 switch (surflevel[base_level].mode) { 803 default: 804 case RADEON_SURF_MODE_LINEAR_ALIGNED: 805 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED; 806 break; 807 case RADEON_SURF_MODE_2D: 808 array_mode = V_028C70_ARRAY_2D_TILED_THIN1; 809 break; 810 case RADEON_SURF_MODE_1D: 811 array_mode = V_028C70_ARRAY_1D_TILED_THIN1; 812 break; 813 } 814 macro_aspect = tmp->surface.u.legacy.mtilea; 815 bankw = tmp->surface.u.legacy.bankw; 816 bankh = tmp->surface.u.legacy.bankh; 817 tile_split = eg_tile_split(tile_split); 818 macro_aspect = eg_macro_tile_aspect(macro_aspect); 819 bankw = eg_bank_wh(bankw); 820 bankh = eg_bank_wh(bankh); 821 fmask_bankh = eg_bank_wh(tmp->fmask.bank_height); 822 823 /* 128 bit formats require tile type = 1 */ 824 if (rscreen->b.gfx_level == CAYMAN) { 825 if (util_format_get_blocksize(params->pipe_format) >= 16) 826 non_disp_tiling = 1; 827 } 828 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks); 829 830 831 va = tmp->resource.gpu_address; 832 833 /* array type views and views into array types need to use layer offset */ 834 dim = r600_tex_dim(tmp, params->target, texture->nr_samples); 835 836 if (dim == V_030000_SQ_TEX_DIM_1D_ARRAY) { 837 height = 1; 838 depth = texture->array_size; 839 } else if (dim == V_030000_SQ_TEX_DIM_2D_ARRAY || 840 dim == V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA) { 841 depth = texture->array_size; 842 } else if (dim == V_030000_SQ_TEX_DIM_CUBEMAP) 843 depth = texture->array_size / 6; 844 845 tex_resource_words[0] = (S_030000_DIM(dim) | 846 S_030000_PITCH((pitch / 8) - 1) | 847 S_030000_TEX_WIDTH(width - 1)); 848 if (rscreen->b.gfx_level == CAYMAN) 849 tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling); 850 else 851 tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling); 852 tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) | 853 S_030004_TEX_DEPTH(depth - 1) | 854 S_030004_ARRAY_MODE(array_mode)); 855 tex_resource_words[2] = ((uint64_t)surflevel[base_level].offset_256B * 256 + va) >> 8; 856 857 *skip_mip_address_reloc = false; 858 /* TEX_RESOURCE_WORD3.MIP_ADDRESS */ 859 if (texture->nr_samples > 1 && rscreen->has_compressed_msaa_texturing) { 860 if (tmp->is_depth) { 861 /* disable FMASK (0 = disabled) */ 862 tex_resource_words[3] = 0; 863 *skip_mip_address_reloc = true; 864 } else { 865 /* FMASK should be in MIP_ADDRESS for multisample textures */ 866 tex_resource_words[3] = (tmp->fmask.offset + va) >> 8; 867 } 868 } else if (last_level && texture->nr_samples <= 1) { 869 tex_resource_words[3] = ((uint64_t)surflevel[1].offset_256B * 256 + va) >> 8; 870 } else { 871 tex_resource_words[3] = ((uint64_t)surflevel[base_level].offset_256B * 256 + va) >> 8; 872 } 873 874 last_layer = params->last_layer; 875 if (params->target != texture->target && depth == 1) { 876 last_layer = params->first_layer; 877 } 878 tex_resource_words[4] = (word4 | 879 S_030010_ENDIAN_SWAP(endian)); 880 tex_resource_words[5] = S_030014_BASE_ARRAY(params->first_layer) | 881 S_030014_LAST_ARRAY(last_layer); 882 tex_resource_words[6] = S_030018_TILE_SPLIT(tile_split); 883 884 if (texture->nr_samples > 1) { 885 unsigned log_samples = util_logbase2(texture->nr_samples); 886 if (rscreen->b.gfx_level == CAYMAN) { 887 tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples); 888 } 889 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */ 890 tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples); 891 tex_resource_words[6] |= S_030018_FMASK_BANK_HEIGHT(fmask_bankh); 892 } else { 893 bool no_mip = first_level == last_level; 894 895 tex_resource_words[4] |= S_030010_BASE_LEVEL(first_level); 896 tex_resource_words[5] |= S_030014_LAST_LEVEL(last_level); 897 /* aniso max 16 samples */ 898 tex_resource_words[6] |= S_030018_MAX_ANISO_RATIO(no_mip ? 0 : 4); 899 } 900 901 tex_resource_words[7] = S_03001C_DATA_FORMAT(format) | 902 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) | 903 S_03001C_BANK_WIDTH(bankw) | 904 S_03001C_BANK_HEIGHT(bankh) | 905 S_03001C_MACRO_TILE_ASPECT(macro_aspect) | 906 S_03001C_NUM_BANKS(nbanks) | 907 S_03001C_DEPTH_SAMPLE_ORDER(tmp->db_compatible); 908 return 0; 909} 910 911struct pipe_sampler_view * 912evergreen_create_sampler_view_custom(struct pipe_context *ctx, 913 struct pipe_resource *texture, 914 const struct pipe_sampler_view *state, 915 unsigned width0, unsigned height0, 916 unsigned force_level) 917{ 918 struct r600_context *rctx = (struct r600_context*)ctx; 919 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view); 920 struct r600_texture *tmp = (struct r600_texture*)texture; 921 struct eg_tex_res_params params; 922 int ret; 923 924 if (!view) 925 return NULL; 926 927 /* initialize base object */ 928 view->base = *state; 929 view->base.texture = NULL; 930 pipe_reference(NULL, &texture->reference); 931 view->base.texture = texture; 932 view->base.reference.count = 1; 933 view->base.context = ctx; 934 935 if (state->target == PIPE_BUFFER) 936 return texture_buffer_sampler_view(rctx, view, width0, height0); 937 938 memset(¶ms, 0, sizeof(params)); 939 params.pipe_format = state->format; 940 params.force_level = force_level; 941 params.width0 = width0; 942 params.height0 = height0; 943 params.first_level = state->u.tex.first_level; 944 params.last_level = state->u.tex.last_level; 945 params.first_layer = state->u.tex.first_layer; 946 params.last_layer = state->u.tex.last_layer; 947 params.target = state->target; 948 params.swizzle[0] = state->swizzle_r; 949 params.swizzle[1] = state->swizzle_g; 950 params.swizzle[2] = state->swizzle_b; 951 params.swizzle[3] = state->swizzle_a; 952 953 ret = evergreen_fill_tex_resource_words(rctx, texture, ¶ms, 954 &view->skip_mip_address_reloc, 955 view->tex_resource_words); 956 if (ret != 0) { 957 FREE(view); 958 return NULL; 959 } 960 961 if (state->format == PIPE_FORMAT_X24S8_UINT || 962 state->format == PIPE_FORMAT_S8X24_UINT || 963 state->format == PIPE_FORMAT_X32_S8X24_UINT || 964 state->format == PIPE_FORMAT_S8_UINT) 965 view->is_stencil_sampler = true; 966 967 view->tex_resource = &tmp->resource; 968 969 return &view->base; 970} 971 972static struct pipe_sampler_view * 973evergreen_create_sampler_view(struct pipe_context *ctx, 974 struct pipe_resource *tex, 975 const struct pipe_sampler_view *state) 976{ 977 return evergreen_create_sampler_view_custom(ctx, tex, state, 978 tex->width0, tex->height0, 0); 979} 980 981static void evergreen_emit_config_state(struct r600_context *rctx, struct r600_atom *atom) 982{ 983 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; 984 struct r600_config_state *a = (struct r600_config_state*)atom; 985 986 radeon_set_config_reg_seq(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 3); 987 if (a->dyn_gpr_enabled) { 988 radeon_emit(cs, S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs)); 989 radeon_emit(cs, 0); 990 radeon_emit(cs, 0); 991 } else { 992 radeon_emit(cs, a->sq_gpr_resource_mgmt_1); 993 radeon_emit(cs, a->sq_gpr_resource_mgmt_2); 994 radeon_emit(cs, a->sq_gpr_resource_mgmt_3); 995 } 996 radeon_set_config_reg(cs, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (a->dyn_gpr_enabled << 8)); 997 if (a->dyn_gpr_enabled) { 998 radeon_set_context_reg(cs, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1, 999 S_028838_PS_GPRS(0x1e) | 1000 S_028838_VS_GPRS(0x1e) | 1001 S_028838_GS_GPRS(0x1e) | 1002 S_028838_ES_GPRS(0x1e) | 1003 S_028838_HS_GPRS(0x1e) | 1004 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/ 1005 } 1006} 1007 1008static void evergreen_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom) 1009{ 1010 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; 1011 struct pipe_clip_state *state = &rctx->clip_state.state; 1012 1013 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP0_X, 6*4); 1014 radeon_emit_array(cs, (unsigned*)state, 6*4); 1015} 1016 1017static void evergreen_set_polygon_stipple(struct pipe_context *ctx, 1018 const struct pipe_poly_stipple *state) 1019{ 1020} 1021 1022static void evergreen_get_scissor_rect(struct r600_context *rctx, 1023 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y, 1024 uint32_t *tl, uint32_t *br) 1025{ 1026 struct pipe_scissor_state scissor = {tl_x, tl_y, br_x, br_y}; 1027 1028 evergreen_apply_scissor_bug_workaround(&rctx->b, &scissor); 1029 1030 *tl = S_028240_TL_X(scissor.minx) | S_028240_TL_Y(scissor.miny); 1031 *br = S_028244_BR_X(scissor.maxx) | S_028244_BR_Y(scissor.maxy); 1032} 1033 1034struct r600_tex_color_info { 1035 unsigned info; 1036 unsigned view; 1037 unsigned dim; 1038 unsigned pitch; 1039 unsigned slice; 1040 unsigned attrib; 1041 unsigned ntype; 1042 unsigned fmask; 1043 unsigned fmask_slice; 1044 uint64_t offset; 1045 boolean export_16bpc; 1046}; 1047 1048static void evergreen_set_color_surface_buffer(struct r600_context *rctx, 1049 struct r600_resource *res, 1050 enum pipe_format pformat, 1051 unsigned first_element, 1052 unsigned last_element, 1053 struct r600_tex_color_info *color) 1054{ 1055 unsigned format, swap, ntype, endian; 1056 const struct util_format_description *desc; 1057 unsigned block_size = util_format_get_blocksize(res->b.b.format); 1058 unsigned pitch_alignment = 1059 MAX2(64, rctx->screen->b.info.pipe_interleave_bytes / block_size); 1060 unsigned pitch = align(res->b.b.width0, pitch_alignment); 1061 int i; 1062 unsigned width_elements; 1063 1064 width_elements = last_element - first_element + 1; 1065 1066 format = r600_translate_colorformat(rctx->b.gfx_level, pformat, FALSE); 1067 swap = r600_translate_colorswap(pformat, FALSE); 1068 1069 endian = r600_colorformat_endian_swap(format, FALSE); 1070 1071 desc = util_format_description(pformat); 1072 for (i = 0; i < 4; i++) { 1073 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { 1074 break; 1075 } 1076 } 1077 ntype = V_028C70_NUMBER_UNORM; 1078 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) 1079 ntype = V_028C70_NUMBER_SRGB; 1080 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) { 1081 if (desc->channel[i].normalized) 1082 ntype = V_028C70_NUMBER_SNORM; 1083 else if (desc->channel[i].pure_integer) 1084 ntype = V_028C70_NUMBER_SINT; 1085 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) { 1086 if (desc->channel[i].normalized) 1087 ntype = V_028C70_NUMBER_UNORM; 1088 else if (desc->channel[i].pure_integer) 1089 ntype = V_028C70_NUMBER_UINT; 1090 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) { 1091 ntype = V_028C70_NUMBER_FLOAT; 1092 } 1093 1094 pitch = (pitch / 8) - 1; 1095 color->pitch = S_028C64_PITCH_TILE_MAX(pitch); 1096 1097 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED); 1098 color->info |= S_028C70_FORMAT(format) | 1099 S_028C70_COMP_SWAP(swap) | 1100 S_028C70_BLEND_CLAMP(0) | 1101 S_028C70_BLEND_BYPASS(1) | 1102 S_028C70_NUMBER_TYPE(ntype) | 1103 S_028C70_ENDIAN(endian); 1104 color->attrib = S_028C74_NON_DISP_TILING_ORDER(1); 1105 color->ntype = ntype; 1106 color->export_16bpc = false; 1107 color->dim = width_elements - 1; 1108 color->slice = 0; /* (width_elements / 64) - 1;*/ 1109 color->view = 0; 1110 color->offset = (res->gpu_address + first_element) >> 8; 1111 1112 color->fmask = color->offset; 1113 color->fmask_slice = 0; 1114} 1115 1116static void evergreen_set_color_surface_common(struct r600_context *rctx, 1117 struct r600_texture *rtex, 1118 unsigned level, 1119 unsigned first_layer, 1120 unsigned last_layer, 1121 enum pipe_format pformat, 1122 struct r600_tex_color_info *color) 1123{ 1124 struct r600_screen *rscreen = rctx->screen; 1125 unsigned pitch, slice; 1126 unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks; 1127 unsigned format, swap, ntype, endian; 1128 const struct util_format_description *desc; 1129 bool blend_clamp = 0, blend_bypass = 0, do_endian_swap = FALSE; 1130 int i; 1131 1132 color->offset = (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256; 1133 color->view = S_028C6C_SLICE_START(first_layer) | 1134 S_028C6C_SLICE_MAX(last_layer); 1135 1136 color->offset += rtex->resource.gpu_address; 1137 color->offset >>= 8; 1138 1139 color->dim = 0; 1140 pitch = (rtex->surface.u.legacy.level[level].nblk_x) / 8 - 1; 1141 slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64; 1142 if (slice) { 1143 slice = slice - 1; 1144 } 1145 1146 color->info = 0; 1147 switch (rtex->surface.u.legacy.level[level].mode) { 1148 default: 1149 case RADEON_SURF_MODE_LINEAR_ALIGNED: 1150 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED); 1151 non_disp_tiling = 1; 1152 break; 1153 case RADEON_SURF_MODE_1D: 1154 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1); 1155 non_disp_tiling = rtex->non_disp_tiling; 1156 break; 1157 case RADEON_SURF_MODE_2D: 1158 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1); 1159 non_disp_tiling = rtex->non_disp_tiling; 1160 break; 1161 } 1162 tile_split = rtex->surface.u.legacy.tile_split; 1163 macro_aspect = rtex->surface.u.legacy.mtilea; 1164 bankw = rtex->surface.u.legacy.bankw; 1165 bankh = rtex->surface.u.legacy.bankh; 1166 if (rtex->fmask.size) 1167 fmask_bankh = rtex->fmask.bank_height; 1168 else 1169 fmask_bankh = rtex->surface.u.legacy.bankh; 1170 tile_split = eg_tile_split(tile_split); 1171 macro_aspect = eg_macro_tile_aspect(macro_aspect); 1172 bankw = eg_bank_wh(bankw); 1173 bankh = eg_bank_wh(bankh); 1174 fmask_bankh = eg_bank_wh(fmask_bankh); 1175 1176 if (rscreen->b.gfx_level == CAYMAN) { 1177 if (util_format_get_blocksize(pformat) >= 16) 1178 non_disp_tiling = 1; 1179 } 1180 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks); 1181 desc = util_format_description(pformat); 1182 for (i = 0; i < 4; i++) { 1183 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { 1184 break; 1185 } 1186 } 1187 color->attrib = S_028C74_TILE_SPLIT(tile_split)| 1188 S_028C74_NUM_BANKS(nbanks) | 1189 S_028C74_BANK_WIDTH(bankw) | 1190 S_028C74_BANK_HEIGHT(bankh) | 1191 S_028C74_MACRO_TILE_ASPECT(macro_aspect) | 1192 S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling) | 1193 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh); 1194 1195 if (rctx->b.gfx_level == CAYMAN) { 1196 color->attrib |= S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == 1197 PIPE_SWIZZLE_1); 1198 1199 if (rtex->resource.b.b.nr_samples > 1) { 1200 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples); 1201 color->attrib |= S_028C74_NUM_SAMPLES(log_samples) | 1202 S_028C74_NUM_FRAGMENTS(log_samples); 1203 } 1204 } 1205 1206 ntype = V_028C70_NUMBER_UNORM; 1207 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) 1208 ntype = V_028C70_NUMBER_SRGB; 1209 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) { 1210 if (desc->channel[i].normalized) 1211 ntype = V_028C70_NUMBER_SNORM; 1212 else if (desc->channel[i].pure_integer) 1213 ntype = V_028C70_NUMBER_SINT; 1214 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) { 1215 if (desc->channel[i].normalized) 1216 ntype = V_028C70_NUMBER_UNORM; 1217 else if (desc->channel[i].pure_integer) 1218 ntype = V_028C70_NUMBER_UINT; 1219 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) { 1220 ntype = V_028C70_NUMBER_FLOAT; 1221 } 1222 1223 if (R600_BIG_ENDIAN) 1224 do_endian_swap = !rtex->db_compatible; 1225 1226 format = r600_translate_colorformat(rctx->b.gfx_level, pformat, do_endian_swap); 1227 assert(format != ~0); 1228 swap = r600_translate_colorswap(pformat, do_endian_swap); 1229 assert(swap != ~0); 1230 1231 endian = r600_colorformat_endian_swap(format, do_endian_swap); 1232 1233 /* blend clamp should be set for all NORM/SRGB types */ 1234 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM || 1235 ntype == V_028C70_NUMBER_SRGB) 1236 blend_clamp = 1; 1237 1238 /* set blend bypass according to docs if SINT/UINT or 1239 8/24 COLOR variants */ 1240 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT || 1241 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 || 1242 format == V_028C70_COLOR_X24_8_32_FLOAT) { 1243 blend_clamp = 0; 1244 blend_bypass = 1; 1245 } 1246 1247 color->ntype = ntype; 1248 color->info |= S_028C70_FORMAT(format) | 1249 S_028C70_COMP_SWAP(swap) | 1250 S_028C70_BLEND_CLAMP(blend_clamp) | 1251 S_028C70_BLEND_BYPASS(blend_bypass) | 1252 S_028C70_SIMPLE_FLOAT(1) | 1253 S_028C70_NUMBER_TYPE(ntype) | 1254 S_028C70_ENDIAN(endian); 1255 1256 if (rtex->fmask.size) { 1257 color->info |= S_028C70_COMPRESSION(1); 1258 } 1259 1260 /* EXPORT_NORM is an optimization that can be enabled for better 1261 * performance in certain cases. 1262 * EXPORT_NORM can be enabled if: 1263 * - 11-bit or smaller UNORM/SNORM/SRGB 1264 * - 16-bit or smaller FLOAT 1265 */ 1266 color->export_16bpc = false; 1267 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS && 1268 ((desc->channel[i].size < 12 && 1269 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT && 1270 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) || 1271 (desc->channel[i].size < 17 && 1272 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) { 1273 color->info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC); 1274 color->export_16bpc = true; 1275 } 1276 1277 color->pitch = S_028C64_PITCH_TILE_MAX(pitch); 1278 color->slice = S_028C68_SLICE_TILE_MAX(slice); 1279 1280 if (rtex->fmask.size) { 1281 color->fmask = (rtex->resource.gpu_address + rtex->fmask.offset) >> 8; 1282 color->fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max); 1283 } else { 1284 color->fmask = color->offset; 1285 color->fmask_slice = S_028C88_TILE_MAX(slice); 1286 } 1287} 1288 1289/** 1290 * This function initializes the CB* register values for RATs. It is meant 1291 * to be used for 1D aligned buffers that do not have an associated 1292 * radeon_surf. 1293 */ 1294void evergreen_init_color_surface_rat(struct r600_context *rctx, 1295 struct r600_surface *surf) 1296{ 1297 struct pipe_resource *pipe_buffer = surf->base.texture; 1298 struct r600_tex_color_info color; 1299 1300 evergreen_set_color_surface_buffer(rctx, (struct r600_resource *)surf->base.texture, 1301 surf->base.format, 0, pipe_buffer->width0, 1302 &color); 1303 1304 surf->cb_color_base = color.offset; 1305 surf->cb_color_dim = color.dim; 1306 surf->cb_color_info = color.info | S_028C70_RAT(1); 1307 surf->cb_color_pitch = color.pitch; 1308 surf->cb_color_slice = color.slice; 1309 surf->cb_color_view = color.view; 1310 surf->cb_color_attrib = color.attrib; 1311 surf->cb_color_fmask = color.fmask; 1312 surf->cb_color_fmask_slice = color.fmask_slice; 1313 1314 surf->cb_color_view = 0; 1315 1316 /* Set the buffer range the GPU will have access to: */ 1317 util_range_add(pipe_buffer, &r600_resource(pipe_buffer)->valid_buffer_range, 1318 0, pipe_buffer->width0); 1319} 1320 1321 1322void evergreen_init_color_surface(struct r600_context *rctx, 1323 struct r600_surface *surf) 1324{ 1325 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture; 1326 unsigned level = surf->base.u.tex.level; 1327 struct r600_tex_color_info color; 1328 1329 evergreen_set_color_surface_common(rctx, rtex, level, 1330 surf->base.u.tex.first_layer, 1331 surf->base.u.tex.last_layer, 1332 surf->base.format, 1333 &color); 1334 1335 surf->alphatest_bypass = color.ntype == V_028C70_NUMBER_UINT || 1336 color.ntype == V_028C70_NUMBER_SINT; 1337 surf->export_16bpc = color.export_16bpc; 1338 1339 /* XXX handle enabling of CB beyond BASE8 which has different offset */ 1340 surf->cb_color_base = color.offset; 1341 surf->cb_color_dim = color.dim; 1342 surf->cb_color_info = color.info; 1343 surf->cb_color_pitch = color.pitch; 1344 surf->cb_color_slice = color.slice; 1345 surf->cb_color_view = color.view; 1346 surf->cb_color_attrib = color.attrib; 1347 surf->cb_color_fmask = color.fmask; 1348 surf->cb_color_fmask_slice = color.fmask_slice; 1349 1350 surf->color_initialized = true; 1351} 1352 1353static void evergreen_init_depth_surface(struct r600_context *rctx, 1354 struct r600_surface *surf) 1355{ 1356 struct r600_screen *rscreen = rctx->screen; 1357 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture; 1358 unsigned level = surf->base.u.tex.level; 1359 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level]; 1360 uint64_t offset; 1361 unsigned format, array_mode; 1362 unsigned macro_aspect, tile_split, bankh, bankw, nbanks; 1363 1364 1365 format = r600_translate_dbformat(surf->base.format); 1366 assert(format != ~0); 1367 1368 offset = rtex->resource.gpu_address; 1369 offset += (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256; 1370 1371 switch (rtex->surface.u.legacy.level[level].mode) { 1372 case RADEON_SURF_MODE_2D: 1373 array_mode = V_028C70_ARRAY_2D_TILED_THIN1; 1374 break; 1375 case RADEON_SURF_MODE_1D: 1376 case RADEON_SURF_MODE_LINEAR_ALIGNED: 1377 default: 1378 array_mode = V_028C70_ARRAY_1D_TILED_THIN1; 1379 break; 1380 } 1381 tile_split = rtex->surface.u.legacy.tile_split; 1382 macro_aspect = rtex->surface.u.legacy.mtilea; 1383 bankw = rtex->surface.u.legacy.bankw; 1384 bankh = rtex->surface.u.legacy.bankh; 1385 tile_split = eg_tile_split(tile_split); 1386 macro_aspect = eg_macro_tile_aspect(macro_aspect); 1387 bankw = eg_bank_wh(bankw); 1388 bankh = eg_bank_wh(bankh); 1389 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks); 1390 offset >>= 8; 1391 1392 surf->db_z_info = S_028040_ARRAY_MODE(array_mode) | 1393 S_028040_FORMAT(format) | 1394 S_028040_TILE_SPLIT(tile_split)| 1395 S_028040_NUM_BANKS(nbanks) | 1396 S_028040_BANK_WIDTH(bankw) | 1397 S_028040_BANK_HEIGHT(bankh) | 1398 S_028040_MACRO_TILE_ASPECT(macro_aspect); 1399 if (rscreen->b.gfx_level == CAYMAN && rtex->resource.b.b.nr_samples > 1) { 1400 surf->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples)); 1401 } 1402 1403 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0); 1404 1405 surf->db_depth_base = offset; 1406 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) | 1407 S_028008_SLICE_MAX(surf->base.u.tex.last_layer); 1408 surf->db_depth_size = S_028058_PITCH_TILE_MAX(levelinfo->nblk_x / 8 - 1) | 1409 S_028058_HEIGHT_TILE_MAX(levelinfo->nblk_y / 8 - 1); 1410 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(levelinfo->nblk_x * 1411 levelinfo->nblk_y / 64 - 1); 1412 1413 if (rtex->surface.has_stencil) { 1414 uint64_t stencil_offset; 1415 unsigned stile_split = rtex->surface.u.legacy.stencil_tile_split; 1416 1417 stile_split = eg_tile_split(stile_split); 1418 1419 stencil_offset = (uint64_t)rtex->surface.u.legacy.zs.stencil_level[level].offset_256B * 256; 1420 stencil_offset += rtex->resource.gpu_address; 1421 1422 surf->db_stencil_base = stencil_offset >> 8; 1423 surf->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8) | 1424 S_028044_TILE_SPLIT(stile_split); 1425 } else { 1426 surf->db_stencil_base = offset; 1427 surf->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_INVALID); 1428 } 1429 1430 if (r600_htile_enabled(rtex, level)) { 1431 uint64_t va = rtex->resource.gpu_address + rtex->htile_offset; 1432 surf->db_htile_data_base = va >> 8; 1433 surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) | 1434 S_028ABC_HTILE_HEIGHT(1) | 1435 S_028ABC_FULL_CACHE(1); 1436 surf->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1); 1437 surf->db_preload_control = 0; 1438 } 1439 1440 surf->depth_initialized = true; 1441} 1442 1443static void evergreen_set_framebuffer_state(struct pipe_context *ctx, 1444 const struct pipe_framebuffer_state *state) 1445{ 1446 struct r600_context *rctx = (struct r600_context *)ctx; 1447 struct r600_surface *surf; 1448 struct r600_texture *rtex; 1449 uint32_t i, log_samples; 1450 uint32_t target_mask = 0; 1451 /* Flush TC when changing the framebuffer state, because the only 1452 * client not using TC that can change textures is the framebuffer. 1453 * Other places don't typically have to flush TC. 1454 */ 1455 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | 1456 R600_CONTEXT_FLUSH_AND_INV | 1457 R600_CONTEXT_FLUSH_AND_INV_CB | 1458 R600_CONTEXT_FLUSH_AND_INV_CB_META | 1459 R600_CONTEXT_FLUSH_AND_INV_DB | 1460 R600_CONTEXT_FLUSH_AND_INV_DB_META | 1461 R600_CONTEXT_INV_TEX_CACHE; 1462 1463 util_copy_framebuffer_state(&rctx->framebuffer.state, state); 1464 1465 /* Colorbuffers. */ 1466 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0; 1467 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] && 1468 util_format_is_pure_integer(state->cbufs[0]->format); 1469 rctx->framebuffer.compressed_cb_mask = 0; 1470 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state); 1471 1472 for (i = 0; i < state->nr_cbufs; i++) { 1473 surf = (struct r600_surface*)state->cbufs[i]; 1474 if (!surf) 1475 continue; 1476 1477 target_mask |= (0xf << (i * 4)); 1478 1479 rtex = (struct r600_texture*)surf->base.texture; 1480 1481 r600_context_add_resource_size(ctx, state->cbufs[i]->texture); 1482 1483 if (!surf->color_initialized) { 1484 evergreen_init_color_surface(rctx, surf); 1485 } 1486 1487 if (!surf->export_16bpc) { 1488 rctx->framebuffer.export_16bpc = false; 1489 } 1490 1491 if (rtex->fmask.size) { 1492 rctx->framebuffer.compressed_cb_mask |= 1 << i; 1493 } 1494 } 1495 1496 /* Update alpha-test state dependencies. 1497 * Alpha-test is done on the first colorbuffer only. */ 1498 if (state->nr_cbufs) { 1499 bool alphatest_bypass = false; 1500 bool export_16bpc = true; 1501 1502 surf = (struct r600_surface*)state->cbufs[0]; 1503 if (surf) { 1504 alphatest_bypass = surf->alphatest_bypass; 1505 export_16bpc = surf->export_16bpc; 1506 } 1507 1508 if (rctx->alphatest_state.bypass != alphatest_bypass) { 1509 rctx->alphatest_state.bypass = alphatest_bypass; 1510 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom); 1511 } 1512 if (rctx->alphatest_state.cb0_export_16bpc != export_16bpc) { 1513 rctx->alphatest_state.cb0_export_16bpc = export_16bpc; 1514 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom); 1515 } 1516 } 1517 1518 /* ZS buffer. */ 1519 if (state->zsbuf) { 1520 surf = (struct r600_surface*)state->zsbuf; 1521 1522 r600_context_add_resource_size(ctx, state->zsbuf->texture); 1523 1524 if (!surf->depth_initialized) { 1525 evergreen_init_depth_surface(rctx, surf); 1526 } 1527 1528 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) { 1529 rctx->poly_offset_state.zs_format = state->zsbuf->format; 1530 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom); 1531 } 1532 1533 if (rctx->db_state.rsurf != surf) { 1534 rctx->db_state.rsurf = surf; 1535 r600_mark_atom_dirty(rctx, &rctx->db_state.atom); 1536 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom); 1537 } 1538 } else if (rctx->db_state.rsurf) { 1539 rctx->db_state.rsurf = NULL; 1540 r600_mark_atom_dirty(rctx, &rctx->db_state.atom); 1541 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom); 1542 } 1543 1544 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs || 1545 rctx->cb_misc_state.bound_cbufs_target_mask != target_mask) { 1546 rctx->cb_misc_state.bound_cbufs_target_mask = target_mask; 1547 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs; 1548 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom); 1549 } 1550 1551 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) { 1552 rctx->alphatest_state.bypass = false; 1553 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom); 1554 } 1555 1556 log_samples = util_logbase2(rctx->framebuffer.nr_samples); 1557 /* This is for Cayman to program SAMPLE_RATE, and for RV770 to fix a hw bug. */ 1558 if ((rctx->b.gfx_level == CAYMAN || 1559 rctx->b.family == CHIP_RV770) && 1560 rctx->db_misc_state.log_samples != log_samples) { 1561 rctx->db_misc_state.log_samples = log_samples; 1562 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom); 1563 } 1564 1565 1566 /* Calculate the CS size. */ 1567 rctx->framebuffer.atom.num_dw = 4; /* SCISSOR */ 1568 1569 /* MSAA. */ 1570 if (rctx->b.gfx_level == EVERGREEN) 1571 rctx->framebuffer.atom.num_dw += 17; /* Evergreen */ 1572 else 1573 rctx->framebuffer.atom.num_dw += 28; /* Cayman */ 1574 1575 /* Colorbuffers. */ 1576 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 23; 1577 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2; 1578 rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3; 1579 1580 /* ZS buffer. */ 1581 if (state->zsbuf) { 1582 rctx->framebuffer.atom.num_dw += 24; 1583 rctx->framebuffer.atom.num_dw += 2; 1584 } else { 1585 rctx->framebuffer.atom.num_dw += 4; 1586 } 1587 1588 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom); 1589 1590 r600_set_sample_locations_constant_buffer(rctx); 1591 rctx->framebuffer.do_update_surf_dirtiness = true; 1592} 1593 1594static void evergreen_set_min_samples(struct pipe_context *ctx, unsigned min_samples) 1595{ 1596 struct r600_context *rctx = (struct r600_context *)ctx; 1597 1598 if (rctx->ps_iter_samples == min_samples) 1599 return; 1600 1601 rctx->ps_iter_samples = min_samples; 1602 if (rctx->framebuffer.nr_samples > 1) { 1603 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom); 1604 } 1605} 1606 1607/* 8xMSAA */ 1608static const uint32_t sample_locs_8x[] = { 1609 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3), 1610 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7), 1611 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3), 1612 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7), 1613 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3), 1614 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7), 1615 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3), 1616 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7), 1617}; 1618static unsigned max_dist_8x = 7; 1619 1620static void evergreen_get_sample_position(struct pipe_context *ctx, 1621 unsigned sample_count, 1622 unsigned sample_index, 1623 float *out_value) 1624{ 1625 int offset, index; 1626 struct { 1627 int idx:4; 1628 } val; 1629 switch (sample_count) { 1630 case 1: 1631 default: 1632 out_value[0] = out_value[1] = 0.5; 1633 break; 1634 case 2: 1635 offset = 4 * (sample_index * 2); 1636 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf; 1637 out_value[0] = (float)(val.idx + 8) / 16.0f; 1638 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf; 1639 out_value[1] = (float)(val.idx + 8) / 16.0f; 1640 break; 1641 case 4: 1642 offset = 4 * (sample_index * 2); 1643 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf; 1644 out_value[0] = (float)(val.idx + 8) / 16.0f; 1645 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf; 1646 out_value[1] = (float)(val.idx + 8) / 16.0f; 1647 break; 1648 case 8: 1649 offset = 4 * (sample_index % 4 * 2); 1650 index = (sample_index / 4); 1651 val.idx = (sample_locs_8x[index] >> offset) & 0xf; 1652 out_value[0] = (float)(val.idx + 8) / 16.0f; 1653 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf; 1654 out_value[1] = (float)(val.idx + 8) / 16.0f; 1655 break; 1656 } 1657} 1658 1659static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples, int ps_iter_samples) 1660{ 1661 1662 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; 1663 unsigned max_dist = 0; 1664 1665 switch (nr_samples) { 1666 default: 1667 nr_samples = 0; 1668 break; 1669 case 2: 1670 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(eg_sample_locs_2x)); 1671 radeon_emit_array(cs, eg_sample_locs_2x, ARRAY_SIZE(eg_sample_locs_2x)); 1672 max_dist = eg_max_dist_2x; 1673 break; 1674 case 4: 1675 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(eg_sample_locs_4x)); 1676 radeon_emit_array(cs, eg_sample_locs_4x, ARRAY_SIZE(eg_sample_locs_4x)); 1677 max_dist = eg_max_dist_4x; 1678 break; 1679 case 8: 1680 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(sample_locs_8x)); 1681 radeon_emit_array(cs, sample_locs_8x, ARRAY_SIZE(sample_locs_8x)); 1682 max_dist = max_dist_8x; 1683 break; 1684 } 1685 1686 if (nr_samples > 1) { 1687 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2); 1688 radeon_emit(cs, S_028C00_LAST_PIXEL(1) | 1689 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */ 1690 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) | 1691 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */ 1692 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1, 1693 EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) | 1694 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) | 1695 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1)); 1696 } else { 1697 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2); 1698 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */ 1699 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */ 1700 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1, 1701 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) | 1702 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1)); 1703 } 1704} 1705 1706static void evergreen_emit_image_state(struct r600_context *rctx, struct r600_atom *atom, 1707 int immed_id_base, int res_id_base, int offset, uint32_t pkt_flags) 1708{ 1709 struct r600_image_state *state = (struct r600_image_state *)atom; 1710 struct pipe_framebuffer_state *fb_state = &rctx->framebuffer.state; 1711 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; 1712 struct r600_texture *rtex; 1713 struct r600_resource *resource; 1714 int i; 1715 1716 for (i = 0; i < R600_MAX_IMAGES; i++) { 1717 struct r600_image_view *image = &state->views[i]; 1718 unsigned reloc, immed_reloc; 1719 int idx = i + offset; 1720 1721 if (!pkt_flags) 1722 idx += fb_state->nr_cbufs + (rctx->dual_src_blend ? 1 : 0); 1723 if (!image->base.resource) 1724 continue; 1725 1726 resource = (struct r600_resource *)image->base.resource; 1727 if (resource->b.b.target != PIPE_BUFFER) 1728 rtex = (struct r600_texture *)image->base.resource; 1729 else 1730 rtex = NULL; 1731 1732 reloc = radeon_add_to_buffer_list(&rctx->b, 1733 &rctx->b.gfx, 1734 resource, 1735 RADEON_USAGE_READWRITE | 1736 RADEON_PRIO_SHADER_RW_BUFFER); 1737 1738 immed_reloc = radeon_add_to_buffer_list(&rctx->b, 1739 &rctx->b.gfx, 1740 resource->immed_buffer, 1741 RADEON_USAGE_READWRITE | 1742 RADEON_PRIO_SHADER_RW_BUFFER); 1743 1744 if (pkt_flags) 1745 radeon_compute_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + idx * 0x3C, 13); 1746 else 1747 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + idx * 0x3C, 13); 1748 1749 radeon_emit(cs, image->cb_color_base); /* R_028C60_CB_COLOR0_BASE */ 1750 radeon_emit(cs, image->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */ 1751 radeon_emit(cs, image->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */ 1752 radeon_emit(cs, image->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */ 1753 radeon_emit(cs, image->cb_color_info); /* R_028C70_CB_COLOR0_INFO */ 1754 radeon_emit(cs, image->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */ 1755 radeon_emit(cs, image->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */ 1756 radeon_emit(cs, rtex ? rtex->cmask.base_address_reg : image->cb_color_base); /* R_028C7C_CB_COLOR0_CMASK */ 1757 radeon_emit(cs, rtex ? rtex->cmask.slice_tile_max : 0); /* R_028C80_CB_COLOR0_CMASK_SLICE */ 1758 radeon_emit(cs, image->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */ 1759 radeon_emit(cs, image->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */ 1760 radeon_emit(cs, rtex ? rtex->color_clear_value[0] : 0); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */ 1761 radeon_emit(cs, rtex ? rtex->color_clear_value[1] : 0); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */ 1762 1763 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */ 1764 radeon_emit(cs, reloc); 1765 1766 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */ 1767 radeon_emit(cs, reloc); 1768 1769 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */ 1770 radeon_emit(cs, reloc); 1771 1772 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */ 1773 radeon_emit(cs, reloc); 1774 1775 if (pkt_flags) 1776 radeon_compute_set_context_reg(cs, R_028B9C_CB_IMMED0_BASE + (idx * 4), resource->immed_buffer->gpu_address >> 8); 1777 else 1778 radeon_set_context_reg(cs, R_028B9C_CB_IMMED0_BASE + (idx * 4), resource->immed_buffer->gpu_address >> 8); 1779 1780 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /**/ 1781 radeon_emit(cs, immed_reloc); 1782 1783 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags); 1784 radeon_emit(cs, (immed_id_base + i + offset) * 8); 1785 radeon_emit_array(cs, image->immed_resource_words, 8); 1786 1787 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags); 1788 radeon_emit(cs, immed_reloc); 1789 1790 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags); 1791 radeon_emit(cs, (res_id_base + i + offset) * 8); 1792 radeon_emit_array(cs, image->resource_words, 8); 1793 1794 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags); 1795 radeon_emit(cs, reloc); 1796 1797 if (!image->skip_mip_address_reloc) { 1798 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags); 1799 radeon_emit(cs, reloc); 1800 } 1801 } 1802} 1803 1804static void evergreen_emit_fragment_image_state(struct r600_context *rctx, struct r600_atom *atom) 1805{ 1806 evergreen_emit_image_state(rctx, atom, 1807 R600_IMAGE_IMMED_RESOURCE_OFFSET, 1808 R600_IMAGE_REAL_RESOURCE_OFFSET, 0, 0); 1809} 1810 1811static void evergreen_emit_compute_image_state(struct r600_context *rctx, struct r600_atom *atom) 1812{ 1813 evergreen_emit_image_state(rctx, atom, 1814 EG_FETCH_CONSTANTS_OFFSET_CS + R600_IMAGE_IMMED_RESOURCE_OFFSET, 1815 EG_FETCH_CONSTANTS_OFFSET_CS + R600_IMAGE_REAL_RESOURCE_OFFSET, 1816 0, RADEON_CP_PACKET3_COMPUTE_MODE); 1817} 1818 1819static void evergreen_emit_fragment_buffer_state(struct r600_context *rctx, struct r600_atom *atom) 1820{ 1821 int offset = util_bitcount(rctx->fragment_images.enabled_mask); 1822 evergreen_emit_image_state(rctx, atom, 1823 R600_IMAGE_IMMED_RESOURCE_OFFSET, 1824 R600_IMAGE_REAL_RESOURCE_OFFSET, offset, 0); 1825} 1826 1827static void evergreen_emit_compute_buffer_state(struct r600_context *rctx, struct r600_atom *atom) 1828{ 1829 int offset = util_bitcount(rctx->compute_images.enabled_mask); 1830 evergreen_emit_image_state(rctx, atom, 1831 EG_FETCH_CONSTANTS_OFFSET_CS + R600_IMAGE_IMMED_RESOURCE_OFFSET, 1832 EG_FETCH_CONSTANTS_OFFSET_CS + R600_IMAGE_REAL_RESOURCE_OFFSET, 1833 offset, RADEON_CP_PACKET3_COMPUTE_MODE); 1834} 1835 1836static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom) 1837{ 1838 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; 1839 struct pipe_framebuffer_state *state = &rctx->framebuffer.state; 1840 unsigned nr_cbufs = state->nr_cbufs; 1841 unsigned i, tl, br; 1842 struct r600_texture *tex = NULL; 1843 struct r600_surface *cb = NULL; 1844 1845 /* XXX support more colorbuffers once we need them */ 1846 assert(nr_cbufs <= 8); 1847 if (nr_cbufs > 8) 1848 nr_cbufs = 8; 1849 1850 /* Colorbuffers. */ 1851 for (i = 0; i < nr_cbufs; i++) { 1852 unsigned reloc, cmask_reloc; 1853 1854 cb = (struct r600_surface*)state->cbufs[i]; 1855 if (!cb) { 1856 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 1857 S_028C70_FORMAT(V_028C70_COLOR_INVALID)); 1858 continue; 1859 } 1860 1861 tex = (struct r600_texture *)cb->base.texture; 1862 reloc = radeon_add_to_buffer_list(&rctx->b, 1863 &rctx->b.gfx, 1864 (struct r600_resource*)cb->base.texture, 1865 RADEON_USAGE_READWRITE | 1866 (tex->resource.b.b.nr_samples > 1 ? 1867 RADEON_PRIO_COLOR_BUFFER_MSAA : 1868 RADEON_PRIO_COLOR_BUFFER)); 1869 1870 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) { 1871 cmask_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, 1872 tex->cmask_buffer, RADEON_USAGE_READWRITE | RADEON_PRIO_SEPARATE_META); 1873 } else { 1874 cmask_reloc = reloc; 1875 } 1876 1877 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13); 1878 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */ 1879 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */ 1880 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */ 1881 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */ 1882 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */ 1883 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */ 1884 radeon_emit(cs, cb->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */ 1885 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */ 1886 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */ 1887 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */ 1888 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */ 1889 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */ 1890 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */ 1891 1892 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */ 1893 radeon_emit(cs, reloc); 1894 1895 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */ 1896 radeon_emit(cs, reloc); 1897 1898 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */ 1899 radeon_emit(cs, cmask_reloc); 1900 1901 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */ 1902 radeon_emit(cs, reloc); 1903 } 1904 /* set CB_COLOR1_INFO for possible dual-src blending */ 1905 if (rctx->framebuffer.dual_src_blend && i == 1 && state->cbufs[0]) { 1906 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C, 1907 cb->cb_color_info | tex->cb_color_info); 1908 i++; 1909 } 1910 i += util_bitcount(rctx->fragment_images.enabled_mask); 1911 i += util_bitcount(rctx->fragment_buffers.enabled_mask); 1912 for (; i < 8 ; i++) 1913 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0); 1914 for (; i < 12; i++) 1915 radeon_set_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0); 1916 1917 /* ZS buffer. */ 1918 if (state->zsbuf) { 1919 struct r600_surface *zb = (struct r600_surface*)state->zsbuf; 1920 unsigned reloc = radeon_add_to_buffer_list(&rctx->b, 1921 &rctx->b.gfx, 1922 (struct r600_resource*)state->zsbuf->texture, 1923 RADEON_USAGE_READWRITE | 1924 (zb->base.texture->nr_samples > 1 ? 1925 RADEON_PRIO_DEPTH_BUFFER_MSAA : 1926 RADEON_PRIO_DEPTH_BUFFER)); 1927 1928 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view); 1929 1930 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 8); 1931 radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */ 1932 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */ 1933 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */ 1934 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */ 1935 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */ 1936 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */ 1937 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */ 1938 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */ 1939 1940 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028048_DB_Z_READ_BASE */ 1941 radeon_emit(cs, reloc); 1942 1943 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */ 1944 radeon_emit(cs, reloc); 1945 1946 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */ 1947 radeon_emit(cs, reloc); 1948 1949 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */ 1950 radeon_emit(cs, reloc); 1951 } else { 1952 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2); 1953 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */ 1954 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */ 1955 } 1956 1957 /* Framebuffer dimensions. */ 1958 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br); 1959 1960 radeon_set_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2); 1961 radeon_emit(cs, tl); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */ 1962 radeon_emit(cs, br); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */ 1963 1964 if (rctx->b.gfx_level == EVERGREEN) { 1965 evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples, rctx->ps_iter_samples); 1966 } else { 1967 cayman_emit_msaa_state(cs, rctx->framebuffer.nr_samples, 1968 rctx->ps_iter_samples, 0); 1969 } 1970} 1971 1972static void evergreen_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a) 1973{ 1974 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; 1975 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a; 1976 float offset_units = state->offset_units; 1977 float offset_scale = state->offset_scale; 1978 uint32_t pa_su_poly_offset_db_fmt_cntl = 0; 1979 1980 if (!state->offset_units_unscaled) { 1981 switch (state->zs_format) { 1982 case PIPE_FORMAT_Z24X8_UNORM: 1983 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 1984 case PIPE_FORMAT_X8Z24_UNORM: 1985 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 1986 offset_units *= 2.0f; 1987 pa_su_poly_offset_db_fmt_cntl = 1988 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24); 1989 break; 1990 case PIPE_FORMAT_Z16_UNORM: 1991 offset_units *= 4.0f; 1992 pa_su_poly_offset_db_fmt_cntl = 1993 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16); 1994 break; 1995 default: 1996 pa_su_poly_offset_db_fmt_cntl = 1997 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) | 1998 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1); 1999 } 2000 } 2001 2002 radeon_set_context_reg_seq(cs, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 4); 2003 radeon_emit(cs, fui(offset_scale)); 2004 radeon_emit(cs, fui(offset_units)); 2005 radeon_emit(cs, fui(offset_scale)); 2006 radeon_emit(cs, fui(offset_units)); 2007 2008 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 2009 pa_su_poly_offset_db_fmt_cntl); 2010} 2011 2012uint32_t evergreen_construct_rat_mask(struct r600_context *rctx, struct r600_cb_misc_state *a, 2013 unsigned nr_cbufs) 2014{ 2015 unsigned base_mask = 0; 2016 unsigned dirty_mask = a->image_rat_enabled_mask; 2017 while (dirty_mask) { 2018 unsigned idx = u_bit_scan(&dirty_mask); 2019 base_mask |= (0xf << (idx * 4)); 2020 } 2021 unsigned offset = util_last_bit(a->image_rat_enabled_mask); 2022 dirty_mask = a->buffer_rat_enabled_mask; 2023 while (dirty_mask) { 2024 unsigned idx = u_bit_scan(&dirty_mask); 2025 base_mask |= (0xf << (idx + offset) * 4); 2026 } 2027 return base_mask << (nr_cbufs * 4); 2028} 2029 2030static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom) 2031{ 2032 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; 2033 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom; 2034 unsigned fb_colormask = a->bound_cbufs_target_mask; 2035 unsigned ps_colormask = a->ps_color_export_mask; 2036 unsigned rat_colormask = evergreen_construct_rat_mask(rctx, a, a->nr_cbufs); 2037 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2); 2038 radeon_emit(cs, (a->blend_colormask & fb_colormask) | rat_colormask); /* R_028238_CB_TARGET_MASK */ 2039 /* This must match the used export instructions exactly. 2040 * Other values may lead to undefined behavior and hangs. 2041 */ 2042 radeon_emit(cs, ps_colormask); /* R_02823C_CB_SHADER_MASK */ 2043} 2044 2045static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom *atom) 2046{ 2047 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; 2048 struct r600_db_state *a = (struct r600_db_state*)atom; 2049 2050 if (a->rsurf && a->rsurf->db_htile_surface) { 2051 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture; 2052 unsigned reloc_idx; 2053 2054 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value)); 2055 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface); 2056 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control); 2057 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base); 2058 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, &rtex->resource, 2059 RADEON_USAGE_READWRITE | RADEON_PRIO_SEPARATE_META); 2060 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); 2061 radeon_emit(cs, reloc_idx); 2062 } else { 2063 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, 0); 2064 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0); 2065 } 2066} 2067 2068static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom) 2069{ 2070 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; 2071 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom; 2072 unsigned db_render_control = 0; 2073 unsigned db_count_control = 0; 2074 unsigned db_render_override = 2075 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) | 2076 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE); 2077 2078 if (rctx->b.num_occlusion_queries > 0 && 2079 !a->occlusion_queries_disabled) { 2080 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1); 2081 if (rctx->b.gfx_level == CAYMAN) { 2082 db_count_control |= S_028004_SAMPLE_RATE(a->log_samples); 2083 } 2084 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1); 2085 } else { 2086 db_count_control |= S_028004_ZPASS_INCREMENT_DISABLE(1); 2087 } 2088 2089 /* This is to fix a lockup when hyperz and alpha test are enabled at 2090 * the same time somehow GPU get confuse on which order to pick for 2091 * z test 2092 */ 2093 if (rctx->alphatest_state.sx_alpha_test_control) 2094 db_render_override |= S_02800C_FORCE_SHADER_Z_ORDER(1); 2095 2096 if (a->flush_depthstencil_through_cb) { 2097 assert(a->copy_depth || a->copy_stencil); 2098 2099 db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) | 2100 S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) | 2101 S_028000_COPY_CENTROID(1) | 2102 S_028000_COPY_SAMPLE(a->copy_sample); 2103 } else if (a->flush_depth_inplace || a->flush_stencil_inplace) { 2104 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) | 2105 S_028000_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace); 2106 db_render_override |= S_02800C_DISABLE_PIXEL_RATE_TILES(1); 2107 } 2108 if (a->htile_clear) { 2109 /* FIXME we might want to disable cliprect here */ 2110 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(1); 2111 } 2112 2113 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2); 2114 radeon_emit(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */ 2115 radeon_emit(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */ 2116 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override); 2117 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control); 2118} 2119 2120static void evergreen_emit_vertex_buffers(struct r600_context *rctx, 2121 struct r600_vertexbuf_state *state, 2122 unsigned resource_offset, 2123 unsigned pkt_flags) 2124{ 2125 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; 2126 uint32_t dirty_mask = state->dirty_mask; 2127 2128 while (dirty_mask) { 2129 struct pipe_vertex_buffer *vb; 2130 struct r600_resource *rbuffer; 2131 uint64_t va; 2132 unsigned buffer_index = u_bit_scan(&dirty_mask); 2133 2134 vb = &state->vb[buffer_index]; 2135 rbuffer = (struct r600_resource*)vb->buffer.resource; 2136 assert(rbuffer); 2137 2138 va = rbuffer->gpu_address + vb->buffer_offset; 2139 2140 /* fetch resources start at index 992 */ 2141 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags); 2142 radeon_emit(cs, (resource_offset + buffer_index) * 8); 2143 radeon_emit(cs, va); /* RESOURCEi_WORD0 */ 2144 radeon_emit(cs, rbuffer->b.b.width0 - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */ 2145 radeon_emit(cs, /* RESOURCEi_WORD2 */ 2146 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) | 2147 S_030008_STRIDE(vb->stride) | 2148 S_030008_BASE_ADDRESS_HI(va >> 32UL)); 2149 radeon_emit(cs, /* RESOURCEi_WORD3 */ 2150 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) | 2151 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) | 2152 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) | 2153 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W)); 2154 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */ 2155 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */ 2156 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */ 2157 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD7 */ 2158 2159 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags); 2160 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer, 2161 RADEON_USAGE_READ | RADEON_PRIO_VERTEX_BUFFER)); 2162 } 2163 state->dirty_mask = 0; 2164} 2165 2166static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom) 2167{ 2168 evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_FS, 0); 2169} 2170 2171static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom) 2172{ 2173 evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_CS, 2174 RADEON_CP_PACKET3_COMPUTE_MODE); 2175} 2176 2177static void evergreen_emit_constant_buffers(struct r600_context *rctx, 2178 struct r600_constbuf_state *state, 2179 unsigned buffer_id_base, 2180 unsigned reg_alu_constbuf_size, 2181 unsigned reg_alu_const_cache, 2182 unsigned pkt_flags) 2183{ 2184 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; 2185 uint32_t dirty_mask = state->dirty_mask; 2186 2187 while (dirty_mask) { 2188 struct pipe_constant_buffer *cb; 2189 struct r600_resource *rbuffer; 2190 uint64_t va; 2191 unsigned buffer_index = ffs(dirty_mask) - 1; 2192 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER); 2193 2194 cb = &state->cb[buffer_index]; 2195 rbuffer = (struct r600_resource*)cb->buffer; 2196 assert(rbuffer); 2197 2198 va = rbuffer->gpu_address + cb->buffer_offset; 2199 2200 if (buffer_index < R600_MAX_HW_CONST_BUFFERS) { 2201 radeon_set_context_reg_flag(cs, reg_alu_constbuf_size + buffer_index * 4, 2202 DIV_ROUND_UP(cb->buffer_size, 256), pkt_flags); 2203 radeon_set_context_reg_flag(cs, reg_alu_const_cache + buffer_index * 4, va >> 8, 2204 pkt_flags); 2205 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags); 2206 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer, 2207 RADEON_USAGE_READ | RADEON_PRIO_CONST_BUFFER)); 2208 } 2209 2210 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags); 2211 radeon_emit(cs, (buffer_id_base + buffer_index) * 8); 2212 radeon_emit(cs, va); /* RESOURCEi_WORD0 */ 2213 radeon_emit(cs, cb->buffer_size -1); /* RESOURCEi_WORD1 */ 2214 radeon_emit(cs, /* RESOURCEi_WORD2 */ 2215 S_030008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) | 2216 S_030008_STRIDE(gs_ring_buffer ? 4 : 16) | 2217 S_030008_BASE_ADDRESS_HI(va >> 32UL) | 2218 S_030008_DATA_FORMAT(FMT_32_32_32_32_FLOAT)); 2219 radeon_emit(cs, /* RESOURCEi_WORD3 */ 2220 S_03000C_UNCACHED(gs_ring_buffer ? 1 : 0) | 2221 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) | 2222 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) | 2223 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) | 2224 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W)); 2225 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */ 2226 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */ 2227 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */ 2228 radeon_emit(cs, /* RESOURCEi_WORD7 */ 2229 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER)); 2230 2231 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags); 2232 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer, 2233 RADEON_USAGE_READ | RADEON_PRIO_CONST_BUFFER)); 2234 2235 dirty_mask &= ~(1 << buffer_index); 2236 } 2237 state->dirty_mask = 0; 2238} 2239 2240/* VS constants can be in VS/ES (same space) or LS if tess is enabled */ 2241static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom) 2242{ 2243 if (rctx->vs_shader->current->shader.vs_as_ls) { 2244 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], 2245 EG_FETCH_CONSTANTS_OFFSET_LS, 2246 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 2247 R_028F40_ALU_CONST_CACHE_LS_0, 2248 0 /* PKT3 flags */); 2249 } else { 2250 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], 2251 EG_FETCH_CONSTANTS_OFFSET_VS, 2252 R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 2253 R_028980_ALU_CONST_CACHE_VS_0, 2254 0 /* PKT3 flags */); 2255 } 2256} 2257 2258static void evergreen_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom) 2259{ 2260 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY], 2261 EG_FETCH_CONSTANTS_OFFSET_GS, 2262 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 2263 R_0289C0_ALU_CONST_CACHE_GS_0, 2264 0 /* PKT3 flags */); 2265} 2266 2267static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom) 2268{ 2269 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT], 2270 EG_FETCH_CONSTANTS_OFFSET_PS, 2271 R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 2272 R_028940_ALU_CONST_CACHE_PS_0, 2273 0 /* PKT3 flags */); 2274} 2275 2276static void evergreen_emit_cs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom) 2277{ 2278 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE], 2279 EG_FETCH_CONSTANTS_OFFSET_CS, 2280 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 2281 R_028F40_ALU_CONST_CACHE_LS_0, 2282 RADEON_CP_PACKET3_COMPUTE_MODE); 2283} 2284 2285/* tes constants can be emitted to VS or ES - which are common */ 2286static void evergreen_emit_tes_constant_buffers(struct r600_context *rctx, struct r600_atom *atom) 2287{ 2288 if (!rctx->tes_shader) 2289 return; 2290 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL], 2291 EG_FETCH_CONSTANTS_OFFSET_VS, 2292 R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 2293 R_028980_ALU_CONST_CACHE_VS_0, 2294 0); 2295} 2296 2297static void evergreen_emit_tcs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom) 2298{ 2299 if (!rctx->tes_shader) 2300 return; 2301 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL], 2302 EG_FETCH_CONSTANTS_OFFSET_HS, 2303 R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 2304 R_028F00_ALU_CONST_CACHE_HS_0, 2305 0); 2306} 2307 2308void evergreen_setup_scratch_buffers(struct r600_context *rctx) { 2309 static const struct { 2310 unsigned ring_base; 2311 unsigned item_size; 2312 unsigned ring_size; 2313 } regs[EG_NUM_HW_STAGES] = { 2314 [R600_HW_STAGE_PS] = { R_008C68_SQ_PSTMP_RING_BASE, R_028914_SQ_PSTMP_RING_ITEMSIZE, R_008C6C_SQ_PSTMP_RING_SIZE }, 2315 [R600_HW_STAGE_VS] = { R_008C60_SQ_VSTMP_RING_BASE, R_028910_SQ_VSTMP_RING_ITEMSIZE, R_008C64_SQ_VSTMP_RING_SIZE }, 2316 [R600_HW_STAGE_GS] = { R_008C58_SQ_GSTMP_RING_BASE, R_02890C_SQ_GSTMP_RING_ITEMSIZE, R_008C5C_SQ_GSTMP_RING_SIZE }, 2317 [R600_HW_STAGE_ES] = { R_008C50_SQ_ESTMP_RING_BASE, R_028908_SQ_ESTMP_RING_ITEMSIZE, R_008C54_SQ_ESTMP_RING_SIZE }, 2318 [EG_HW_STAGE_LS] = { R_008E10_SQ_LSTMP_RING_BASE, R_028830_SQ_LSTMP_RING_ITEMSIZE, R_008E14_SQ_LSTMP_RING_SIZE }, 2319 [EG_HW_STAGE_HS] = { R_008E18_SQ_HSTMP_RING_BASE, R_028834_SQ_HSTMP_RING_ITEMSIZE, R_008E1C_SQ_HSTMP_RING_SIZE } 2320 }; 2321 2322 for (unsigned i = 0; i < EG_NUM_HW_STAGES; i++) { 2323 struct r600_pipe_shader *stage = rctx->hw_shader_stages[i].shader; 2324 2325 if (stage && unlikely(stage->scratch_space_needed)) { 2326 r600_setup_scratch_area_for_shader(rctx, stage, 2327 &rctx->scratch_buffers[i], regs[i].ring_base, regs[i].item_size, regs[i].ring_size); 2328 } 2329 } 2330} 2331 2332static void evergreen_emit_sampler_views(struct r600_context *rctx, 2333 struct r600_samplerview_state *state, 2334 unsigned resource_id_base, unsigned pkt_flags) 2335{ 2336 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; 2337 uint32_t dirty_mask = state->dirty_mask; 2338 2339 while (dirty_mask) { 2340 struct r600_pipe_sampler_view *rview; 2341 unsigned resource_index = u_bit_scan(&dirty_mask); 2342 unsigned reloc; 2343 2344 rview = state->views[resource_index]; 2345 assert(rview); 2346 2347 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags); 2348 radeon_emit(cs, (resource_id_base + resource_index) * 8); 2349 radeon_emit_array(cs, rview->tex_resource_words, 8); 2350 2351 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource, 2352 RADEON_USAGE_READ | 2353 r600_get_sampler_view_priority(rview->tex_resource)); 2354 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags); 2355 radeon_emit(cs, reloc); 2356 2357 if (!rview->skip_mip_address_reloc) { 2358 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags); 2359 radeon_emit(cs, reloc); 2360 } 2361 } 2362 state->dirty_mask = 0; 2363} 2364 2365static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom) 2366{ 2367 if (rctx->vs_shader->current->shader.vs_as_ls) { 2368 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, 2369 EG_FETCH_CONSTANTS_OFFSET_LS + R600_MAX_CONST_BUFFERS, 0); 2370 } else { 2371 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, 2372 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0); 2373 } 2374} 2375 2376static void evergreen_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom) 2377{ 2378 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, 2379 EG_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS, 0); 2380} 2381 2382static void evergreen_emit_tcs_sampler_views(struct r600_context *rctx, struct r600_atom *atom) 2383{ 2384 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views, 2385 EG_FETCH_CONSTANTS_OFFSET_HS + R600_MAX_CONST_BUFFERS, 0); 2386} 2387 2388static void evergreen_emit_tes_sampler_views(struct r600_context *rctx, struct r600_atom *atom) 2389{ 2390 if (!rctx->tes_shader) 2391 return; 2392 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views, 2393 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0); 2394} 2395 2396static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom) 2397{ 2398 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, 2399 EG_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS, 0); 2400} 2401 2402static void evergreen_emit_cs_sampler_views(struct r600_context *rctx, struct r600_atom *atom) 2403{ 2404 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views, 2405 EG_FETCH_CONSTANTS_OFFSET_CS + R600_MAX_CONST_BUFFERS, RADEON_CP_PACKET3_COMPUTE_MODE); 2406} 2407 2408static void evergreen_convert_border_color(union pipe_color_union *in, 2409 union pipe_color_union *out, 2410 enum pipe_format format) 2411{ 2412 if (util_format_is_pure_integer(format) && 2413 !util_format_is_depth_or_stencil(format)) { 2414 const struct util_format_description *d = util_format_description(format); 2415 2416 for (int i = 0; i < d->nr_channels; ++i) { 2417 int cs = d->channel[i].size; 2418 if (d->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) 2419 out->f[i] = (double)(in->i[i]) / ((1ul << (cs - 1)) - 1 ); 2420 else if (d->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) 2421 out->f[i] = (double)(in->ui[i]) / ((1ul << cs) - 1 ); 2422 else 2423 out->f[i] = 0; 2424 } 2425 2426 } else { 2427 switch (format) { 2428 case PIPE_FORMAT_X24S8_UINT: 2429 case PIPE_FORMAT_X32_S8X24_UINT: 2430 out->f[0] = (double)(in->ui[0]) / 255.0; 2431 out->f[1] = out->f[2] = out->f[3] = 0.0f; 2432 break; 2433 default: 2434 memcpy(out->f, in->f, 4 * sizeof(float)); 2435 } 2436 } 2437} 2438 2439static void evergreen_emit_sampler_states(struct r600_context *rctx, 2440 struct r600_textures_info *texinfo, 2441 unsigned resource_id_base, 2442 unsigned border_index_reg, 2443 unsigned pkt_flags) 2444{ 2445 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; 2446 uint32_t dirty_mask = texinfo->states.dirty_mask; 2447 union pipe_color_union border_color = {{0,0,0,1}}; 2448 union pipe_color_union *border_color_ptr = &border_color; 2449 2450 while (dirty_mask) { 2451 struct r600_pipe_sampler_state *rstate; 2452 unsigned i = u_bit_scan(&dirty_mask); 2453 2454 rstate = texinfo->states.states[i]; 2455 assert(rstate); 2456 2457 if (rstate->border_color_use) { 2458 struct r600_pipe_sampler_view *rview = texinfo->views.views[i]; 2459 if (rview) { 2460 evergreen_convert_border_color(&rstate->border_color, 2461 &border_color, rview->base.format); 2462 } else { 2463 border_color_ptr = &rstate->border_color; 2464 } 2465 } 2466 2467 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0) | pkt_flags); 2468 radeon_emit(cs, (resource_id_base + i) * 3); 2469 radeon_emit_array(cs, rstate->tex_sampler_words, 3); 2470 2471 if (rstate->border_color_use) { 2472 radeon_set_config_reg_seq(cs, border_index_reg, 5); 2473 radeon_emit(cs, i); 2474 radeon_emit_array(cs, border_color_ptr->ui, 4); 2475 } 2476 } 2477 texinfo->states.dirty_mask = 0; 2478} 2479 2480static void evergreen_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom) 2481{ 2482 if (rctx->vs_shader->current->shader.vs_as_ls) { 2483 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 72, 2484 R_00A450_TD_LS_SAMPLER0_BORDER_COLOR_INDEX, 0); 2485 } else { 2486 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, 2487 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0); 2488 } 2489} 2490 2491static void evergreen_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom) 2492{ 2493 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, 2494 R_00A428_TD_GS_SAMPLER0_BORDER_INDEX, 0); 2495} 2496 2497static void evergreen_emit_tcs_sampler_states(struct r600_context *rctx, struct r600_atom *atom) 2498{ 2499 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL], 54, 2500 R_00A43C_TD_HS_SAMPLER0_BORDER_COLOR_INDEX, 0); 2501} 2502 2503static void evergreen_emit_tes_sampler_states(struct r600_context *rctx, struct r600_atom *atom) 2504{ 2505 if (!rctx->tes_shader) 2506 return; 2507 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL], 18, 2508 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0); 2509} 2510 2511static void evergreen_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom) 2512{ 2513 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, 2514 R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0); 2515} 2516 2517static void evergreen_emit_cs_sampler_states(struct r600_context *rctx, struct r600_atom *atom) 2518{ 2519 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE], 90, 2520 R_00A464_TD_CS_SAMPLER0_BORDER_INDEX, 2521 RADEON_CP_PACKET3_COMPUTE_MODE); 2522} 2523 2524static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a) 2525{ 2526 struct r600_sample_mask *s = (struct r600_sample_mask*)a; 2527 uint8_t mask = s->sample_mask; 2528 2529 radeon_set_context_reg(&rctx->b.gfx.cs, R_028C3C_PA_SC_AA_MASK, 2530 mask | (mask << 8) | (mask << 16) | (mask << 24)); 2531} 2532 2533static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a) 2534{ 2535 struct r600_sample_mask *s = (struct r600_sample_mask*)a; 2536 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; 2537 uint16_t mask = s->sample_mask; 2538 2539 radeon_set_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2); 2540 radeon_emit(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */ 2541 radeon_emit(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */ 2542} 2543 2544static void evergreen_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a) 2545{ 2546 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; 2547 struct r600_cso_state *state = (struct r600_cso_state*)a; 2548 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso; 2549 2550 if (!shader) 2551 return; 2552 2553 radeon_set_context_reg(cs, R_0288A4_SQ_PGM_START_FS, 2554 (shader->buffer->gpu_address + shader->offset) >> 8); 2555 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); 2556 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer, 2557 RADEON_USAGE_READ | 2558 RADEON_PRIO_SHADER_BINARY)); 2559} 2560 2561static void evergreen_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a) 2562{ 2563 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; 2564 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a; 2565 2566 uint32_t v = 0, v2 = 0, primid = 0, tf_param = 0; 2567 2568 if (rctx->vs_shader->current->shader.vs_as_gs_a) { 2569 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A); 2570 primid = 1; 2571 } 2572 2573 if (state->geom_enable) { 2574 uint32_t cut_val; 2575 2576 if (rctx->gs_shader->gs_max_out_vertices <= 128) 2577 cut_val = V_028A40_GS_CUT_128; 2578 else if (rctx->gs_shader->gs_max_out_vertices <= 256) 2579 cut_val = V_028A40_GS_CUT_256; 2580 else if (rctx->gs_shader->gs_max_out_vertices <= 512) 2581 cut_val = V_028A40_GS_CUT_512; 2582 else 2583 cut_val = V_028A40_GS_CUT_1024; 2584 2585 v = S_028B54_GS_EN(1) | 2586 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER); 2587 if (!rctx->tes_shader) 2588 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL); 2589 2590 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) | 2591 S_028A40_CUT_MODE(cut_val); 2592 2593 if (rctx->gs_shader->current->shader.gs_prim_id_input) 2594 primid = 1; 2595 } 2596 2597 if (rctx->tes_shader) { 2598 uint32_t type, partitioning, topology; 2599 struct tgsi_shader_info *info = &rctx->tes_shader->current->selector->info; 2600 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE]; 2601 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING]; 2602 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW]; 2603 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE]; 2604 switch (tes_prim_mode) { 2605 case PIPE_PRIM_LINES: 2606 type = V_028B6C_TESS_ISOLINE; 2607 break; 2608 case PIPE_PRIM_TRIANGLES: 2609 type = V_028B6C_TESS_TRIANGLE; 2610 break; 2611 case PIPE_PRIM_QUADS: 2612 type = V_028B6C_TESS_QUAD; 2613 break; 2614 default: 2615 assert(0); 2616 return; 2617 } 2618 2619 switch (tes_spacing) { 2620 case PIPE_TESS_SPACING_FRACTIONAL_ODD: 2621 partitioning = V_028B6C_PART_FRAC_ODD; 2622 break; 2623 case PIPE_TESS_SPACING_FRACTIONAL_EVEN: 2624 partitioning = V_028B6C_PART_FRAC_EVEN; 2625 break; 2626 case PIPE_TESS_SPACING_EQUAL: 2627 partitioning = V_028B6C_PART_INTEGER; 2628 break; 2629 default: 2630 assert(0); 2631 return; 2632 } 2633 2634 if (tes_point_mode) 2635 topology = V_028B6C_OUTPUT_POINT; 2636 else if (tes_prim_mode == PIPE_PRIM_LINES) 2637 topology = V_028B6C_OUTPUT_LINE; 2638 else if (tes_vertex_order_cw) 2639 /* XXX follow radeonsi and invert */ 2640 topology = V_028B6C_OUTPUT_TRIANGLE_CCW; 2641 else 2642 topology = V_028B6C_OUTPUT_TRIANGLE_CW; 2643 2644 tf_param = S_028B6C_TYPE(type) | 2645 S_028B6C_PARTITIONING(partitioning) | 2646 S_028B6C_TOPOLOGY(topology); 2647 } 2648 2649 if (rctx->tes_shader) { 2650 v |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) | 2651 S_028B54_HS_EN(1); 2652 if (!state->geom_enable) 2653 v |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS); 2654 else 2655 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS); 2656 } 2657 2658 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, v ? 1 : 0 ); 2659 radeon_set_context_reg(cs, R_028B54_VGT_SHADER_STAGES_EN, v); 2660 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2); 2661 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid); 2662 radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM, tf_param); 2663} 2664 2665static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a) 2666{ 2667 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; 2668 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a; 2669 struct r600_resource *rbuffer; 2670 2671 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1)); 2672 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); 2673 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH)); 2674 2675 if (state->enable) { 2676 rbuffer =(struct r600_resource*)state->esgs_ring.buffer; 2677 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE, 2678 rbuffer->gpu_address >> 8); 2679 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); 2680 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer, 2681 RADEON_USAGE_READWRITE | 2682 RADEON_PRIO_SHADER_RINGS)); 2683 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 2684 state->esgs_ring.buffer_size >> 8); 2685 2686 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer; 2687 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE, 2688 rbuffer->gpu_address >> 8); 2689 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); 2690 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer, 2691 RADEON_USAGE_READWRITE | 2692 RADEON_PRIO_SHADER_RINGS)); 2693 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 2694 state->gsvs_ring.buffer_size >> 8); 2695 } else { 2696 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0); 2697 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0); 2698 } 2699 2700 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1)); 2701 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); 2702 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH)); 2703} 2704 2705void cayman_init_common_regs(struct r600_command_buffer *cb, 2706 enum amd_gfx_level gfx_level, 2707 enum radeon_family ctx_family, 2708 int ctx_drm_minor) 2709{ 2710 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2); 2711 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */ 2712 /* always set the temp clauses */ 2713 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */ 2714 2715 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2); 2716 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */ 2717 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */ 2718 2719 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8)); 2720 2721 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2); 2722 r600_store_value(cb, 0); 2723 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf)); 2724 2725 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0); 2726} 2727 2728static void cayman_init_atom_start_cs(struct r600_context *rctx) 2729{ 2730 struct r600_command_buffer *cb = &rctx->start_cs_cmd; 2731 int i; 2732 2733 r600_init_command_buffer(cb, 338); 2734 2735 /* This must be first. */ 2736 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); 2737 r600_store_value(cb, 0x80000000); 2738 r600_store_value(cb, 0x80000000); 2739 2740 /* We're setting config registers here. */ 2741 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0)); 2742 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4)); 2743 2744 /* This enables pipeline stat & streamout queries. 2745 * They are only disabled by blits. 2746 */ 2747 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0)); 2748 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0)); 2749 2750 cayman_init_common_regs(cb, rctx->b.gfx_level, 2751 rctx->b.family, rctx->screen->b.info.drm_minor); 2752 2753 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0); 2754 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4)); 2755 2756 /* remove LS/HS from one SIMD for hw workaround */ 2757 r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3); 2758 r600_store_value(cb, 0xffffffff); 2759 r600_store_value(cb, 0xffffffff); 2760 r600_store_value(cb, 0xfffffffe); 2761 2762 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6); 2763 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */ 2764 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */ 2765 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */ 2766 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */ 2767 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */ 2768 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */ 2769 2770 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4); 2771 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */ 2772 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */ 2773 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */ 2774 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */ 2775 2776 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13); 2777 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */ 2778 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */ 2779 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */ 2780 r600_store_value(cb, fui(0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */ 2781 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */ 2782 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */ 2783 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */ 2784 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */ 2785 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */ 2786 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */ 2787 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */ 2788 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */ 2789 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */ 2790 2791 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0); 2792 2793 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1); 2794 2795 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2); 2796 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */ 2797 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */ 2798 2799 r600_store_context_reg(cb, R_028724_GDS_ADDR_SIZE, 0x3fff); 2800 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2); 2801 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */ 2802 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */ 2803 2804 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0); 2805 2806 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2); 2807 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */ 2808 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */ 2809 2810 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0); 2811 2812 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0); 2813 2814 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0); 2815 2816 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3); 2817 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */ 2818 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */ 2819 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */ 2820 2821 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0); 2822 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF); 2823 2824 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA); 2825 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0); 2826 2827 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2); 2828 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */ 2829 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */ 2830 2831 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2); 2832 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */ 2833 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */ 2834 2835 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN)); 2836 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN)); 2837 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN)); 2838 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN)); 2839 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN)); 2840 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN)); 2841 2842 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0); 2843 2844 /* to avoid GPU doing any preloading of constant from random address */ 2845 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16); 2846 for (i = 0; i < 16; i++) 2847 r600_store_value(cb, 0); 2848 2849 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16); 2850 for (i = 0; i < 16; i++) 2851 r600_store_value(cb, 0); 2852 2853 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16); 2854 for (i = 0; i < 16; i++) 2855 r600_store_value(cb, 0); 2856 2857 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16); 2858 for (i = 0; i < 16; i++) 2859 r600_store_value(cb, 0); 2860 2861 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16); 2862 for (i = 0; i < 16; i++) 2863 r600_store_value(cb, 0); 2864 2865 if (rctx->screen->b.has_streamout) { 2866 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0); 2867 } 2868 2869 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0); 2870 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0); 2871 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0); 2872 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2); 2873 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */ 2874 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */ 2875 2876 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2); 2877 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */ 2878 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */ 2879 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0); 2880 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF); 2881 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF); 2882 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF); 2883 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF); 2884 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF); 2885} 2886 2887void evergreen_init_common_regs(struct r600_context *rctx, struct r600_command_buffer *cb, 2888 enum amd_gfx_level gfx_level, 2889 enum radeon_family ctx_family, 2890 int ctx_drm_minor) 2891{ 2892 int ps_prio; 2893 int vs_prio; 2894 int gs_prio; 2895 int es_prio; 2896 2897 int hs_prio; 2898 int cs_prio; 2899 int ls_prio; 2900 2901 unsigned tmp; 2902 2903 ps_prio = 0; 2904 vs_prio = 1; 2905 gs_prio = 2; 2906 es_prio = 3; 2907 hs_prio = 3; 2908 ls_prio = 3; 2909 cs_prio = 0; 2910 2911 rctx->default_gprs[R600_HW_STAGE_PS] = 93; 2912 rctx->default_gprs[R600_HW_STAGE_VS] = 46; 2913 rctx->r6xx_num_clause_temp_gprs = 4; 2914 rctx->default_gprs[R600_HW_STAGE_GS] = 31; 2915 rctx->default_gprs[R600_HW_STAGE_ES] = 31; 2916 rctx->default_gprs[EG_HW_STAGE_HS] = 23; 2917 rctx->default_gprs[EG_HW_STAGE_LS] = 23; 2918 2919 tmp = 0; 2920 switch (ctx_family) { 2921 case CHIP_CEDAR: 2922 case CHIP_PALM: 2923 case CHIP_SUMO: 2924 case CHIP_SUMO2: 2925 case CHIP_CAICOS: 2926 break; 2927 default: 2928 tmp |= S_008C00_VC_ENABLE(1); 2929 break; 2930 } 2931 tmp |= S_008C00_EXPORT_SRC_C(1); 2932 tmp |= S_008C00_CS_PRIO(cs_prio); 2933 tmp |= S_008C00_LS_PRIO(ls_prio); 2934 tmp |= S_008C00_HS_PRIO(hs_prio); 2935 tmp |= S_008C00_PS_PRIO(ps_prio); 2936 tmp |= S_008C00_VS_PRIO(vs_prio); 2937 tmp |= S_008C00_GS_PRIO(gs_prio); 2938 tmp |= S_008C00_ES_PRIO(es_prio); 2939 2940 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 1); 2941 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */ 2942 2943 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2); 2944 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */ 2945 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */ 2946 2947 /* The cs checker requires this register to be set. */ 2948 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0); 2949 2950 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2); 2951 r600_store_value(cb, 0); 2952 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf)); 2953 2954 return; 2955} 2956 2957void evergreen_init_atom_start_cs(struct r600_context *rctx) 2958{ 2959 struct r600_command_buffer *cb = &rctx->start_cs_cmd; 2960 int num_ps_threads; 2961 int num_vs_threads; 2962 int num_gs_threads; 2963 int num_es_threads; 2964 int num_hs_threads; 2965 int num_ls_threads; 2966 2967 int num_ps_stack_entries; 2968 int num_vs_stack_entries; 2969 int num_gs_stack_entries; 2970 int num_es_stack_entries; 2971 int num_hs_stack_entries; 2972 int num_ls_stack_entries; 2973 enum radeon_family family; 2974 unsigned tmp, i; 2975 2976 if (rctx->b.gfx_level == CAYMAN) { 2977 cayman_init_atom_start_cs(rctx); 2978 return; 2979 } 2980 2981 r600_init_command_buffer(cb, 338); 2982 2983 /* This must be first. */ 2984 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); 2985 r600_store_value(cb, 0x80000000); 2986 r600_store_value(cb, 0x80000000); 2987 2988 /* We're setting config registers here. */ 2989 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0)); 2990 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4)); 2991 2992 /* This enables pipeline stat & streamout queries. 2993 * They are only disabled by blits. 2994 */ 2995 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0)); 2996 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0)); 2997 2998 evergreen_init_common_regs(rctx, cb, rctx->b.gfx_level, 2999 rctx->b.family, rctx->screen->b.info.drm_minor); 3000 3001 family = rctx->b.family; 3002 switch (family) { 3003 case CHIP_CEDAR: 3004 default: 3005 num_ps_threads = 96; 3006 num_vs_threads = 16; 3007 num_gs_threads = 16; 3008 num_es_threads = 16; 3009 num_hs_threads = 16; 3010 num_ls_threads = 16; 3011 num_ps_stack_entries = 42; 3012 num_vs_stack_entries = 42; 3013 num_gs_stack_entries = 42; 3014 num_es_stack_entries = 42; 3015 num_hs_stack_entries = 42; 3016 num_ls_stack_entries = 42; 3017 break; 3018 case CHIP_REDWOOD: 3019 num_ps_threads = 128; 3020 num_vs_threads = 20; 3021 num_gs_threads = 20; 3022 num_es_threads = 20; 3023 num_hs_threads = 20; 3024 num_ls_threads = 20; 3025 num_ps_stack_entries = 42; 3026 num_vs_stack_entries = 42; 3027 num_gs_stack_entries = 42; 3028 num_es_stack_entries = 42; 3029 num_hs_stack_entries = 42; 3030 num_ls_stack_entries = 42; 3031 break; 3032 case CHIP_JUNIPER: 3033 num_ps_threads = 128; 3034 num_vs_threads = 20; 3035 num_gs_threads = 20; 3036 num_es_threads = 20; 3037 num_hs_threads = 20; 3038 num_ls_threads = 20; 3039 num_ps_stack_entries = 85; 3040 num_vs_stack_entries = 85; 3041 num_gs_stack_entries = 85; 3042 num_es_stack_entries = 85; 3043 num_hs_stack_entries = 85; 3044 num_ls_stack_entries = 85; 3045 break; 3046 case CHIP_CYPRESS: 3047 case CHIP_HEMLOCK: 3048 num_ps_threads = 128; 3049 num_vs_threads = 20; 3050 num_gs_threads = 20; 3051 num_es_threads = 20; 3052 num_hs_threads = 20; 3053 num_ls_threads = 20; 3054 num_ps_stack_entries = 85; 3055 num_vs_stack_entries = 85; 3056 num_gs_stack_entries = 85; 3057 num_es_stack_entries = 85; 3058 num_hs_stack_entries = 85; 3059 num_ls_stack_entries = 85; 3060 break; 3061 case CHIP_PALM: 3062 num_ps_threads = 96; 3063 num_vs_threads = 16; 3064 num_gs_threads = 16; 3065 num_es_threads = 16; 3066 num_hs_threads = 16; 3067 num_ls_threads = 16; 3068 num_ps_stack_entries = 42; 3069 num_vs_stack_entries = 42; 3070 num_gs_stack_entries = 42; 3071 num_es_stack_entries = 42; 3072 num_hs_stack_entries = 42; 3073 num_ls_stack_entries = 42; 3074 break; 3075 case CHIP_SUMO: 3076 num_ps_threads = 96; 3077 num_vs_threads = 25; 3078 num_gs_threads = 25; 3079 num_es_threads = 25; 3080 num_hs_threads = 16; 3081 num_ls_threads = 16; 3082 num_ps_stack_entries = 42; 3083 num_vs_stack_entries = 42; 3084 num_gs_stack_entries = 42; 3085 num_es_stack_entries = 42; 3086 num_hs_stack_entries = 42; 3087 num_ls_stack_entries = 42; 3088 break; 3089 case CHIP_SUMO2: 3090 num_ps_threads = 96; 3091 num_vs_threads = 25; 3092 num_gs_threads = 25; 3093 num_es_threads = 25; 3094 num_hs_threads = 16; 3095 num_ls_threads = 16; 3096 num_ps_stack_entries = 85; 3097 num_vs_stack_entries = 85; 3098 num_gs_stack_entries = 85; 3099 num_es_stack_entries = 85; 3100 num_hs_stack_entries = 85; 3101 num_ls_stack_entries = 85; 3102 break; 3103 case CHIP_BARTS: 3104 num_ps_threads = 128; 3105 num_vs_threads = 20; 3106 num_gs_threads = 20; 3107 num_es_threads = 20; 3108 num_hs_threads = 20; 3109 num_ls_threads = 20; 3110 num_ps_stack_entries = 85; 3111 num_vs_stack_entries = 85; 3112 num_gs_stack_entries = 85; 3113 num_es_stack_entries = 85; 3114 num_hs_stack_entries = 85; 3115 num_ls_stack_entries = 85; 3116 break; 3117 case CHIP_TURKS: 3118 num_ps_threads = 128; 3119 num_vs_threads = 20; 3120 num_gs_threads = 20; 3121 num_es_threads = 20; 3122 num_hs_threads = 20; 3123 num_ls_threads = 20; 3124 num_ps_stack_entries = 42; 3125 num_vs_stack_entries = 42; 3126 num_gs_stack_entries = 42; 3127 num_es_stack_entries = 42; 3128 num_hs_stack_entries = 42; 3129 num_ls_stack_entries = 42; 3130 break; 3131 case CHIP_CAICOS: 3132 num_ps_threads = 96; 3133 num_vs_threads = 10; 3134 num_gs_threads = 10; 3135 num_es_threads = 10; 3136 num_hs_threads = 10; 3137 num_ls_threads = 10; 3138 num_ps_stack_entries = 42; 3139 num_vs_stack_entries = 42; 3140 num_gs_stack_entries = 42; 3141 num_es_stack_entries = 42; 3142 num_hs_stack_entries = 42; 3143 num_ls_stack_entries = 42; 3144 break; 3145 } 3146 3147 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads); 3148 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads); 3149 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads); 3150 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads); 3151 3152 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5); 3153 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */ 3154 3155 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads); 3156 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads); 3157 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */ 3158 3159 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries); 3160 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries); 3161 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */ 3162 3163 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries); 3164 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries); 3165 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */ 3166 3167 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries); 3168 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries); 3169 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */ 3170 3171 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT, 3172 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000)); 3173 3174 /* remove LS/HS from one SIMD for hw workaround */ 3175 r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3); 3176 r600_store_value(cb, 0xffffffff); 3177 r600_store_value(cb, 0xffffffff); 3178 r600_store_value(cb, 0xfffffffe); 3179 3180 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0); 3181 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4)); 3182 3183 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6); 3184 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */ 3185 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */ 3186 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */ 3187 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */ 3188 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */ 3189 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */ 3190 3191 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4); 3192 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */ 3193 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */ 3194 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */ 3195 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */ 3196 3197 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13); 3198 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */ 3199 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */ 3200 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */ 3201 r600_store_value(cb, fui(1.0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */ 3202 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */ 3203 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */ 3204 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */ 3205 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */ 3206 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */ 3207 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */ 3208 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */ 3209 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */ 3210 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */ 3211 3212 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1); 3213 3214 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0); 3215 3216 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2); 3217 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */ 3218 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */ 3219 3220 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0); 3221 3222 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0); 3223 3224 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0); 3225 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF); 3226 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA); 3227 3228 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0); 3229 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0); 3230 3231 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3); 3232 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */ 3233 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */ 3234 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */ 3235 3236 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2); 3237 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */ 3238 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */ 3239 3240 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2); 3241 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */ 3242 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */ 3243 3244 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN)); 3245 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN)); 3246 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN)); 3247 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN)); 3248 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0); 3249 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN)); 3250 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN)); 3251 3252 /* to avoid GPU doing any preloading of constant from random address */ 3253 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16); 3254 for (i = 0; i < 16; i++) 3255 r600_store_value(cb, 0); 3256 3257 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16); 3258 for (i = 0; i < 16; i++) 3259 r600_store_value(cb, 0); 3260 3261 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16); 3262 for (i = 0; i < 16; i++) 3263 r600_store_value(cb, 0); 3264 3265 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16); 3266 for (i = 0; i < 16; i++) 3267 r600_store_value(cb, 0); 3268 3269 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16); 3270 for (i = 0; i < 16; i++) 3271 r600_store_value(cb, 0); 3272 3273 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0); 3274 3275 if (rctx->screen->b.has_streamout) { 3276 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0); 3277 } 3278 3279 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0); 3280 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0); 3281 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0); 3282 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2); 3283 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */ 3284 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */ 3285 3286 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2); 3287 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */ 3288 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */ 3289 3290 if (rctx->b.family == CHIP_CAICOS) { 3291 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2); 3292 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */ 3293 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */ 3294 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0); 3295 } else { 3296 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 7); 3297 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */ 3298 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */ 3299 r600_store_value(cb, 0); /* R028B5C_VGT_LS_SIZE */ 3300 r600_store_value(cb, 0); /* R028B60_VGT_HS_SIZE */ 3301 r600_store_value(cb, 0); /* R028B64_VGT_LS_HS_ALLOC */ 3302 r600_store_value(cb, 0); /* R028B68_VGT_HS_PATCH_CONST */ 3303 r600_store_value(cb, 0); /* R028B68_VGT_TF_PARAM */ 3304 } 3305 3306 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF); 3307 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF); 3308 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF); 3309 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF); 3310 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF); 3311} 3312 3313void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader) 3314{ 3315 struct r600_context *rctx = (struct r600_context *)ctx; 3316 struct r600_command_buffer *cb = &shader->command_buffer; 3317 struct r600_shader *rshader = &shader->shader; 3318 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control = 0; 3319 int pos_index = -1, face_index = -1, fixed_pt_position_index = -1; 3320 int ninterp = 0; 3321 boolean have_perspective = FALSE, have_linear = FALSE; 3322 static const unsigned spi_baryc_enable_bit[6] = { 3323 S_0286E0_PERSP_SAMPLE_ENA(1), 3324 S_0286E0_PERSP_CENTER_ENA(1), 3325 S_0286E0_PERSP_CENTROID_ENA(1), 3326 S_0286E0_LINEAR_SAMPLE_ENA(1), 3327 S_0286E0_LINEAR_CENTER_ENA(1), 3328 S_0286E0_LINEAR_CENTROID_ENA(1) 3329 }; 3330 unsigned spi_baryc_cntl = 0, sid, tmp, num = 0; 3331 unsigned z_export = 0, stencil_export = 0, mask_export = 0; 3332 uint32_t spi_ps_input_cntl[32]; 3333 3334 /* Pull any state we use out of rctx. Make sure that any additional 3335 * state added to this list is also checked in the caller in 3336 * r600_update_derived_state(). 3337 */ 3338 bool sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0; 3339 bool flatshade = rctx->rasterizer ? rctx->rasterizer->flatshade : 0; 3340 bool msaa = rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0; 3341 3342 if (!cb->buf) { 3343 r600_init_command_buffer(cb, 64); 3344 } else { 3345 cb->num_dw = 0; 3346 } 3347 3348 for (i = 0; i < rshader->ninput; i++) { 3349 /* evergreen NUM_INTERP only contains values interpolated into the LDS, 3350 POSITION goes via GPRs from the SC so isn't counted */ 3351 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION) 3352 pos_index = i; 3353 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE) { 3354 if (face_index == -1) 3355 face_index = i; 3356 } 3357 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEMASK) { 3358 if (face_index == -1) 3359 face_index = i; /* lives in same register, same enable bit */ 3360 } 3361 else if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEID) { 3362 fixed_pt_position_index = i; 3363 } 3364 else { 3365 ninterp++; 3366 int k = eg_get_interpolator_index( 3367 rshader->input[i].interpolate, 3368 rshader->input[i].interpolate_location); 3369 if (k >= 0) { 3370 spi_baryc_cntl |= spi_baryc_enable_bit[k]; 3371 have_perspective |= k < 3; 3372 have_linear |= !(k < 3); 3373 if (rshader->input[i].uses_interpolate_at_centroid) { 3374 k = eg_get_interpolator_index( 3375 rshader->input[i].interpolate, 3376 TGSI_INTERPOLATE_LOC_CENTROID); 3377 spi_baryc_cntl |= spi_baryc_enable_bit[k]; 3378 } 3379 } 3380 } 3381 3382 sid = rshader->input[i].spi_sid; 3383 3384 if (sid) { 3385 tmp = S_028644_SEMANTIC(sid); 3386 3387 /* D3D 9 behaviour. GL is undefined */ 3388 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR && rshader->input[i].sid == 0) 3389 tmp |= S_028644_DEFAULT_VAL(3); 3390 3391 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION || 3392 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT || 3393 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR && flatshade)) { 3394 tmp |= S_028644_FLAT_SHADE(1); 3395 } 3396 3397 if (rshader->input[i].name == TGSI_SEMANTIC_PCOORD || 3398 (rshader->input[i].name == TGSI_SEMANTIC_TEXCOORD && 3399 (sprite_coord_enable & (1 << rshader->input[i].sid)))) { 3400 tmp |= S_028644_PT_SPRITE_TEX(1); 3401 } 3402 3403 spi_ps_input_cntl[num++] = tmp; 3404 } 3405 } 3406 3407 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, num); 3408 r600_store_array(cb, num, spi_ps_input_cntl); 3409 3410 for (i = 0; i < rshader->noutput; i++) { 3411 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION) 3412 z_export = 1; 3413 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL) 3414 stencil_export = 1; 3415 if (rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK && msaa) 3416 mask_export = 1; 3417 } 3418 if (rshader->uses_kill) 3419 db_shader_control |= S_02880C_KILL_ENABLE(1); 3420 3421 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export); 3422 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export); 3423 db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export); 3424 3425 if (shader->selector->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) { 3426 db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) | 3427 S_02880C_EXEC_ON_NOOP(shader->selector->info.writes_memory); 3428 } else if (shader->selector->info.writes_memory) { 3429 db_shader_control |= S_02880C_EXEC_ON_HIER_FAIL(1); 3430 } 3431 3432 switch (rshader->ps_conservative_z) { 3433 default: /* fall through */ 3434 case TGSI_FS_DEPTH_LAYOUT_ANY: 3435 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_ANY_Z); 3436 break; 3437 case TGSI_FS_DEPTH_LAYOUT_GREATER: 3438 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z); 3439 break; 3440 case TGSI_FS_DEPTH_LAYOUT_LESS: 3441 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z); 3442 break; 3443 } 3444 3445 exports_ps = 0; 3446 for (i = 0; i < rshader->noutput; i++) { 3447 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION || 3448 rshader->output[i].name == TGSI_SEMANTIC_STENCIL || 3449 rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) 3450 exports_ps |= 1; 3451 } 3452 3453 num_cout = rshader->ps_export_highest + 1; 3454 3455 exports_ps |= S_02884C_EXPORT_COLORS(num_cout); 3456 if (!exports_ps) { 3457 /* always at least export 1 component per pixel */ 3458 exports_ps = 2; 3459 } 3460 shader->nr_ps_color_outputs = num_cout; 3461 shader->ps_color_export_mask = rshader->ps_color_export_mask; 3462 if (ninterp == 0) { 3463 ninterp = 1; 3464 have_perspective = TRUE; 3465 } 3466 if (!spi_baryc_cntl) 3467 spi_baryc_cntl |= spi_baryc_enable_bit[0]; 3468 3469 if (!have_perspective && !have_linear) 3470 have_perspective = TRUE; 3471 3472 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) | 3473 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) | 3474 S_0286CC_LINEAR_GRADIENT_ENA(have_linear); 3475 spi_input_z = 0; 3476 if (pos_index != -1) { 3477 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) | 3478 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) | 3479 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr); 3480 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1); 3481 } 3482 3483 spi_ps_in_control_1 = 0; 3484 if (face_index != -1) { 3485 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) | 3486 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr); 3487 } 3488 if (fixed_pt_position_index != -1) { 3489 spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) | 3490 S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr); 3491 } 3492 3493 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2); 3494 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */ 3495 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */ 3496 3497 r600_store_context_reg(cb, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl); 3498 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z); 3499 r600_store_context_reg(cb, R_02884C_SQ_PGM_EXPORTS_PS, exports_ps); 3500 3501 r600_store_context_reg_seq(cb, R_028840_SQ_PGM_START_PS, 2); 3502 r600_store_value(cb, shader->bo->gpu_address >> 8); 3503 r600_store_value(cb, /* R_028844_SQ_PGM_RESOURCES_PS */ 3504 S_028844_NUM_GPRS(rshader->bc.ngpr) | 3505 S_028844_PRIME_CACHE_ON_DRAW(1) | 3506 S_028844_DX10_CLAMP(1) | 3507 S_028844_STACK_SIZE(rshader->bc.nstack)); 3508 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */ 3509 3510 shader->db_shader_control = db_shader_control; 3511 shader->ps_depth_export = z_export | stencil_export | mask_export; 3512 3513 shader->sprite_coord_enable = sprite_coord_enable; 3514 shader->flatshade = flatshade; 3515 shader->msaa = msaa; 3516} 3517 3518void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader) 3519{ 3520 struct r600_command_buffer *cb = &shader->command_buffer; 3521 struct r600_shader *rshader = &shader->shader; 3522 3523 r600_init_command_buffer(cb, 32); 3524 3525 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES, 3526 S_028890_NUM_GPRS(rshader->bc.ngpr) | 3527 S_028890_DX10_CLAMP(1) | 3528 S_028890_STACK_SIZE(rshader->bc.nstack)); 3529 r600_store_context_reg(cb, R_02888C_SQ_PGM_START_ES, 3530 shader->bo->gpu_address >> 8); 3531 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */ 3532} 3533 3534void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader) 3535{ 3536 struct r600_command_buffer *cb = &shader->command_buffer; 3537 struct r600_shader *rshader = &shader->shader; 3538 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader; 3539 unsigned gsvs_itemsizes[4] = { 3540 (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2, 3541 (cp_shader->ring_item_sizes[1] * shader->selector->gs_max_out_vertices) >> 2, 3542 (cp_shader->ring_item_sizes[2] * shader->selector->gs_max_out_vertices) >> 2, 3543 (cp_shader->ring_item_sizes[3] * shader->selector->gs_max_out_vertices) >> 2 3544 }; 3545 3546 r600_init_command_buffer(cb, 64); 3547 3548 /* VGT_GS_MODE is written by evergreen_emit_shader_stages */ 3549 3550 3551 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT, 3552 S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices)); 3553 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE, 3554 r600_conv_prim_to_gs_out(shader->selector->gs_output_prim)); 3555 3556 r600_store_context_reg(cb, R_028B90_VGT_GS_INSTANCE_CNT, 3557 S_028B90_CNT(MIN2(shader->selector->gs_num_invocations, 127)) | 3558 S_028B90_ENABLE(shader->selector->gs_num_invocations > 0)); 3559 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4); 3560 r600_store_value(cb, cp_shader->ring_item_sizes[0] >> 2); 3561 r600_store_value(cb, cp_shader->ring_item_sizes[1] >> 2); 3562 r600_store_value(cb, cp_shader->ring_item_sizes[2] >> 2); 3563 r600_store_value(cb, cp_shader->ring_item_sizes[3] >> 2); 3564 3565 r600_store_context_reg(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 3566 (rshader->ring_item_sizes[0]) >> 2); 3567 3568 r600_store_context_reg(cb, R_028904_SQ_GSVS_RING_ITEMSIZE, 3569 gsvs_itemsizes[0] + 3570 gsvs_itemsizes[1] + 3571 gsvs_itemsizes[2] + 3572 gsvs_itemsizes[3]); 3573 3574 r600_store_context_reg_seq(cb, R_02892C_SQ_GSVS_RING_OFFSET_1, 3); 3575 r600_store_value(cb, gsvs_itemsizes[0]); 3576 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1]); 3577 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1] + gsvs_itemsizes[2]); 3578 3579 /* FIXME calculate these values somehow ??? */ 3580 r600_store_context_reg_seq(cb, R_028A54_GS_PER_ES, 3); 3581 r600_store_value(cb, 0x80); /* GS_PER_ES */ 3582 r600_store_value(cb, 0x100); /* ES_PER_GS */ 3583 r600_store_value(cb, 0x2); /* GS_PER_VS */ 3584 3585 r600_store_context_reg(cb, R_028878_SQ_PGM_RESOURCES_GS, 3586 S_028878_NUM_GPRS(rshader->bc.ngpr) | 3587 S_028878_DX10_CLAMP(1) | 3588 S_028878_STACK_SIZE(rshader->bc.nstack)); 3589 r600_store_context_reg(cb, R_028874_SQ_PGM_START_GS, 3590 shader->bo->gpu_address >> 8); 3591 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */ 3592} 3593 3594 3595void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader) 3596{ 3597 struct r600_command_buffer *cb = &shader->command_buffer; 3598 struct r600_shader *rshader = &shader->shader; 3599 unsigned spi_vs_out_id[10] = {}; 3600 unsigned i, tmp, nparams = 0; 3601 3602 for (i = 0; i < rshader->noutput; i++) { 3603 if (rshader->output[i].spi_sid) { 3604 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8); 3605 spi_vs_out_id[nparams / 4] |= tmp; 3606 nparams++; 3607 } 3608 } 3609 3610 r600_init_command_buffer(cb, 32); 3611 3612 r600_store_context_reg_seq(cb, R_02861C_SPI_VS_OUT_ID_0, 10); 3613 for (i = 0; i < 10; i++) { 3614 r600_store_value(cb, spi_vs_out_id[i]); 3615 } 3616 3617 /* Certain attributes (position, psize, etc.) don't count as params. 3618 * VS is required to export at least one param and r600_shader_from_tgsi() 3619 * takes care of adding a dummy export. 3620 */ 3621 if (nparams < 1) 3622 nparams = 1; 3623 3624 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG, 3625 S_0286C4_VS_EXPORT_COUNT(nparams - 1)); 3626 r600_store_context_reg(cb, R_028860_SQ_PGM_RESOURCES_VS, 3627 S_028860_NUM_GPRS(rshader->bc.ngpr) | 3628 S_028860_DX10_CLAMP(1) | 3629 S_028860_STACK_SIZE(rshader->bc.nstack)); 3630 if (rshader->vs_position_window_space) { 3631 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 3632 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1)); 3633 } else { 3634 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 3635 S_028818_VTX_W0_FMT(1) | 3636 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) | 3637 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) | 3638 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1)); 3639 3640 } 3641 r600_store_context_reg(cb, R_02885C_SQ_PGM_START_VS, 3642 shader->bo->gpu_address >> 8); 3643 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */ 3644 3645 shader->pa_cl_vs_out_cntl = 3646 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->cc_dist_mask & 0x0F) != 0) | 3647 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->cc_dist_mask & 0xF0) != 0) | 3648 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) | 3649 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) | 3650 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) | 3651 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport) | 3652 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer); 3653} 3654 3655void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader) 3656{ 3657 struct r600_command_buffer *cb = &shader->command_buffer; 3658 struct r600_shader *rshader = &shader->shader; 3659 3660 r600_init_command_buffer(cb, 32); 3661 r600_store_context_reg(cb, R_0288BC_SQ_PGM_RESOURCES_HS, 3662 S_0288BC_NUM_GPRS(rshader->bc.ngpr) | 3663 S_0288BC_DX10_CLAMP(1) | 3664 S_0288BC_STACK_SIZE(rshader->bc.nstack)); 3665 r600_store_context_reg(cb, R_0288B8_SQ_PGM_START_HS, 3666 shader->bo->gpu_address >> 8); 3667} 3668 3669void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader) 3670{ 3671 struct r600_command_buffer *cb = &shader->command_buffer; 3672 struct r600_shader *rshader = &shader->shader; 3673 3674 r600_init_command_buffer(cb, 32); 3675 r600_store_context_reg(cb, R_0288D4_SQ_PGM_RESOURCES_LS, 3676 S_0288D4_NUM_GPRS(rshader->bc.ngpr) | 3677 S_0288D4_DX10_CLAMP(1) | 3678 S_0288D4_STACK_SIZE(rshader->bc.nstack)); 3679 r600_store_context_reg(cb, R_0288D0_SQ_PGM_START_LS, 3680 shader->bo->gpu_address >> 8); 3681} 3682void *evergreen_create_resolve_blend(struct r600_context *rctx) 3683{ 3684 struct pipe_blend_state blend; 3685 3686 memset(&blend, 0, sizeof(blend)); 3687 blend.independent_blend_enable = true; 3688 blend.rt[0].colormask = 0xf; 3689 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, V_028808_CB_RESOLVE); 3690} 3691 3692void *evergreen_create_decompress_blend(struct r600_context *rctx) 3693{ 3694 struct pipe_blend_state blend; 3695 unsigned mode = rctx->screen->has_compressed_msaa_texturing ? 3696 V_028808_CB_FMASK_DECOMPRESS : V_028808_CB_DECOMPRESS; 3697 3698 memset(&blend, 0, sizeof(blend)); 3699 blend.independent_blend_enable = true; 3700 blend.rt[0].colormask = 0xf; 3701 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode); 3702} 3703 3704void *evergreen_create_fastclear_blend(struct r600_context *rctx) 3705{ 3706 struct pipe_blend_state blend; 3707 unsigned mode = V_028808_CB_ELIMINATE_FAST_CLEAR; 3708 3709 memset(&blend, 0, sizeof(blend)); 3710 blend.independent_blend_enable = true; 3711 blend.rt[0].colormask = 0xf; 3712 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode); 3713} 3714 3715void *evergreen_create_db_flush_dsa(struct r600_context *rctx) 3716{ 3717 struct pipe_depth_stencil_alpha_state dsa = {{{0}}}; 3718 3719 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa); 3720} 3721 3722void evergreen_update_db_shader_control(struct r600_context * rctx) 3723{ 3724 bool dual_export; 3725 unsigned db_shader_control; 3726 3727 if (!rctx->ps_shader) { 3728 return; 3729 } 3730 3731 dual_export = rctx->framebuffer.export_16bpc && 3732 !rctx->ps_shader->current->ps_depth_export; 3733 3734 db_shader_control = rctx->ps_shader->current->db_shader_control | 3735 S_02880C_DUAL_EXPORT_ENABLE(dual_export) | 3736 S_02880C_DB_SOURCE_FORMAT(dual_export ? V_02880C_EXPORT_DB_TWO : 3737 V_02880C_EXPORT_DB_FULL) | 3738 S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer); 3739 3740 /* When alpha test is enabled we can't trust the hw to make the proper 3741 * decision on the order in which ztest should be run related to fragment 3742 * shader execution. 3743 * 3744 * If alpha test is enabled perform early z rejection (RE_Z) but don't early 3745 * write to the zbuffer. Write to zbuffer is delayed after fragment shader 3746 * execution and thus after alpha test so if discarded by the alpha test 3747 * the z value is not written. 3748 * If ReZ is enabled, and the zfunc/zenable/zwrite values change you can 3749 * get a hang unless you flush the DB in between. For now just use 3750 * LATE_Z. 3751 */ 3752 if (rctx->alphatest_state.sx_alpha_test_control || rctx->ps_shader->info.writes_memory) { 3753 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z); 3754 } else { 3755 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z); 3756 } 3757 3758 if (db_shader_control != rctx->db_misc_state.db_shader_control) { 3759 rctx->db_misc_state.db_shader_control = db_shader_control; 3760 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom); 3761 } 3762} 3763 3764static void evergreen_dma_copy_tile(struct r600_context *rctx, 3765 struct pipe_resource *dst, 3766 unsigned dst_level, 3767 unsigned dst_x, 3768 unsigned dst_y, 3769 unsigned dst_z, 3770 struct pipe_resource *src, 3771 unsigned src_level, 3772 unsigned src_x, 3773 unsigned src_y, 3774 unsigned src_z, 3775 unsigned copy_height, 3776 unsigned pitch, 3777 unsigned bpp) 3778{ 3779 struct radeon_cmdbuf *cs = &rctx->b.dma.cs; 3780 struct r600_texture *rsrc = (struct r600_texture*)src; 3781 struct r600_texture *rdst = (struct r600_texture*)dst; 3782 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size; 3783 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode; 3784 unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, non_disp_tiling = 0; 3785 uint64_t base, addr; 3786 3787 dst_mode = rdst->surface.u.legacy.level[dst_level].mode; 3788 src_mode = rsrc->surface.u.legacy.level[src_level].mode; 3789 assert(dst_mode != src_mode); 3790 3791 /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */ 3792 if (util_format_has_depth(util_format_description(src->format))) 3793 non_disp_tiling = 1; 3794 3795 y = 0; 3796 sub_cmd = EG_DMA_COPY_TILED; 3797 lbpp = util_logbase2(bpp); 3798 pitch_tile_max = ((pitch / bpp) / 8) - 1; 3799 nbanks = eg_num_banks(rctx->screen->b.info.r600_num_banks); 3800 3801 if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED) { 3802 /* T2L */ 3803 array_mode = evergreen_array_mode(src_mode); 3804 slice_tile_max = (rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.u.legacy.level[src_level].nblk_y) / (8*8); 3805 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0; 3806 /* linear height must be the same as the slice tile max height, it's ok even 3807 * if the linear destination/source have smaller heigh as the size of the 3808 * dma packet will be using the copy_height which is always smaller or equal 3809 * to the linear height 3810 */ 3811 height = u_minify(rsrc->resource.b.b.height0, src_level); 3812 detile = 1; 3813 x = src_x; 3814 y = src_y; 3815 z = src_z; 3816 base = (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 256; 3817 addr = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256; 3818 addr += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z; 3819 addr += dst_y * pitch + dst_x * bpp; 3820 bank_h = eg_bank_wh(rsrc->surface.u.legacy.bankh); 3821 bank_w = eg_bank_wh(rsrc->surface.u.legacy.bankw); 3822 mt_aspect = eg_macro_tile_aspect(rsrc->surface.u.legacy.mtilea); 3823 tile_split = eg_tile_split(rsrc->surface.u.legacy.tile_split); 3824 base += rsrc->resource.gpu_address; 3825 addr += rdst->resource.gpu_address; 3826 } else { 3827 /* L2T */ 3828 array_mode = evergreen_array_mode(dst_mode); 3829 slice_tile_max = (rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[dst_level].nblk_y) / (8*8); 3830 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0; 3831 /* linear height must be the same as the slice tile max height, it's ok even 3832 * if the linear destination/source have smaller heigh as the size of the 3833 * dma packet will be using the copy_height which is always smaller or equal 3834 * to the linear height 3835 */ 3836 height = u_minify(rdst->resource.b.b.height0, dst_level); 3837 detile = 0; 3838 x = dst_x; 3839 y = dst_y; 3840 z = dst_z; 3841 base = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256; 3842 addr = (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 256; 3843 addr += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_z; 3844 addr += src_y * pitch + src_x * bpp; 3845 bank_h = eg_bank_wh(rdst->surface.u.legacy.bankh); 3846 bank_w = eg_bank_wh(rdst->surface.u.legacy.bankw); 3847 mt_aspect = eg_macro_tile_aspect(rdst->surface.u.legacy.mtilea); 3848 tile_split = eg_tile_split(rdst->surface.u.legacy.tile_split); 3849 base += rdst->resource.gpu_address; 3850 addr += rsrc->resource.gpu_address; 3851 } 3852 3853 size = (copy_height * pitch) / 4; 3854 ncopy = (size / EG_DMA_COPY_MAX_SIZE) + !!(size % EG_DMA_COPY_MAX_SIZE); 3855 r600_need_dma_space(&rctx->b, ncopy * 9, &rdst->resource, &rsrc->resource); 3856 3857 for (i = 0; i < ncopy; i++) { 3858 cheight = copy_height; 3859 if (((cheight * pitch) / 4) > EG_DMA_COPY_MAX_SIZE) { 3860 cheight = (EG_DMA_COPY_MAX_SIZE * 4) / pitch; 3861 } 3862 size = (cheight * pitch) / 4; 3863 /* emit reloc before writing cs so that cs is always in consistent state */ 3864 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource, 3865 RADEON_USAGE_READ); 3866 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource, 3867 RADEON_USAGE_WRITE); 3868 radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, sub_cmd, size)); 3869 radeon_emit(cs, base >> 8); 3870 radeon_emit(cs, (detile << 31) | (array_mode << 27) | 3871 (lbpp << 24) | (bank_h << 21) | 3872 (bank_w << 18) | (mt_aspect << 16)); 3873 radeon_emit(cs, (pitch_tile_max << 0) | ((height - 1) << 16)); 3874 radeon_emit(cs, (slice_tile_max << 0)); 3875 radeon_emit(cs, (x << 0) | (z << 18)); 3876 radeon_emit(cs, (y << 0) | (tile_split << 21) | (nbanks << 25) | (non_disp_tiling << 28)); 3877 radeon_emit(cs, addr & 0xfffffffc); 3878 radeon_emit(cs, (addr >> 32UL) & 0xff); 3879 copy_height -= cheight; 3880 addr += cheight * pitch; 3881 y += cheight; 3882 } 3883} 3884 3885static void evergreen_dma_copy(struct pipe_context *ctx, 3886 struct pipe_resource *dst, 3887 unsigned dst_level, 3888 unsigned dstx, unsigned dsty, unsigned dstz, 3889 struct pipe_resource *src, 3890 unsigned src_level, 3891 const struct pipe_box *src_box) 3892{ 3893 struct r600_context *rctx = (struct r600_context *)ctx; 3894 struct r600_texture *rsrc = (struct r600_texture*)src; 3895 struct r600_texture *rdst = (struct r600_texture*)dst; 3896 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height; 3897 unsigned src_w, dst_w; 3898 unsigned src_x, src_y; 3899 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz; 3900 3901 if (rctx->b.dma.cs.priv == NULL) { 3902 goto fallback; 3903 } 3904 3905 if (rctx->cmd_buf_is_compute) { 3906 rctx->b.gfx.flush(rctx, PIPE_FLUSH_ASYNC, NULL); 3907 rctx->cmd_buf_is_compute = false; 3908 } 3909 3910 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) { 3911 evergreen_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width); 3912 return; 3913 } 3914 3915 if (src_box->depth > 1 || 3916 !r600_prepare_for_dma_blit(&rctx->b, rdst, dst_level, dstx, dsty, 3917 dstz, rsrc, src_level, src_box)) 3918 goto fallback; 3919 3920 src_x = util_format_get_nblocksx(src->format, src_box->x); 3921 dst_x = util_format_get_nblocksx(src->format, dst_x); 3922 src_y = util_format_get_nblocksy(src->format, src_box->y); 3923 dst_y = util_format_get_nblocksy(src->format, dst_y); 3924 3925 bpp = rdst->surface.bpe; 3926 dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.bpe; 3927 src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.bpe; 3928 src_w = u_minify(rsrc->resource.b.b.width0, src_level); 3929 dst_w = u_minify(rdst->resource.b.b.width0, dst_level); 3930 copy_height = src_box->height / rsrc->surface.blk_h; 3931 3932 dst_mode = rdst->surface.u.legacy.level[dst_level].mode; 3933 src_mode = rsrc->surface.u.legacy.level[src_level].mode; 3934 3935 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) { 3936 /* FIXME evergreen can do partial blit */ 3937 goto fallback; 3938 } 3939 /* the x test here are currently useless (because we don't support partial blit) 3940 * but keep them around so we don't forget about those 3941 */ 3942 if (src_pitch % 8 || src_box->x % 8 || dst_x % 8 || src_box->y % 8 || dst_y % 8) { 3943 goto fallback; 3944 } 3945 3946 /* 128 bpp surfaces require non_disp_tiling for both 3947 * tiled and linear buffers on cayman. However, async 3948 * DMA only supports it on the tiled side. As such 3949 * the tile order is backwards after a L2T/T2L packet. 3950 */ 3951 if ((rctx->b.gfx_level == CAYMAN) && 3952 (src_mode != dst_mode) && 3953 (util_format_get_blocksize(src->format) >= 16)) { 3954 goto fallback; 3955 } 3956 3957 if (src_mode == dst_mode) { 3958 uint64_t dst_offset, src_offset; 3959 /* simple dma blit would do NOTE code here assume : 3960 * src_box.x/y == 0 3961 * dst_x/y == 0 3962 * dst_pitch == src_pitch 3963 */ 3964 src_offset= (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 256; 3965 src_offset += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_box->z; 3966 src_offset += src_y * src_pitch + src_x * bpp; 3967 dst_offset = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256; 3968 dst_offset += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z; 3969 dst_offset += dst_y * dst_pitch + dst_x * bpp; 3970 evergreen_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset, 3971 src_box->height * src_pitch); 3972 } else { 3973 evergreen_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z, 3974 src, src_level, src_x, src_y, src_box->z, 3975 copy_height, dst_pitch, bpp); 3976 } 3977 return; 3978 3979fallback: 3980 r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz, 3981 src, src_level, src_box); 3982} 3983 3984static void evergreen_set_tess_state(struct pipe_context *ctx, 3985 const float default_outer_level[4], 3986 const float default_inner_level[2]) 3987{ 3988 struct r600_context *rctx = (struct r600_context *)ctx; 3989 3990 memcpy(rctx->tess_state, default_outer_level, sizeof(float) * 4); 3991 memcpy(rctx->tess_state+4, default_inner_level, sizeof(float) * 2); 3992 rctx->driver_consts[PIPE_SHADER_TESS_CTRL].tcs_default_levels_dirty = true; 3993} 3994 3995static void evergreen_set_patch_vertices(struct pipe_context *ctx, uint8_t patch_vertices) 3996{ 3997 struct r600_context *rctx = (struct r600_context *)ctx; 3998 3999 rctx->patch_vertices = patch_vertices; 4000} 4001 4002static void evergreen_setup_immed_buffer(struct r600_context *rctx, 4003 struct r600_image_view *rview, 4004 enum pipe_format pformat) 4005{ 4006 struct r600_screen *rscreen = (struct r600_screen *)rctx->b.b.screen; 4007 uint32_t immed_size = rscreen->b.info.max_se * 256 * 64 * util_format_get_blocksize(pformat); 4008 struct eg_buf_res_params buf_params; 4009 bool skip_reloc = false; 4010 struct r600_resource *resource = (struct r600_resource *)rview->base.resource; 4011 if (!resource->immed_buffer) { 4012 eg_resource_alloc_immed(&rscreen->b, resource, immed_size); 4013 } 4014 4015 memset(&buf_params, 0, sizeof(buf_params)); 4016 buf_params.pipe_format = pformat; 4017 buf_params.size = resource->immed_buffer->b.b.width0; 4018 buf_params.swizzle[0] = PIPE_SWIZZLE_X; 4019 buf_params.swizzle[1] = PIPE_SWIZZLE_Y; 4020 buf_params.swizzle[2] = PIPE_SWIZZLE_Z; 4021 buf_params.swizzle[3] = PIPE_SWIZZLE_W; 4022 buf_params.uncached = 1; 4023 evergreen_fill_buffer_resource_words(rctx, &resource->immed_buffer->b.b, 4024 &buf_params, &skip_reloc, 4025 rview->immed_resource_words); 4026} 4027 4028static void evergreen_set_hw_atomic_buffers(struct pipe_context *ctx, 4029 unsigned start_slot, 4030 unsigned count, 4031 const struct pipe_shader_buffer *buffers) 4032{ 4033 struct r600_context *rctx = (struct r600_context *)ctx; 4034 struct r600_atomic_buffer_state *astate; 4035 unsigned i, idx; 4036 4037 astate = &rctx->atomic_buffer_state; 4038 4039 /* we'd probably like to expand this to 8 later so put the logic in */ 4040 for (i = start_slot, idx = 0; i < start_slot + count; i++, idx++) { 4041 const struct pipe_shader_buffer *buf; 4042 struct pipe_shader_buffer *abuf; 4043 4044 abuf = &astate->buffer[i]; 4045 4046 if (!buffers || !buffers[idx].buffer) { 4047 pipe_resource_reference(&abuf->buffer, NULL); 4048 continue; 4049 } 4050 buf = &buffers[idx]; 4051 4052 pipe_resource_reference(&abuf->buffer, buf->buffer); 4053 abuf->buffer_offset = buf->buffer_offset; 4054 abuf->buffer_size = buf->buffer_size; 4055 } 4056} 4057 4058static void evergreen_set_shader_buffers(struct pipe_context *ctx, 4059 enum pipe_shader_type shader, unsigned start_slot, 4060 unsigned count, 4061 const struct pipe_shader_buffer *buffers, 4062 unsigned writable_bitmask) 4063{ 4064 struct r600_context *rctx = (struct r600_context *)ctx; 4065 struct r600_image_state *istate = NULL; 4066 struct r600_image_view *rview; 4067 struct r600_tex_color_info color; 4068 struct eg_buf_res_params buf_params; 4069 struct r600_resource *resource; 4070 unsigned i, idx; 4071 unsigned old_mask; 4072 4073 if (shader != PIPE_SHADER_FRAGMENT && 4074 shader != PIPE_SHADER_COMPUTE && count == 0) 4075 return; 4076 4077 if (shader == PIPE_SHADER_FRAGMENT) 4078 istate = &rctx->fragment_buffers; 4079 else if (shader == PIPE_SHADER_COMPUTE) 4080 istate = &rctx->compute_buffers; 4081 4082 old_mask = istate->enabled_mask; 4083 for (i = start_slot, idx = 0; i < start_slot + count; i++, idx++) { 4084 const struct pipe_shader_buffer *buf; 4085 unsigned res_type; 4086 4087 rview = &istate->views[i]; 4088 4089 if (!buffers || !buffers[idx].buffer) { 4090 pipe_resource_reference((struct pipe_resource **)&rview->base.resource, NULL); 4091 istate->enabled_mask &= ~(1 << i); 4092 continue; 4093 } 4094 4095 buf = &buffers[idx]; 4096 pipe_resource_reference((struct pipe_resource **)&rview->base.resource, buf->buffer); 4097 4098 resource = (struct r600_resource *)rview->base.resource; 4099 4100 evergreen_setup_immed_buffer(rctx, rview, PIPE_FORMAT_R32_UINT); 4101 4102 color.offset = 0; 4103 color.view = 0; 4104 evergreen_set_color_surface_buffer(rctx, resource, 4105 PIPE_FORMAT_R32_UINT, 4106 buf->buffer_offset, 4107 buf->buffer_offset + buf->buffer_size, 4108 &color); 4109 4110 res_type = V_028C70_BUFFER; 4111 4112 rview->cb_color_base = color.offset; 4113 rview->cb_color_dim = color.dim; 4114 rview->cb_color_info = color.info | 4115 S_028C70_RAT(1) | 4116 S_028C70_RESOURCE_TYPE(res_type); 4117 rview->cb_color_pitch = color.pitch; 4118 rview->cb_color_slice = color.slice; 4119 rview->cb_color_view = color.view; 4120 rview->cb_color_attrib = color.attrib; 4121 rview->cb_color_fmask = color.fmask; 4122 rview->cb_color_fmask_slice = color.fmask_slice; 4123 4124 memset(&buf_params, 0, sizeof(buf_params)); 4125 buf_params.pipe_format = PIPE_FORMAT_R32_UINT; 4126 buf_params.offset = buf->buffer_offset; 4127 buf_params.size = buf->buffer_size; 4128 buf_params.swizzle[0] = PIPE_SWIZZLE_X; 4129 buf_params.swizzle[1] = PIPE_SWIZZLE_Y; 4130 buf_params.swizzle[2] = PIPE_SWIZZLE_Z; 4131 buf_params.swizzle[3] = PIPE_SWIZZLE_W; 4132 buf_params.force_swizzle = true; 4133 buf_params.uncached = 1; 4134 buf_params.size_in_bytes = true; 4135 evergreen_fill_buffer_resource_words(rctx, &resource->b.b, 4136 &buf_params, 4137 &rview->skip_mip_address_reloc, 4138 rview->resource_words); 4139 4140 istate->enabled_mask |= (1 << i); 4141 } 4142 4143 istate->atom.num_dw = util_bitcount(istate->enabled_mask) * 46; 4144 4145 if (old_mask != istate->enabled_mask) 4146 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom); 4147 4148 /* construct the target mask */ 4149 if (rctx->cb_misc_state.buffer_rat_enabled_mask != istate->enabled_mask) { 4150 rctx->cb_misc_state.buffer_rat_enabled_mask = istate->enabled_mask; 4151 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom); 4152 } 4153 4154 if (shader == PIPE_SHADER_FRAGMENT) 4155 r600_mark_atom_dirty(rctx, &istate->atom); 4156} 4157 4158static void evergreen_set_shader_images(struct pipe_context *ctx, 4159 enum pipe_shader_type shader, unsigned start_slot, 4160 unsigned count, unsigned unbind_num_trailing_slots, 4161 const struct pipe_image_view *images) 4162{ 4163 struct r600_context *rctx = (struct r600_context *)ctx; 4164 unsigned i; 4165 struct r600_image_view *rview; 4166 struct pipe_resource *image; 4167 struct r600_resource *resource; 4168 struct r600_tex_color_info color; 4169 struct eg_buf_res_params buf_params; 4170 struct eg_tex_res_params tex_params; 4171 unsigned old_mask; 4172 struct r600_image_state *istate = NULL; 4173 int idx; 4174 if (shader != PIPE_SHADER_FRAGMENT && shader != PIPE_SHADER_COMPUTE) 4175 return; 4176 if (!count && !unbind_num_trailing_slots) 4177 return; 4178 4179 if (shader == PIPE_SHADER_FRAGMENT) 4180 istate = &rctx->fragment_images; 4181 else if (shader == PIPE_SHADER_COMPUTE) 4182 istate = &rctx->compute_images; 4183 4184 assert (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE); 4185 4186 old_mask = istate->enabled_mask; 4187 for (i = start_slot, idx = 0; i < start_slot + count; i++, idx++) { 4188 unsigned res_type; 4189 const struct pipe_image_view *iview; 4190 rview = &istate->views[i]; 4191 4192 if (!images || !images[idx].resource) { 4193 pipe_resource_reference((struct pipe_resource **)&rview->base.resource, NULL); 4194 istate->enabled_mask &= ~(1 << i); 4195 istate->compressed_colortex_mask &= ~(1 << i); 4196 istate->compressed_depthtex_mask &= ~(1 << i); 4197 continue; 4198 } 4199 4200 iview = &images[idx]; 4201 image = iview->resource; 4202 resource = (struct r600_resource *)image; 4203 4204 r600_context_add_resource_size(ctx, image); 4205 4206 rview->base = *iview; 4207 rview->base.resource = NULL; 4208 pipe_resource_reference((struct pipe_resource **)&rview->base.resource, image); 4209 4210 evergreen_setup_immed_buffer(rctx, rview, iview->format); 4211 4212 bool is_buffer = image->target == PIPE_BUFFER; 4213 struct r600_texture *rtex = (struct r600_texture *)image; 4214 if (!is_buffer & rtex->db_compatible) 4215 istate->compressed_depthtex_mask |= 1 << i; 4216 else 4217 istate->compressed_depthtex_mask &= ~(1 << i); 4218 4219 if (!is_buffer && rtex->cmask.size) 4220 istate->compressed_colortex_mask |= 1 << i; 4221 else 4222 istate->compressed_colortex_mask &= ~(1 << i); 4223 if (!is_buffer) { 4224 4225 evergreen_set_color_surface_common(rctx, rtex, 4226 iview->u.tex.level, 4227 iview->u.tex.first_layer, 4228 iview->u.tex.last_layer, 4229 iview->format, 4230 &color); 4231 color.dim = S_028C78_WIDTH_MAX(u_minify(image->width0, iview->u.tex.level) - 1) | 4232 S_028C78_HEIGHT_MAX(u_minify(image->height0, iview->u.tex.level) - 1); 4233 } else { 4234 color.offset = 0; 4235 color.view = 0; 4236 evergreen_set_color_surface_buffer(rctx, resource, 4237 iview->format, 4238 iview->u.buf.offset, 4239 iview->u.buf.size, 4240 &color); 4241 } 4242 4243 switch (image->target) { 4244 case PIPE_BUFFER: 4245 res_type = V_028C70_BUFFER; 4246 break; 4247 case PIPE_TEXTURE_1D: 4248 res_type = V_028C70_TEXTURE1D; 4249 break; 4250 case PIPE_TEXTURE_1D_ARRAY: 4251 res_type = V_028C70_TEXTURE1DARRAY; 4252 break; 4253 case PIPE_TEXTURE_2D: 4254 case PIPE_TEXTURE_RECT: 4255 res_type = V_028C70_TEXTURE2D; 4256 break; 4257 case PIPE_TEXTURE_3D: 4258 res_type = V_028C70_TEXTURE3D; 4259 break; 4260 case PIPE_TEXTURE_2D_ARRAY: 4261 case PIPE_TEXTURE_CUBE: 4262 case PIPE_TEXTURE_CUBE_ARRAY: 4263 res_type = V_028C70_TEXTURE2DARRAY; 4264 break; 4265 default: 4266 assert(0); 4267 res_type = 0; 4268 break; 4269 } 4270 4271 rview->cb_color_base = color.offset; 4272 rview->cb_color_dim = color.dim; 4273 rview->cb_color_info = color.info | 4274 S_028C70_RAT(1) | 4275 S_028C70_RESOURCE_TYPE(res_type); 4276 rview->cb_color_pitch = color.pitch; 4277 rview->cb_color_slice = color.slice; 4278 rview->cb_color_view = color.view; 4279 rview->cb_color_attrib = color.attrib; 4280 rview->cb_color_fmask = color.fmask; 4281 rview->cb_color_fmask_slice = color.fmask_slice; 4282 4283 if (image->target != PIPE_BUFFER) { 4284 memset(&tex_params, 0, sizeof(tex_params)); 4285 tex_params.pipe_format = iview->format; 4286 tex_params.force_level = 0; 4287 tex_params.width0 = image->width0; 4288 tex_params.height0 = image->height0; 4289 tex_params.first_level = iview->u.tex.level; 4290 tex_params.last_level = iview->u.tex.level; 4291 tex_params.first_layer = iview->u.tex.first_layer; 4292 tex_params.last_layer = iview->u.tex.last_layer; 4293 tex_params.target = image->target; 4294 tex_params.swizzle[0] = PIPE_SWIZZLE_X; 4295 tex_params.swizzle[1] = PIPE_SWIZZLE_Y; 4296 tex_params.swizzle[2] = PIPE_SWIZZLE_Z; 4297 tex_params.swizzle[3] = PIPE_SWIZZLE_W; 4298 evergreen_fill_tex_resource_words(rctx, &resource->b.b, &tex_params, 4299 &rview->skip_mip_address_reloc, 4300 rview->resource_words); 4301 4302 } else { 4303 memset(&buf_params, 0, sizeof(buf_params)); 4304 buf_params.pipe_format = iview->format; 4305 buf_params.size = iview->u.buf.size; 4306 buf_params.offset = iview->u.buf.offset; 4307 buf_params.swizzle[0] = PIPE_SWIZZLE_X; 4308 buf_params.swizzle[1] = PIPE_SWIZZLE_Y; 4309 buf_params.swizzle[2] = PIPE_SWIZZLE_Z; 4310 buf_params.swizzle[3] = PIPE_SWIZZLE_W; 4311 evergreen_fill_buffer_resource_words(rctx, &resource->b.b, 4312 &buf_params, 4313 &rview->skip_mip_address_reloc, 4314 rview->resource_words); 4315 } 4316 istate->enabled_mask |= (1 << i); 4317 } 4318 4319 for (i = start_slot + count, idx = 0; 4320 i < start_slot + count + unbind_num_trailing_slots; i++, idx++) { 4321 rview = &istate->views[i]; 4322 4323 pipe_resource_reference((struct pipe_resource **)&rview->base.resource, NULL); 4324 istate->enabled_mask &= ~(1 << i); 4325 istate->compressed_colortex_mask &= ~(1 << i); 4326 istate->compressed_depthtex_mask &= ~(1 << i); 4327 } 4328 4329 istate->atom.num_dw = util_bitcount(istate->enabled_mask) * 46; 4330 istate->dirty_buffer_constants = TRUE; 4331 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV; 4332 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB | 4333 R600_CONTEXT_FLUSH_AND_INV_CB_META; 4334 4335 if (old_mask != istate->enabled_mask) 4336 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom); 4337 4338 if (rctx->cb_misc_state.image_rat_enabled_mask != istate->enabled_mask) { 4339 rctx->cb_misc_state.image_rat_enabled_mask = istate->enabled_mask; 4340 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom); 4341 } 4342 4343 if (shader == PIPE_SHADER_FRAGMENT) 4344 r600_mark_atom_dirty(rctx, &istate->atom); 4345} 4346 4347static void evergreen_get_pipe_constant_buffer(struct r600_context *rctx, 4348 enum pipe_shader_type shader, uint slot, 4349 struct pipe_constant_buffer *cbuf) 4350{ 4351 struct r600_constbuf_state *state = &rctx->constbuf_state[shader]; 4352 struct pipe_constant_buffer *cb; 4353 cbuf->user_buffer = NULL; 4354 4355 cb = &state->cb[slot]; 4356 4357 cbuf->buffer_size = cb->buffer_size; 4358 pipe_resource_reference(&cbuf->buffer, cb->buffer); 4359} 4360 4361static void evergreen_get_shader_buffers(struct r600_context *rctx, 4362 enum pipe_shader_type shader, 4363 uint start_slot, uint count, 4364 struct pipe_shader_buffer *sbuf) 4365{ 4366 assert(shader == PIPE_SHADER_COMPUTE); 4367 int idx, i; 4368 struct r600_image_state *istate = &rctx->compute_buffers; 4369 struct r600_image_view *rview; 4370 4371 for (i = start_slot, idx = 0; i < start_slot + count; i++, idx++) { 4372 4373 rview = &istate->views[i]; 4374 4375 pipe_resource_reference(&sbuf[idx].buffer, rview->base.resource); 4376 if (rview->base.resource) { 4377 uint64_t rview_va = ((struct r600_resource *)rview->base.resource)->gpu_address; 4378 4379 uint64_t prog_va = rview->resource_words[0]; 4380 4381 prog_va += ((uint64_t)G_030008_BASE_ADDRESS_HI(rview->resource_words[2])) << 32; 4382 prog_va -= rview_va; 4383 4384 sbuf[idx].buffer_offset = prog_va & 0xffffffff; 4385 sbuf[idx].buffer_size = rview->resource_words[1] + 1;; 4386 } else { 4387 sbuf[idx].buffer_offset = 0; 4388 sbuf[idx].buffer_size = 0; 4389 } 4390 } 4391} 4392 4393static void evergreen_save_qbo_state(struct pipe_context *ctx, struct r600_qbo_state *st) 4394{ 4395 struct r600_context *rctx = (struct r600_context *)ctx; 4396 st->saved_compute = rctx->cs_shader_state.shader; 4397 4398 /* save constant buffer 0 */ 4399 evergreen_get_pipe_constant_buffer(rctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0); 4400 /* save ssbo 0 */ 4401 evergreen_get_shader_buffers(rctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo); 4402} 4403 4404 4405void evergreen_init_state_functions(struct r600_context *rctx) 4406{ 4407 unsigned id = 1; 4408 unsigned i; 4409 /* !!! 4410 * To avoid GPU lockup registers must be emitted in a specific order 4411 * (no kidding ...). The order below is important and have been 4412 * partially inferred from analyzing fglrx command stream. 4413 * 4414 * Don't reorder atom without carefully checking the effect (GPU lockup 4415 * or piglit regression). 4416 * !!! 4417 */ 4418 if (rctx->b.gfx_level == EVERGREEN) { 4419 r600_init_atom(rctx, &rctx->config_state.atom, id++, evergreen_emit_config_state, 11); 4420 rctx->config_state.dyn_gpr_enabled = true; 4421 } 4422 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0); 4423 r600_init_atom(rctx, &rctx->fragment_images.atom, id++, evergreen_emit_fragment_image_state, 0); 4424 r600_init_atom(rctx, &rctx->compute_images.atom, id++, evergreen_emit_compute_image_state, 0); 4425 r600_init_atom(rctx, &rctx->fragment_buffers.atom, id++, evergreen_emit_fragment_buffer_state, 0); 4426 r600_init_atom(rctx, &rctx->compute_buffers.atom, id++, evergreen_emit_compute_buffer_state, 0); 4427 /* shader const */ 4428 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0); 4429 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0); 4430 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0); 4431 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL].atom, id++, evergreen_emit_tcs_constant_buffers, 0); 4432 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL].atom, id++, evergreen_emit_tes_constant_buffers, 0); 4433 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE].atom, id++, evergreen_emit_cs_constant_buffers, 0); 4434 /* shader program */ 4435 r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0); 4436 /* sampler */ 4437 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, evergreen_emit_vs_sampler_states, 0); 4438 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, evergreen_emit_gs_sampler_states, 0); 4439 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].states.atom, id++, evergreen_emit_tcs_sampler_states, 0); 4440 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].states.atom, id++, evergreen_emit_tes_sampler_states, 0); 4441 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0); 4442 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].states.atom, id++, evergreen_emit_cs_sampler_states, 0); 4443 /* resources */ 4444 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0); 4445 r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0); 4446 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, evergreen_emit_vs_sampler_views, 0); 4447 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0); 4448 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views.atom, id++, evergreen_emit_tcs_sampler_views, 0); 4449 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views.atom, id++, evergreen_emit_tes_sampler_views, 0); 4450 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0); 4451 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views.atom, id++, evergreen_emit_cs_sampler_views, 0); 4452 4453 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10); 4454 4455 if (rctx->b.gfx_level == EVERGREEN) { 4456 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3); 4457 } else { 4458 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4); 4459 } 4460 rctx->sample_mask.sample_mask = ~0; 4461 4462 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6); 4463 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6); 4464 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0); 4465 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4); 4466 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 9); 4467 r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26); 4468 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 10); 4469 r600_init_atom(rctx, &rctx->db_state.atom, id++, evergreen_emit_db_state, 14); 4470 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0); 4471 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 9); 4472 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0); 4473 r600_add_atom(rctx, &rctx->b.scissors.atom, id++); 4474 r600_add_atom(rctx, &rctx->b.viewports.atom, id++); 4475 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4); 4476 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, evergreen_emit_vertex_fetch_shader, 5); 4477 r600_add_atom(rctx, &rctx->b.render_cond_atom, id++); 4478 r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++); 4479 r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++); 4480 for (i = 0; i < EG_NUM_HW_STAGES; i++) 4481 r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0); 4482 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, evergreen_emit_shader_stages, 15); 4483 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, evergreen_emit_gs_rings, 26); 4484 4485 rctx->b.b.create_blend_state = evergreen_create_blend_state; 4486 rctx->b.b.create_depth_stencil_alpha_state = evergreen_create_dsa_state; 4487 rctx->b.b.create_rasterizer_state = evergreen_create_rs_state; 4488 rctx->b.b.create_sampler_state = evergreen_create_sampler_state; 4489 rctx->b.b.create_sampler_view = evergreen_create_sampler_view; 4490 rctx->b.b.set_framebuffer_state = evergreen_set_framebuffer_state; 4491 rctx->b.b.set_polygon_stipple = evergreen_set_polygon_stipple; 4492 rctx->b.b.set_min_samples = evergreen_set_min_samples; 4493 rctx->b.b.set_tess_state = evergreen_set_tess_state; 4494 rctx->b.b.set_patch_vertices = evergreen_set_patch_vertices; 4495 rctx->b.b.set_hw_atomic_buffers = evergreen_set_hw_atomic_buffers; 4496 rctx->b.b.set_shader_images = evergreen_set_shader_images; 4497 rctx->b.b.set_shader_buffers = evergreen_set_shader_buffers; 4498 if (rctx->b.gfx_level == EVERGREEN) 4499 rctx->b.b.get_sample_position = evergreen_get_sample_position; 4500 else 4501 rctx->b.b.get_sample_position = cayman_get_sample_position; 4502 rctx->b.dma_copy = evergreen_dma_copy; 4503 rctx->b.save_qbo_state = evergreen_save_qbo_state; 4504 4505 evergreen_init_compute_state_functions(rctx); 4506} 4507 4508/** 4509 * This calculates the LDS size for tessellation shaders (VS, TCS, TES). 4510 * 4511 * The information about LDS and other non-compile-time parameters is then 4512 * written to the const buffer. 4513 4514 * const buffer contains - 4515 * uint32_t input_patch_size 4516 * uint32_t input_vertex_size 4517 * uint32_t num_tcs_input_cp 4518 * uint32_t num_tcs_output_cp; 4519 * uint32_t output_patch_size 4520 * uint32_t output_vertex_size 4521 * uint32_t output_patch0_offset 4522 * uint32_t perpatch_output_offset 4523 * and the same constbuf is bound to LS/HS/VS(ES). 4524 */ 4525void evergreen_setup_tess_constants(struct r600_context *rctx, const struct pipe_draw_info *info, unsigned *num_patches) 4526{ 4527 struct pipe_constant_buffer constbuf = {0}; 4528 struct r600_pipe_shader_selector *tcs = rctx->tcs_shader ? rctx->tcs_shader : rctx->tes_shader; 4529 struct r600_pipe_shader_selector *ls = rctx->vs_shader; 4530 unsigned num_tcs_input_cp = rctx->patch_vertices; 4531 unsigned num_tcs_outputs; 4532 unsigned num_tcs_output_cp; 4533 unsigned num_tcs_patch_outputs; 4534 unsigned num_tcs_inputs; 4535 unsigned input_vertex_size, output_vertex_size; 4536 unsigned input_patch_size, pervertex_output_patch_size, output_patch_size; 4537 unsigned output_patch0_offset, perpatch_output_offset, lds_size; 4538 uint32_t values[8]; 4539 unsigned num_waves; 4540 unsigned num_pipes = rctx->screen->b.info.r600_max_quad_pipes; 4541 unsigned wave_divisor = (16 * num_pipes); 4542 4543 *num_patches = 1; 4544 4545 if (!rctx->tes_shader) { 4546 rctx->lds_alloc = 0; 4547 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX, 4548 R600_LDS_INFO_CONST_BUFFER, false, NULL); 4549 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL, 4550 R600_LDS_INFO_CONST_BUFFER, false, NULL); 4551 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL, 4552 R600_LDS_INFO_CONST_BUFFER, false, NULL); 4553 return; 4554 } 4555 4556 if (rctx->lds_alloc != 0 && 4557 rctx->last_ls == ls && 4558 rctx->last_num_tcs_input_cp == num_tcs_input_cp && 4559 rctx->last_tcs == tcs) 4560 return; 4561 4562 num_tcs_inputs = util_last_bit64(ls->lds_outputs_written_mask); 4563 4564 if (rctx->tcs_shader) { 4565 num_tcs_outputs = util_last_bit64(tcs->lds_outputs_written_mask); 4566 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT]; 4567 num_tcs_patch_outputs = util_last_bit64(tcs->lds_patch_outputs_written_mask); 4568 } else { 4569 num_tcs_outputs = num_tcs_inputs; 4570 num_tcs_output_cp = num_tcs_input_cp; 4571 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */ 4572 } 4573 4574 /* size in bytes */ 4575 input_vertex_size = num_tcs_inputs * 16; 4576 output_vertex_size = num_tcs_outputs * 16; 4577 4578 input_patch_size = num_tcs_input_cp * input_vertex_size; 4579 4580 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size; 4581 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16; 4582 4583 output_patch0_offset = rctx->tcs_shader ? input_patch_size * *num_patches : 0; 4584 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size; 4585 4586 lds_size = output_patch0_offset + output_patch_size * *num_patches; 4587 4588 values[0] = input_patch_size; 4589 values[1] = input_vertex_size; 4590 values[2] = num_tcs_input_cp; 4591 values[3] = num_tcs_output_cp; 4592 4593 values[4] = output_patch_size; 4594 values[5] = output_vertex_size; 4595 values[6] = output_patch0_offset; 4596 values[7] = perpatch_output_offset; 4597 4598 /* docs say HS_NUM_WAVES - CEIL((LS_HS_CONFIG.NUM_PATCHES * 4599 LS_HS_CONFIG.HS_NUM_OUTPUT_CP) / (NUM_GOOD_PIPES * 16)) */ 4600 num_waves = ceilf((float)(*num_patches * num_tcs_output_cp) / (float)wave_divisor); 4601 4602 rctx->lds_alloc = (lds_size | (num_waves << 14)); 4603 4604 rctx->last_ls = ls; 4605 rctx->last_tcs = tcs; 4606 rctx->last_num_tcs_input_cp = num_tcs_input_cp; 4607 4608 constbuf.user_buffer = values; 4609 constbuf.buffer_size = 8 * 4; 4610 4611 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX, 4612 R600_LDS_INFO_CONST_BUFFER, false, &constbuf); 4613 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL, 4614 R600_LDS_INFO_CONST_BUFFER, false, &constbuf); 4615 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL, 4616 R600_LDS_INFO_CONST_BUFFER, true, &constbuf); 4617} 4618 4619uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx, 4620 const struct pipe_draw_info *info, 4621 unsigned num_patches) 4622{ 4623 unsigned num_output_cp; 4624 4625 if (!rctx->tes_shader) 4626 return 0; 4627 4628 num_output_cp = rctx->tcs_shader ? 4629 rctx->tcs_shader->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : 4630 rctx->patch_vertices; 4631 4632 return S_028B58_NUM_PATCHES(num_patches) | 4633 S_028B58_HS_NUM_INPUT_CP(rctx->patch_vertices) | 4634 S_028B58_HS_NUM_OUTPUT_CP(num_output_cp); 4635} 4636 4637void evergreen_set_ls_hs_config(struct r600_context *rctx, 4638 struct radeon_cmdbuf *cs, 4639 uint32_t ls_hs_config) 4640{ 4641 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config); 4642} 4643 4644void evergreen_set_lds_alloc(struct r600_context *rctx, 4645 struct radeon_cmdbuf *cs, 4646 uint32_t lds_alloc) 4647{ 4648 radeon_set_context_reg(cs, R_0288E8_SQ_LDS_ALLOC, lds_alloc); 4649} 4650 4651/* on evergreen if you are running tessellation you need to disable dynamic 4652 GPRs to workaround a hardware bug.*/ 4653bool evergreen_adjust_gprs(struct r600_context *rctx) 4654{ 4655 unsigned num_gprs[EG_NUM_HW_STAGES]; 4656 unsigned def_gprs[EG_NUM_HW_STAGES]; 4657 unsigned cur_gprs[EG_NUM_HW_STAGES]; 4658 unsigned new_gprs[EG_NUM_HW_STAGES]; 4659 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs; 4660 unsigned max_gprs; 4661 unsigned i; 4662 unsigned total_gprs; 4663 unsigned tmp[3]; 4664 bool rework = false, set_default = false, set_dirty = false; 4665 max_gprs = 0; 4666 for (i = 0; i < EG_NUM_HW_STAGES; i++) { 4667 def_gprs[i] = rctx->default_gprs[i]; 4668 max_gprs += def_gprs[i]; 4669 } 4670 max_gprs += def_num_clause_temp_gprs * 2; 4671 4672 /* if we have no TESS and dyn gpr is enabled then do nothing. */ 4673 if (!rctx->hw_shader_stages[EG_HW_STAGE_HS].shader) { 4674 if (rctx->config_state.dyn_gpr_enabled) 4675 return true; 4676 4677 /* transition back to dyn gpr enabled state */ 4678 rctx->config_state.dyn_gpr_enabled = true; 4679 r600_mark_atom_dirty(rctx, &rctx->config_state.atom); 4680 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE; 4681 return true; 4682 } 4683 4684 4685 /* gather required shader gprs */ 4686 for (i = 0; i < EG_NUM_HW_STAGES; i++) { 4687 if (rctx->hw_shader_stages[i].shader) 4688 num_gprs[i] = rctx->hw_shader_stages[i].shader->shader.bc.ngpr; 4689 else 4690 num_gprs[i] = 0; 4691 } 4692 4693 cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1); 4694 cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1); 4695 cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2); 4696 cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2); 4697 cur_gprs[EG_HW_STAGE_LS] = G_008C0C_NUM_LS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3); 4698 cur_gprs[EG_HW_STAGE_HS] = G_008C0C_NUM_HS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3); 4699 4700 total_gprs = 0; 4701 for (i = 0; i < EG_NUM_HW_STAGES; i++) { 4702 new_gprs[i] = num_gprs[i]; 4703 total_gprs += num_gprs[i]; 4704 } 4705 4706 if (total_gprs > (max_gprs - (2 * def_num_clause_temp_gprs))) 4707 return false; 4708 4709 for (i = 0; i < EG_NUM_HW_STAGES; i++) { 4710 if (new_gprs[i] > cur_gprs[i]) { 4711 rework = true; 4712 break; 4713 } 4714 } 4715 4716 if (rctx->config_state.dyn_gpr_enabled) { 4717 set_dirty = true; 4718 rctx->config_state.dyn_gpr_enabled = false; 4719 } 4720 4721 if (rework) { 4722 set_default = true; 4723 for (i = 0; i < EG_NUM_HW_STAGES; i++) { 4724 if (new_gprs[i] > def_gprs[i]) 4725 set_default = false; 4726 } 4727 4728 if (set_default) { 4729 for (i = 0; i < EG_NUM_HW_STAGES; i++) { 4730 new_gprs[i] = def_gprs[i]; 4731 } 4732 } else { 4733 unsigned ps_value = max_gprs; 4734 4735 ps_value -= (def_num_clause_temp_gprs * 2); 4736 for (i = R600_HW_STAGE_VS; i < EG_NUM_HW_STAGES; i++) 4737 ps_value -= new_gprs[i]; 4738 4739 new_gprs[R600_HW_STAGE_PS] = ps_value; 4740 } 4741 4742 tmp[0] = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) | 4743 S_008C04_NUM_VS_GPRS(new_gprs[R600_HW_STAGE_VS]) | 4744 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs); 4745 4746 tmp[1] = S_008C08_NUM_ES_GPRS(new_gprs[R600_HW_STAGE_ES]) | 4747 S_008C08_NUM_GS_GPRS(new_gprs[R600_HW_STAGE_GS]); 4748 4749 tmp[2] = S_008C0C_NUM_HS_GPRS(new_gprs[EG_HW_STAGE_HS]) | 4750 S_008C0C_NUM_LS_GPRS(new_gprs[EG_HW_STAGE_LS]); 4751 4752 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp[0] || 4753 rctx->config_state.sq_gpr_resource_mgmt_2 != tmp[1] || 4754 rctx->config_state.sq_gpr_resource_mgmt_3 != tmp[2]) { 4755 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp[0]; 4756 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp[1]; 4757 rctx->config_state.sq_gpr_resource_mgmt_3 = tmp[2]; 4758 set_dirty = true; 4759 } 4760 } 4761 4762 4763 if (set_dirty) { 4764 r600_mark_atom_dirty(rctx, &rctx->config_state.atom); 4765 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE; 4766 } 4767 return true; 4768} 4769 4770#define AC_ENCODE_TRACE_POINT(id) (0xcafe0000 | ((id) & 0xffff)) 4771 4772void eg_trace_emit(struct r600_context *rctx) 4773{ 4774 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; 4775 unsigned reloc; 4776 4777 if (rctx->b.gfx_level < EVERGREEN) 4778 return; 4779 4780 /* This must be done after r600_need_cs_space. */ 4781 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, 4782 (struct r600_resource*)rctx->trace_buf, RADEON_USAGE_WRITE | 4783 RADEON_PRIO_CP_DMA); 4784 4785 rctx->trace_id++; 4786 radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rctx->trace_buf, 4787 RADEON_USAGE_READWRITE | RADEON_PRIO_FENCE_TRACE); 4788 radeon_emit(cs, PKT3(PKT3_MEM_WRITE, 3, 0)); 4789 radeon_emit(cs, rctx->trace_buf->gpu_address); 4790 radeon_emit(cs, rctx->trace_buf->gpu_address >> 32 | MEM_WRITE_32_BITS | MEM_WRITE_CONFIRM); 4791 radeon_emit(cs, rctx->trace_id); 4792 radeon_emit(cs, 0); 4793 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); 4794 radeon_emit(cs, reloc); 4795 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); 4796 radeon_emit(cs, AC_ENCODE_TRACE_POINT(rctx->trace_id)); 4797} 4798 4799static void evergreen_emit_set_append_cnt(struct r600_context *rctx, 4800 struct r600_shader_atomic *atomic, 4801 struct r600_resource *resource, 4802 uint32_t pkt_flags) 4803{ 4804 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; 4805 unsigned reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, 4806 resource, 4807 RADEON_USAGE_READ | 4808 RADEON_PRIO_SHADER_RW_BUFFER); 4809 uint64_t dst_offset = resource->gpu_address + (atomic->start * 4); 4810 uint32_t base_reg_0 = R_02872C_GDS_APPEND_COUNT_0; 4811 4812 uint32_t reg_val = (base_reg_0 + atomic->hw_idx * 4 - EVERGREEN_CONTEXT_REG_OFFSET) >> 2; 4813 4814 radeon_emit(cs, PKT3(PKT3_SET_APPEND_CNT, 2, 0) | pkt_flags); 4815 radeon_emit(cs, (reg_val << 16) | 0x3); 4816 radeon_emit(cs, dst_offset & 0xfffffffc); 4817 radeon_emit(cs, (dst_offset >> 32) & 0xff); 4818 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); 4819 radeon_emit(cs, reloc); 4820} 4821 4822static void evergreen_emit_event_write_eos(struct r600_context *rctx, 4823 struct r600_shader_atomic *atomic, 4824 struct r600_resource *resource, 4825 uint32_t pkt_flags) 4826{ 4827 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; 4828 uint32_t event = EVENT_TYPE_PS_DONE; 4829 uint32_t base_reg_0 = R_02872C_GDS_APPEND_COUNT_0; 4830 uint32_t reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, 4831 resource, 4832 RADEON_USAGE_WRITE | 4833 RADEON_PRIO_SHADER_RW_BUFFER); 4834 uint64_t dst_offset = resource->gpu_address + (atomic->start * 4); 4835 uint32_t reg_val = (base_reg_0 + atomic->hw_idx * 4) >> 2; 4836 4837 if (pkt_flags == RADEON_CP_PACKET3_COMPUTE_MODE) 4838 event = EVENT_TYPE_CS_DONE; 4839 4840 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOS, 3, 0) | pkt_flags); 4841 radeon_emit(cs, EVENT_TYPE(event) | EVENT_INDEX(6)); 4842 radeon_emit(cs, (dst_offset) & 0xffffffff); 4843 radeon_emit(cs, (0 << 29) | ((dst_offset >> 32) & 0xff)); 4844 radeon_emit(cs, reg_val); 4845 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); 4846 radeon_emit(cs, reloc); 4847} 4848 4849static void cayman_emit_event_write_eos(struct r600_context *rctx, 4850 struct r600_shader_atomic *atomic, 4851 struct r600_resource *resource, 4852 uint32_t pkt_flags) 4853{ 4854 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; 4855 uint32_t event = EVENT_TYPE_PS_DONE; 4856 uint32_t reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, 4857 resource, 4858 RADEON_USAGE_WRITE | 4859 RADEON_PRIO_SHADER_RW_BUFFER); 4860 uint64_t dst_offset = resource->gpu_address + (atomic->start * 4); 4861 4862 if (pkt_flags == RADEON_CP_PACKET3_COMPUTE_MODE) 4863 event = EVENT_TYPE_CS_DONE; 4864 4865 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOS, 3, 0) | pkt_flags); 4866 radeon_emit(cs, EVENT_TYPE(event) | EVENT_INDEX(6)); 4867 radeon_emit(cs, (dst_offset) & 0xffffffff); 4868 radeon_emit(cs, (1 << 29) | ((dst_offset >> 32) & 0xff)); 4869 radeon_emit(cs, (atomic->hw_idx) | (1 << 16)); 4870 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); 4871 radeon_emit(cs, reloc); 4872} 4873 4874/* writes count from a buffer into GDS */ 4875static void cayman_write_count_to_gds(struct r600_context *rctx, 4876 struct r600_shader_atomic *atomic, 4877 struct r600_resource *resource, 4878 uint32_t pkt_flags) 4879{ 4880 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; 4881 unsigned reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, 4882 resource, 4883 RADEON_USAGE_READ | 4884 RADEON_PRIO_SHADER_RW_BUFFER); 4885 uint64_t dst_offset = resource->gpu_address + (atomic->start * 4); 4886 4887 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0) | pkt_flags); 4888 radeon_emit(cs, dst_offset & 0xffffffff); 4889 radeon_emit(cs, PKT3_CP_DMA_CP_SYNC | PKT3_CP_DMA_DST_SEL(1) | ((dst_offset >> 32) & 0xff));// GDS 4890 radeon_emit(cs, atomic->hw_idx * 4); 4891 radeon_emit(cs, 0); 4892 radeon_emit(cs, PKT3_CP_DMA_CMD_DAS | 4); 4893 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); 4894 radeon_emit(cs, reloc); 4895} 4896 4897void evergreen_emit_atomic_buffer_setup_count(struct r600_context *rctx, 4898 struct r600_pipe_shader *cs_shader, 4899 struct r600_shader_atomic *combined_atomics, 4900 uint8_t *atomic_used_mask_p) 4901{ 4902 uint8_t atomic_used_mask = 0; 4903 int i, j, k; 4904 bool is_compute = cs_shader ? true : false; 4905 4906 for (i = 0; i < (is_compute ? 1 : EG_NUM_HW_STAGES); i++) { 4907 uint8_t num_atomic_stage; 4908 struct r600_pipe_shader *pshader; 4909 4910 if (is_compute) 4911 pshader = cs_shader; 4912 else 4913 pshader = rctx->hw_shader_stages[i].shader; 4914 if (!pshader) 4915 continue; 4916 4917 num_atomic_stage = pshader->shader.nhwatomic_ranges; 4918 if (!num_atomic_stage) 4919 continue; 4920 4921 for (j = 0; j < num_atomic_stage; j++) { 4922 struct r600_shader_atomic *atomic = &pshader->shader.atomics[j]; 4923 int natomics = atomic->end - atomic->start + 1; 4924 4925 for (k = 0; k < natomics; k++) { 4926 /* seen this in a previous stage */ 4927 if (atomic_used_mask & (1u << (atomic->hw_idx + k))) 4928 continue; 4929 4930 combined_atomics[atomic->hw_idx + k].hw_idx = atomic->hw_idx + k; 4931 combined_atomics[atomic->hw_idx + k].buffer_id = atomic->buffer_id; 4932 combined_atomics[atomic->hw_idx + k].start = atomic->start + k; 4933 combined_atomics[atomic->hw_idx + k].end = combined_atomics[atomic->hw_idx + k].start + 1; 4934 atomic_used_mask |= (1u << (atomic->hw_idx + k)); 4935 } 4936 } 4937 } 4938 *atomic_used_mask_p = atomic_used_mask; 4939} 4940 4941void evergreen_emit_atomic_buffer_setup(struct r600_context *rctx, 4942 bool is_compute, 4943 struct r600_shader_atomic *combined_atomics, 4944 uint8_t atomic_used_mask) 4945{ 4946 struct r600_atomic_buffer_state *astate = &rctx->atomic_buffer_state; 4947 unsigned pkt_flags = 0; 4948 uint32_t mask; 4949 4950 if (is_compute) 4951 pkt_flags = RADEON_CP_PACKET3_COMPUTE_MODE; 4952 4953 mask = atomic_used_mask; 4954 if (!mask) 4955 return; 4956 4957 while (mask) { 4958 unsigned atomic_index = u_bit_scan(&mask); 4959 struct r600_shader_atomic *atomic = &combined_atomics[atomic_index]; 4960 struct r600_resource *resource = r600_resource(astate->buffer[atomic->buffer_id].buffer); 4961 assert(resource); 4962 4963 if (rctx->b.gfx_level == CAYMAN) 4964 cayman_write_count_to_gds(rctx, atomic, resource, pkt_flags); 4965 else 4966 evergreen_emit_set_append_cnt(rctx, atomic, resource, pkt_flags); 4967 } 4968} 4969 4970void evergreen_emit_atomic_buffer_save(struct r600_context *rctx, 4971 bool is_compute, 4972 struct r600_shader_atomic *combined_atomics, 4973 uint8_t *atomic_used_mask_p) 4974{ 4975 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs; 4976 struct r600_atomic_buffer_state *astate = &rctx->atomic_buffer_state; 4977 uint32_t pkt_flags = 0; 4978 uint32_t event = EVENT_TYPE_PS_DONE; 4979 uint32_t mask; 4980 uint64_t dst_offset; 4981 unsigned reloc; 4982 4983 if (is_compute) 4984 pkt_flags = RADEON_CP_PACKET3_COMPUTE_MODE; 4985 4986 mask = *atomic_used_mask_p; 4987 if (!mask) 4988 return; 4989 4990 while (mask) { 4991 unsigned atomic_index = u_bit_scan(&mask); 4992 struct r600_shader_atomic *atomic = &combined_atomics[atomic_index]; 4993 struct r600_resource *resource = r600_resource(astate->buffer[atomic->buffer_id].buffer); 4994 assert(resource); 4995 4996 if (rctx->b.gfx_level == CAYMAN) 4997 cayman_emit_event_write_eos(rctx, atomic, resource, pkt_flags); 4998 else 4999 evergreen_emit_event_write_eos(rctx, atomic, resource, pkt_flags); 5000 } 5001 5002 if (pkt_flags == RADEON_CP_PACKET3_COMPUTE_MODE) 5003 event = EVENT_TYPE_CS_DONE; 5004 5005 ++rctx->append_fence_id; 5006 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, 5007 r600_resource(rctx->append_fence), 5008 RADEON_USAGE_READWRITE | 5009 RADEON_PRIO_SHADER_RW_BUFFER); 5010 dst_offset = r600_resource(rctx->append_fence)->gpu_address; 5011 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOS, 3, 0) | pkt_flags); 5012 radeon_emit(cs, EVENT_TYPE(event) | EVENT_INDEX(6)); 5013 radeon_emit(cs, dst_offset & 0xffffffff); 5014 radeon_emit(cs, (2 << 29) | ((dst_offset >> 32) & 0xff)); 5015 radeon_emit(cs, rctx->append_fence_id); 5016 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); 5017 radeon_emit(cs, reloc); 5018 5019 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0) | pkt_flags); 5020 radeon_emit(cs, WAIT_REG_MEM_GEQUAL | WAIT_REG_MEM_MEMORY | (1 << 8)); 5021 radeon_emit(cs, dst_offset & 0xffffffff); 5022 radeon_emit(cs, ((dst_offset >> 32) & 0xff)); 5023 radeon_emit(cs, rctx->append_fence_id); 5024 radeon_emit(cs, 0xffffffff); 5025 radeon_emit(cs, 0xa); 5026 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); 5027 radeon_emit(cs, reloc); 5028} 5029