1/* 2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com> 3 * Copyright 2010 Marek Olšák <maraeo@gmail.com> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * on the rights to use, copy, modify, merge, publish, distribute, sub 9 * license, and/or sell copies of the Software, and to permit persons to whom 10 * the Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */ 23 24#include "compiler/nir/nir.h" 25#include "util/format/u_format.h" 26#include "util/format/u_format_s3tc.h" 27#include "util/u_screen.h" 28#include "util/u_memory.h" 29#include "util/os_time.h" 30#include "vl/vl_decoder.h" 31#include "vl/vl_video_buffer.h" 32 33#include "r300_context.h" 34#include "r300_texture.h" 35#include "r300_screen_buffer.h" 36#include "r300_state_inlines.h" 37#include "r300_public.h" 38 39#include "draw/draw_context.h" 40 41/* Return the identifier behind whom the brave coders responsible for this 42 * amalgamation of code, sweat, and duct tape, routinely obscure their names. 43 * 44 * ...I should have just put "Corbin Simpson", but I'm not that cool. 45 * 46 * (Or egotistical. Yet.) */ 47static const char* r300_get_vendor(struct pipe_screen* pscreen) 48{ 49 return "X.Org R300 Project"; 50} 51 52static const char* r300_get_device_vendor(struct pipe_screen* pscreen) 53{ 54 return "ATI"; 55} 56 57static const char* chip_families[] = { 58 "unknown", 59 "ATI R300", 60 "ATI R350", 61 "ATI RV350", 62 "ATI RV370", 63 "ATI RV380", 64 "ATI RS400", 65 "ATI RC410", 66 "ATI RS480", 67 "ATI R420", 68 "ATI R423", 69 "ATI R430", 70 "ATI R480", 71 "ATI R481", 72 "ATI RV410", 73 "ATI RS600", 74 "ATI RS690", 75 "ATI RS740", 76 "ATI RV515", 77 "ATI R520", 78 "ATI RV530", 79 "ATI R580", 80 "ATI RV560", 81 "ATI RV570" 82}; 83 84static const char* r300_get_family_name(struct r300_screen* r300screen) 85{ 86 return chip_families[r300screen->caps.family]; 87} 88 89static const char* r300_get_name(struct pipe_screen* pscreen) 90{ 91 struct r300_screen* r300screen = r300_screen(pscreen); 92 93 return r300_get_family_name(r300screen); 94} 95 96static void r300_disk_cache_create(struct r300_screen* r300screen) 97{ 98 struct mesa_sha1 ctx; 99 unsigned char sha1[20]; 100 char cache_id[20 * 2 + 1]; 101 102 _mesa_sha1_init(&ctx); 103 if (!disk_cache_get_function_identifier(r300_disk_cache_create, 104 &ctx)) 105 return; 106 107 _mesa_sha1_final(&ctx, sha1); 108 disk_cache_format_hex_id(cache_id, sha1, 20 * 2); 109 110 r300screen->disk_shader_cache = 111 disk_cache_create(r300_get_family_name(r300screen), 112 cache_id, 113 r300screen->debug); 114} 115 116static struct disk_cache* r300_get_disk_shader_cache(struct pipe_screen* pscreen) 117{ 118 struct r300_screen* r300screen = r300_screen(pscreen); 119 return r300screen->disk_shader_cache; 120} 121 122static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param) 123{ 124 struct r300_screen* r300screen = r300_screen(pscreen); 125 boolean is_r500 = r300screen->caps.is_r500; 126 127 switch (param) { 128 /* Supported features (boolean caps). */ 129 case PIPE_CAP_NPOT_TEXTURES: 130 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: 131 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS: 132 case PIPE_CAP_ANISOTROPIC_FILTER: 133 case PIPE_CAP_POINT_SPRITE: 134 case PIPE_CAP_OCCLUSION_QUERY: 135 case PIPE_CAP_TEXTURE_MIRROR_CLAMP: 136 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE: 137 case PIPE_CAP_BLEND_EQUATION_SEPARATE: 138 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: 139 case PIPE_CAP_FS_COORD_ORIGIN_UPPER_LEFT: 140 case PIPE_CAP_FS_COORD_PIXEL_CENTER_HALF_INTEGER: 141 case PIPE_CAP_CONDITIONAL_RENDER: 142 case PIPE_CAP_TEXTURE_BARRIER: 143 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: 144 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT: 145 case PIPE_CAP_CLIP_HALFZ: 146 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION: 147 case PIPE_CAP_LEGACY_MATH_RULES: 148 return 1; 149 150 case PIPE_CAP_TEXTURE_TRANSFER_MODES: 151 return PIPE_TEXTURE_TRANSFER_BLIT; 152 153 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT: 154 return R300_BUFFER_ALIGNMENT; 155 156 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: 157 return 16; 158 159 case PIPE_CAP_GLSL_FEATURE_LEVEL: 160 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY: 161 return 120; 162 163 /* r300 cannot do swizzling of compressed textures. Supported otherwise. */ 164 case PIPE_CAP_TEXTURE_SWIZZLE: 165 return r300screen->caps.dxtc_swizzle; 166 167 /* We don't support color clamping on r500, so that we can use color 168 * interpolators for generic varyings. */ 169 case PIPE_CAP_VERTEX_COLOR_CLAMPED: 170 return !is_r500; 171 172 /* Supported on r500 only. */ 173 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: 174 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: 175 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD: 176 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES: 177 return is_r500 ? 1 : 0; 178 179 case PIPE_CAP_SHAREABLE_SHADERS: 180 return 0; 181 182 case PIPE_CAP_MAX_GS_INVOCATIONS: 183 return 32; 184 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT: 185 return 1 << 27; 186 187 /* SWTCL-only features. */ 188 case PIPE_CAP_PRIMITIVE_RESTART: 189 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX: 190 case PIPE_CAP_USER_VERTEX_BUFFERS: 191 case PIPE_CAP_VS_WINDOW_SPACE_POSITION: 192 return !r300screen->caps.has_tcl; 193 194 /* HWTCL-only features / limitations. */ 195 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: 196 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: 197 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: 198 return r300screen->caps.has_tcl; 199 200 /* Texturing. */ 201 case PIPE_CAP_MAX_TEXTURE_2D_SIZE: 202 return is_r500 ? 4096 : 2048; 203 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: 204 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: 205 /* 13 == 4096, 12 == 2048 */ 206 return is_r500 ? 13 : 12; 207 208 /* Render targets. */ 209 case PIPE_CAP_MAX_RENDER_TARGETS: 210 return 4; 211 case PIPE_CAP_ENDIANNESS: 212 return PIPE_ENDIAN_LITTLE; 213 214 case PIPE_CAP_MAX_VIEWPORTS: 215 return 1; 216 217 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE: 218 return 2048; 219 220 case PIPE_CAP_MAX_VARYINGS: 221 return 10; 222 223 case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF: 224 return 0; 225 226 case PIPE_CAP_VENDOR_ID: 227 return 0x1002; 228 case PIPE_CAP_DEVICE_ID: 229 return r300screen->info.pci_id; 230 case PIPE_CAP_ACCELERATED: 231 return 1; 232 case PIPE_CAP_VIDEO_MEMORY: 233 return r300screen->info.vram_size_kb >> 10; 234 case PIPE_CAP_UMA: 235 return 0; 236 case PIPE_CAP_PCI_GROUP: 237 return r300screen->info.pci_domain; 238 case PIPE_CAP_PCI_BUS: 239 return r300screen->info.pci_bus; 240 case PIPE_CAP_PCI_DEVICE: 241 return r300screen->info.pci_dev; 242 case PIPE_CAP_PCI_FUNCTION: 243 return r300screen->info.pci_func; 244 default: 245 return u_pipe_screen_get_param_defaults(pscreen, param); 246 } 247} 248 249static int r300_get_shader_param(struct pipe_screen *pscreen, 250 enum pipe_shader_type shader, 251 enum pipe_shader_cap param) 252{ 253 struct r300_screen* r300screen = r300_screen(pscreen); 254 boolean is_r400 = r300screen->caps.is_r400; 255 boolean is_r500 = r300screen->caps.is_r500; 256 257 switch (param) { 258 case PIPE_SHADER_CAP_PREFERRED_IR: 259 return (r300screen->debug & DBG_USE_TGSI) ? PIPE_SHADER_IR_TGSI : PIPE_SHADER_IR_NIR; 260 case PIPE_SHADER_CAP_SUPPORTED_IRS: 261 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI); 262 default: 263 break; 264 } 265 266 switch (shader) { 267 case PIPE_SHADER_FRAGMENT: 268 switch (param) 269 { 270 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: 271 return is_r500 || is_r400 ? 512 : 96; 272 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: 273 return is_r500 || is_r400 ? 512 : 64; 274 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: 275 return is_r500 || is_r400 ? 512 : 32; 276 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: 277 return is_r500 ? 511 : 4; 278 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: 279 return is_r500 ? 64 : 0; /* Actually unlimited on r500. */ 280 /* Fragment shader limits. */ 281 case PIPE_SHADER_CAP_MAX_INPUTS: 282 /* 2 colors + 8 texcoords are always supported 283 * (minus fog and wpos). 284 * 285 * R500 has the ability to turn 3rd and 4th color into 286 * additional texcoords but there is no two-sided color 287 * selection then. However the facing bit can be used instead. */ 288 return 10; 289 case PIPE_SHADER_CAP_MAX_OUTPUTS: 290 return 4; 291 case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE: 292 return (is_r500 ? 256 : 32) * sizeof(float[4]); 293 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: 294 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: 295 return 1; 296 case PIPE_SHADER_CAP_MAX_TEMPS: 297 return is_r500 ? 128 : is_r400 ? 64 : 32; 298 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: 299 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: 300 return r300screen->caps.num_tex_units; 301 case PIPE_SHADER_CAP_CONT_SUPPORTED: 302 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: 303 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: 304 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: 305 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: 306 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: 307 case PIPE_SHADER_CAP_SUBROUTINES: 308 case PIPE_SHADER_CAP_INTEGERS: 309 case PIPE_SHADER_CAP_INT64_ATOMICS: 310 case PIPE_SHADER_CAP_FP16: 311 case PIPE_SHADER_CAP_FP16_DERIVATIVES: 312 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS: 313 case PIPE_SHADER_CAP_INT16: 314 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS: 315 case PIPE_SHADER_CAP_DROUND_SUPPORTED: 316 case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED: 317 case PIPE_SHADER_CAP_LDEXP_SUPPORTED: 318 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: 319 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: 320 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: 321 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: 322 return 0; 323 default: 324 break; 325 } 326 break; 327 case PIPE_SHADER_VERTEX: 328 switch (param) 329 { 330 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: 331 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: 332 case PIPE_SHADER_CAP_SUBROUTINES: 333 return 0; 334 default:; 335 } 336 337 if (!r300screen->caps.has_tcl) { 338 switch (param) { 339 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: 340 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: 341 return 0; 342 343 /* mesa/st requires that this cap is the same across stages, and the FS 344 * can't do ints. 345 */ 346 case PIPE_SHADER_CAP_INTEGERS: 347 return 0; 348 349 /* Even if gallivm NIR can do this, we call nir_to_tgsi manually and 350 * TGSI can't. 351 */ 352 case PIPE_SHADER_CAP_INT16: 353 case PIPE_SHADER_CAP_FP16: 354 case PIPE_SHADER_CAP_FP16_DERIVATIVES: 355 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS: 356 return 0; 357 358 /* While draw could normally handle this for the VS, the NIR lowering 359 * to regs can't handle our non-native-integers, so we have to lower to 360 * if ladders. 361 */ 362 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: 363 return 0; 364 default: 365 return draw_get_shader_param(shader, param); 366 } 367 } 368 369 switch (param) 370 { 371 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: 372 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: 373 return is_r500 ? 1024 : 256; 374 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: 375 return is_r500 ? 4 : 0; /* For loops; not sure about conditionals. */ 376 case PIPE_SHADER_CAP_MAX_INPUTS: 377 return 16; 378 case PIPE_SHADER_CAP_MAX_OUTPUTS: 379 return 10; 380 case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE: 381 return 256 * sizeof(float[4]); 382 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: 383 return 1; 384 case PIPE_SHADER_CAP_MAX_TEMPS: 385 return 32; 386 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: 387 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: 388 return 1; 389 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: 390 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: 391 case PIPE_SHADER_CAP_CONT_SUPPORTED: 392 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: 393 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: 394 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: 395 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: 396 case PIPE_SHADER_CAP_SUBROUTINES: 397 case PIPE_SHADER_CAP_INTEGERS: 398 case PIPE_SHADER_CAP_FP16: 399 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS: 400 case PIPE_SHADER_CAP_FP16_DERIVATIVES: 401 case PIPE_SHADER_CAP_INT16: 402 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS: 403 case PIPE_SHADER_CAP_INT64_ATOMICS: 404 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: 405 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: 406 case PIPE_SHADER_CAP_DROUND_SUPPORTED: 407 case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED: 408 case PIPE_SHADER_CAP_LDEXP_SUPPORTED: 409 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: 410 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: 411 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: 412 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: 413 return 0; 414 default: 415 break; 416 } 417 break; 418 default: 419 ; /* nothing */ 420 } 421 return 0; 422} 423 424static float r300_get_paramf(struct pipe_screen* pscreen, 425 enum pipe_capf param) 426{ 427 struct r300_screen* r300screen = r300_screen(pscreen); 428 429 switch (param) { 430 case PIPE_CAPF_MIN_LINE_WIDTH: 431 case PIPE_CAPF_MIN_LINE_WIDTH_AA: 432 case PIPE_CAPF_MIN_POINT_SIZE: 433 case PIPE_CAPF_MIN_POINT_SIZE_AA: 434 return 1; 435 case PIPE_CAPF_POINT_SIZE_GRANULARITY: 436 case PIPE_CAPF_LINE_WIDTH_GRANULARITY: 437 return 0.1; 438 case PIPE_CAPF_MAX_LINE_WIDTH: 439 case PIPE_CAPF_MAX_LINE_WIDTH_AA: 440 case PIPE_CAPF_MAX_POINT_SIZE: 441 case PIPE_CAPF_MAX_POINT_SIZE_AA: 442 /* The maximum dimensions of the colorbuffer are our practical 443 * rendering limits. 2048 pixels should be enough for anybody. */ 444 if (r300screen->caps.is_r500) { 445 return 4096.0f; 446 } else if (r300screen->caps.is_r400) { 447 return 4021.0f; 448 } else { 449 return 2560.0f; 450 } 451 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY: 452 return 16.0f; 453 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: 454 return 16.0f; 455 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE: 456 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE: 457 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY: 458 return 0.0f; 459 default: 460 debug_printf("r300: Warning: Unknown CAP %d in get_paramf.\n", 461 param); 462 return 0.0f; 463 } 464} 465 466static int r300_get_video_param(struct pipe_screen *screen, 467 enum pipe_video_profile profile, 468 enum pipe_video_entrypoint entrypoint, 469 enum pipe_video_cap param) 470{ 471 switch (param) { 472 case PIPE_VIDEO_CAP_SUPPORTED: 473 return vl_profile_supported(screen, profile, entrypoint); 474 case PIPE_VIDEO_CAP_NPOT_TEXTURES: 475 return 0; 476 case PIPE_VIDEO_CAP_MAX_WIDTH: 477 case PIPE_VIDEO_CAP_MAX_HEIGHT: 478 return vl_video_buffer_max_size(screen); 479 case PIPE_VIDEO_CAP_PREFERED_FORMAT: 480 return PIPE_FORMAT_NV12; 481 case PIPE_VIDEO_CAP_PREFERS_INTERLACED: 482 return false; 483 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: 484 return false; 485 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE: 486 return true; 487 case PIPE_VIDEO_CAP_MAX_LEVEL: 488 return vl_level_supported(screen, profile); 489 default: 490 return 0; 491 } 492} 493 494#define COMMON_NIR_OPTIONS \ 495 .fdot_replicates = true, \ 496 .fuse_ffma32 = true, \ 497 .fuse_ffma64 = true, \ 498 .lower_bitops = true, \ 499 .lower_extract_byte = true, \ 500 .lower_extract_word = true, \ 501 .lower_fdiv = true, \ 502 .lower_fdph = true, \ 503 .lower_flrp32 = true, \ 504 .lower_flrp64 = true, \ 505 .lower_fmod = true, \ 506 .lower_fround_even = true, \ 507 .lower_insert_byte = true, \ 508 .lower_insert_word = true, \ 509 .lower_rotate = true, \ 510 .lower_uniforms_to_ubo = true, \ 511 .lower_vector_cmp = true, \ 512 .no_integers = true, \ 513 .use_interpolated_input_intrinsics = true 514 515static const nir_shader_compiler_options r500_vs_compiler_options = { 516 COMMON_NIR_OPTIONS, 517 518 /* Have HW loops support and 1024 max instr count, but don't unroll *too* 519 * hard. 520 */ 521 .max_unroll_iterations = 32, 522}; 523 524static const nir_shader_compiler_options r500_fs_compiler_options = { 525 COMMON_NIR_OPTIONS, 526 .lower_fpow = true, /* POW is only in the VS */ 527 528 /* Have HW loops support and 512 max instr count, but don't unroll *too* 529 * hard. 530 */ 531 .max_unroll_iterations = 32, 532}; 533 534static const nir_shader_compiler_options r300_vs_compiler_options = { 535 COMMON_NIR_OPTIONS, 536 .lower_fsat = true, /* No fsat in pre-r500 VS */ 537 .lower_sincos = true, 538 539 /* Note: has HW loops support, but only 256 ALU instructions. */ 540 .max_unroll_iterations = 32, 541}; 542 543static const nir_shader_compiler_options r300_fs_compiler_options = { 544 COMMON_NIR_OPTIONS, 545 .lower_fpow = true, /* POW is only in the VS */ 546 .lower_sincos = true, 547 548 /* No HW loops support, so set it equal to ALU instr max */ 549 .max_unroll_iterations = 64, 550}; 551 552static const void * 553r300_get_compiler_options(struct pipe_screen *pscreen, 554 enum pipe_shader_ir ir, 555 enum pipe_shader_type shader) 556{ 557 struct r300_screen* r300screen = r300_screen(pscreen); 558 559 assert(ir == PIPE_SHADER_IR_NIR); 560 561 if (r300screen->caps.is_r500) { 562 if (shader == PIPE_SHADER_VERTEX) 563 return &r500_vs_compiler_options; 564 else 565 return &r500_fs_compiler_options; 566 } else { 567 if (shader == PIPE_SHADER_VERTEX) 568 return &r300_vs_compiler_options; 569 else 570 return &r300_fs_compiler_options; 571 } 572} 573 574/** 575 * Whether the format matches: 576 * PIPE_FORMAT_?10?10?10?2_UNORM 577 */ 578static inline boolean 579util_format_is_rgba1010102_variant(const struct util_format_description *desc) 580{ 581 static const unsigned size[4] = {10, 10, 10, 2}; 582 unsigned chan; 583 584 if (desc->block.width != 1 || 585 desc->block.height != 1 || 586 desc->block.bits != 32) 587 return FALSE; 588 589 for (chan = 0; chan < 4; ++chan) { 590 if(desc->channel[chan].type != UTIL_FORMAT_TYPE_UNSIGNED && 591 desc->channel[chan].type != UTIL_FORMAT_TYPE_VOID) 592 return FALSE; 593 if (desc->channel[chan].size != size[chan]) 594 return FALSE; 595 } 596 597 return TRUE; 598} 599 600static bool r300_is_blending_supported(struct r300_screen *rscreen, 601 enum pipe_format format) 602{ 603 int c; 604 const struct util_format_description *desc = 605 util_format_description(format); 606 607 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) 608 return false; 609 610 c = util_format_get_first_non_void_channel(format); 611 612 /* RGBA16F */ 613 if (rscreen->caps.is_r500 && 614 desc->nr_channels == 4 && 615 desc->channel[c].size == 16 && 616 desc->channel[c].type == UTIL_FORMAT_TYPE_FLOAT) 617 return true; 618 619 if (desc->channel[c].normalized && 620 desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED && 621 desc->channel[c].size >= 4 && 622 desc->channel[c].size <= 10) { 623 /* RGB10_A2, RGBA8, RGB5_A1, RGBA4, RGB565 */ 624 if (desc->nr_channels >= 3) 625 return true; 626 627 if (format == PIPE_FORMAT_R8G8_UNORM) 628 return true; 629 630 /* R8, I8, L8, A8 */ 631 if (desc->nr_channels == 1) 632 return true; 633 } 634 635 return false; 636} 637 638static bool r300_is_format_supported(struct pipe_screen* screen, 639 enum pipe_format format, 640 enum pipe_texture_target target, 641 unsigned sample_count, 642 unsigned storage_sample_count, 643 unsigned usage) 644{ 645 uint32_t retval = 0; 646 boolean is_r500 = r300_screen(screen)->caps.is_r500; 647 boolean is_r400 = r300_screen(screen)->caps.is_r400; 648 boolean is_color2101010 = format == PIPE_FORMAT_R10G10B10A2_UNORM || 649 format == PIPE_FORMAT_R10G10B10X2_SNORM || 650 format == PIPE_FORMAT_B10G10R10A2_UNORM || 651 format == PIPE_FORMAT_B10G10R10X2_UNORM || 652 format == PIPE_FORMAT_R10SG10SB10SA2U_NORM; 653 boolean is_ati1n = format == PIPE_FORMAT_RGTC1_UNORM || 654 format == PIPE_FORMAT_RGTC1_SNORM || 655 format == PIPE_FORMAT_LATC1_UNORM || 656 format == PIPE_FORMAT_LATC1_SNORM; 657 boolean is_ati2n = format == PIPE_FORMAT_RGTC2_UNORM || 658 format == PIPE_FORMAT_RGTC2_SNORM || 659 format == PIPE_FORMAT_LATC2_UNORM || 660 format == PIPE_FORMAT_LATC2_SNORM; 661 boolean is_half_float = format == PIPE_FORMAT_R16_FLOAT || 662 format == PIPE_FORMAT_R16G16_FLOAT || 663 format == PIPE_FORMAT_R16G16B16_FLOAT || 664 format == PIPE_FORMAT_R16G16B16A16_FLOAT || 665 format == PIPE_FORMAT_R16G16B16X16_FLOAT; 666 const struct util_format_description *desc; 667 668 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count)) 669 return false; 670 671 /* Check multisampling support. */ 672 switch (sample_count) { 673 case 0: 674 case 1: 675 break; 676 case 2: 677 case 4: 678 case 6: 679 /* No texturing and scanout. */ 680 if (usage & (PIPE_BIND_SAMPLER_VIEW | 681 PIPE_BIND_DISPLAY_TARGET | 682 PIPE_BIND_SCANOUT)) { 683 return false; 684 } 685 686 desc = util_format_description(format); 687 688 if (is_r500) { 689 /* Only allow depth/stencil, RGBA8, RGBA1010102, RGBA16F. */ 690 if (!util_format_is_depth_or_stencil(format) && 691 !util_format_is_rgba8_variant(desc) && 692 !util_format_is_rgba1010102_variant(desc) && 693 format != PIPE_FORMAT_R16G16B16A16_FLOAT && 694 format != PIPE_FORMAT_R16G16B16X16_FLOAT) { 695 return false; 696 } 697 } else { 698 /* Only allow depth/stencil, RGBA8. */ 699 if (!util_format_is_depth_or_stencil(format) && 700 !util_format_is_rgba8_variant(desc)) { 701 return false; 702 } 703 } 704 break; 705 default: 706 return false; 707 } 708 709 /* Check sampler format support. */ 710 if ((usage & PIPE_BIND_SAMPLER_VIEW) && 711 /* these two are broken for an unknown reason */ 712 format != PIPE_FORMAT_R8G8B8X8_SNORM && 713 format != PIPE_FORMAT_R16G16B16X16_SNORM && 714 /* ATI1N is r5xx-only. */ 715 (is_r500 || !is_ati1n) && 716 /* ATI2N is supported on r4xx-r5xx. */ 717 (is_r400 || is_r500 || !is_ati2n) && 718 r300_is_sampler_format_supported(format)) { 719 retval |= PIPE_BIND_SAMPLER_VIEW; 720 } 721 722 /* Check colorbuffer format support. */ 723 if ((usage & (PIPE_BIND_RENDER_TARGET | 724 PIPE_BIND_DISPLAY_TARGET | 725 PIPE_BIND_SCANOUT | 726 PIPE_BIND_SHARED | 727 PIPE_BIND_BLENDABLE)) && 728 /* 2101010 cannot be rendered to on non-r5xx. */ 729 (!is_color2101010 || is_r500) && 730 r300_is_colorbuffer_format_supported(format)) { 731 retval |= usage & 732 (PIPE_BIND_RENDER_TARGET | 733 PIPE_BIND_DISPLAY_TARGET | 734 PIPE_BIND_SCANOUT | 735 PIPE_BIND_SHARED); 736 737 if (r300_is_blending_supported(r300_screen(screen), format)) { 738 retval |= usage & PIPE_BIND_BLENDABLE; 739 } 740 } 741 742 /* Check depth-stencil format support. */ 743 if (usage & PIPE_BIND_DEPTH_STENCIL && 744 r300_is_zs_format_supported(format)) { 745 retval |= PIPE_BIND_DEPTH_STENCIL; 746 } 747 748 /* Check vertex buffer format support. */ 749 if (usage & PIPE_BIND_VERTEX_BUFFER) { 750 if (r300_screen(screen)->caps.has_tcl) { 751 /* Half float is supported on >= R400. */ 752 if ((is_r400 || is_r500 || !is_half_float) && 753 r300_translate_vertex_data_type(format) != R300_INVALID_FORMAT) { 754 retval |= PIPE_BIND_VERTEX_BUFFER; 755 } 756 } else { 757 /* SW TCL */ 758 if (!util_format_is_pure_integer(format)) { 759 retval |= PIPE_BIND_VERTEX_BUFFER; 760 } 761 } 762 } 763 764 if (usage & PIPE_BIND_INDEX_BUFFER) { 765 if (format == PIPE_FORMAT_R8_UINT || 766 format == PIPE_FORMAT_R16_UINT || 767 format == PIPE_FORMAT_R32_UINT) 768 retval |= PIPE_BIND_INDEX_BUFFER; 769 } 770 771 return retval == usage; 772} 773 774static void r300_destroy_screen(struct pipe_screen* pscreen) 775{ 776 struct r300_screen* r300screen = r300_screen(pscreen); 777 struct radeon_winsys *rws = radeon_winsys(pscreen); 778 779 if (rws && !rws->unref(rws)) 780 return; 781 782 mtx_destroy(&r300screen->cmask_mutex); 783 slab_destroy_parent(&r300screen->pool_transfers); 784 785 disk_cache_destroy(r300screen->disk_shader_cache); 786 787 if (rws) 788 rws->destroy(rws); 789 790 FREE(r300screen); 791} 792 793static void r300_fence_reference(struct pipe_screen *screen, 794 struct pipe_fence_handle **ptr, 795 struct pipe_fence_handle *fence) 796{ 797 struct radeon_winsys *rws = r300_screen(screen)->rws; 798 799 rws->fence_reference(ptr, fence); 800} 801 802static bool r300_fence_finish(struct pipe_screen *screen, 803 struct pipe_context *ctx, 804 struct pipe_fence_handle *fence, 805 uint64_t timeout) 806{ 807 struct radeon_winsys *rws = r300_screen(screen)->rws; 808 809 return rws->fence_wait(rws, fence, timeout); 810} 811 812struct pipe_screen* r300_screen_create(struct radeon_winsys *rws, 813 const struct pipe_screen_config *config) 814{ 815 struct r300_screen *r300screen = CALLOC_STRUCT(r300_screen); 816 817 if (!r300screen) { 818 FREE(r300screen); 819 return NULL; 820 } 821 822 rws->query_info(rws, &r300screen->info, false, false); 823 824 r300_init_debug(r300screen); 825 r300_parse_chipset(r300screen->info.pci_id, &r300screen->caps); 826 827 if (SCREEN_DBG_ON(r300screen, DBG_NO_ZMASK)) 828 r300screen->caps.zmask_ram = 0; 829 if (SCREEN_DBG_ON(r300screen, DBG_NO_HIZ)) 830 r300screen->caps.hiz_ram = 0; 831 if (SCREEN_DBG_ON(r300screen, DBG_NO_TCL)) 832 r300screen->caps.has_tcl = FALSE; 833 834 r300screen->rws = rws; 835 r300screen->screen.destroy = r300_destroy_screen; 836 r300screen->screen.get_name = r300_get_name; 837 r300screen->screen.get_vendor = r300_get_vendor; 838 r300screen->screen.get_compiler_options = r300_get_compiler_options; 839 r300screen->screen.get_device_vendor = r300_get_device_vendor; 840 r300screen->screen.get_disk_shader_cache = r300_get_disk_shader_cache; 841 r300screen->screen.get_param = r300_get_param; 842 r300screen->screen.get_shader_param = r300_get_shader_param; 843 r300screen->screen.get_paramf = r300_get_paramf; 844 r300screen->screen.get_video_param = r300_get_video_param; 845 r300screen->screen.is_format_supported = r300_is_format_supported; 846 r300screen->screen.is_video_format_supported = vl_video_buffer_is_format_supported; 847 r300screen->screen.context_create = r300_create_context; 848 r300screen->screen.fence_reference = r300_fence_reference; 849 r300screen->screen.fence_finish = r300_fence_finish; 850 851 r300_init_screen_resource_functions(r300screen); 852 853 r300_disk_cache_create(r300screen); 854 855 slab_create_parent(&r300screen->pool_transfers, sizeof(struct pipe_transfer), 64); 856 857 (void) mtx_init(&r300screen->cmask_mutex, mtx_plain); 858 859 return &r300screen->screen; 860} 861