1/* 2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com> 3 * Copyright 2009 Marek Olšák <maraeo@gmail.com> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * on the rights to use, copy, modify, merge, publish, distribute, sub 9 * license, and/or sell copies of the Software, and to permit persons to whom 10 * the Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */ 23 24/* r300_emit: Functions for emitting state. */ 25 26#include "util/format/u_format.h" 27#include "util/u_math.h" 28 29#include "r300_context.h" 30#include "r300_cb.h" 31#include "r300_cs.h" 32#include "r300_emit.h" 33#include "r300_fs.h" 34#include "r300_screen.h" 35#include "r300_screen_buffer.h" 36#include "r300_vs.h" 37 38void r300_emit_blend_state(struct r300_context* r300, 39 unsigned size, void* state) 40{ 41 struct r300_blend_state* blend = (struct r300_blend_state*)state; 42 struct pipe_framebuffer_state* fb = 43 (struct pipe_framebuffer_state*)r300->fb_state.state; 44 struct pipe_surface *cb; 45 CS_LOCALS(r300); 46 47 cb = fb->nr_cbufs ? r300_get_nonnull_cb(fb, 0) : NULL; 48 49 if (cb) { 50 if (cb->format == PIPE_FORMAT_R16G16B16A16_FLOAT) { 51 WRITE_CS_TABLE(blend->cb_noclamp, size); 52 } else if (cb->format == PIPE_FORMAT_R16G16B16X16_FLOAT) { 53 WRITE_CS_TABLE(blend->cb_noclamp_noalpha, size); 54 } else { 55 unsigned swz = r300_surface(cb)->colormask_swizzle; 56 WRITE_CS_TABLE(blend->cb_clamp[swz], size); 57 } 58 } else { 59 WRITE_CS_TABLE(blend->cb_no_readwrite, size); 60 } 61} 62 63void r300_emit_blend_color_state(struct r300_context* r300, 64 unsigned size, void* state) 65{ 66 struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state; 67 CS_LOCALS(r300); 68 69 WRITE_CS_TABLE(bc->cb, size); 70} 71 72void r300_emit_clip_state(struct r300_context* r300, 73 unsigned size, void* state) 74{ 75 struct r300_clip_state* clip = (struct r300_clip_state*)state; 76 CS_LOCALS(r300); 77 78 WRITE_CS_TABLE(clip->cb, size); 79} 80 81void r300_emit_dsa_state(struct r300_context* r300, unsigned size, void* state) 82{ 83 struct r300_dsa_state* dsa = (struct r300_dsa_state*)state; 84 struct pipe_framebuffer_state* fb = 85 (struct pipe_framebuffer_state*)r300->fb_state.state; 86 boolean is_r500 = r300->screen->caps.is_r500; 87 CS_LOCALS(r300); 88 uint32_t alpha_func = dsa->alpha_function; 89 90 /* Choose the alpha ref value between 8-bit (FG_ALPHA_FUNC.AM_VAL) and 91 * 16-bit (FG_ALPHA_VALUE). */ 92 if (is_r500 && (alpha_func & R300_FG_ALPHA_FUNC_ENABLE)) { 93 struct pipe_surface *cb = fb->nr_cbufs ? r300_get_nonnull_cb(fb, 0) : NULL; 94 95 if (cb && 96 (cb->format == PIPE_FORMAT_R16G16B16A16_FLOAT || 97 cb->format == PIPE_FORMAT_R16G16B16X16_FLOAT)) { 98 alpha_func |= R500_FG_ALPHA_FUNC_FP16_ENABLE; 99 } else { 100 alpha_func |= R500_FG_ALPHA_FUNC_8BIT; 101 } 102 } 103 104 /* Setup alpha-to-coverage. */ 105 if (r300->alpha_to_coverage && r300->msaa_enable) { 106 /* Always set 3/6, it improves precision even for 2x and 4x MSAA. */ 107 alpha_func |= R300_FG_ALPHA_FUNC_MASK_ENABLE | 108 R300_FG_ALPHA_FUNC_CFG_3_OF_6; 109 } 110 111 BEGIN_CS(size); 112 OUT_CS_REG(R300_FG_ALPHA_FUNC, alpha_func); 113 OUT_CS_TABLE(fb->zsbuf ? &dsa->cb_begin : dsa->cb_zb_no_readwrite, size-2); 114 END_CS; 115} 116 117static void get_rc_constant_state( 118 float vec[4], 119 struct r300_context * r300, 120 struct rc_constant * constant) 121{ 122 struct r300_textures_state* texstate = r300->textures_state.state; 123 struct r300_resource *tex; 124 125 assert(constant->Type == RC_CONSTANT_STATE); 126 127 /* vec should either be (0, 0, 0, 1), which should be a relatively safe 128 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE 129 * state factors. */ 130 131 switch (constant->u.State[0]) { 132 /* Factor for converting rectangle coords to 133 * normalized coords. Should only show up on non-r500. */ 134 case RC_STATE_R300_TEXRECT_FACTOR: 135 tex = r300_resource(texstate->sampler_views[constant->u.State[1]]->base.texture); 136 vec[0] = 1.0 / tex->tex.width0; 137 vec[1] = 1.0 / tex->tex.height0; 138 vec[2] = 0; 139 vec[3] = 1; 140 break; 141 142 case RC_STATE_R300_TEXSCALE_FACTOR: 143 tex = r300_resource(texstate->sampler_views[constant->u.State[1]]->base.texture); 144 /* Add a small number to the texture size to work around rounding errors in hw. */ 145 vec[0] = tex->b.width0 / (tex->tex.width0 + 0.001f); 146 vec[1] = tex->b.height0 / (tex->tex.height0 + 0.001f); 147 vec[2] = tex->b.depth0 / (tex->tex.depth0 + 0.001f); 148 vec[3] = 1; 149 break; 150 151 case RC_STATE_R300_VIEWPORT_SCALE: 152 vec[0] = r300->viewport.scale[0]; 153 vec[1] = r300->viewport.scale[1]; 154 vec[2] = r300->viewport.scale[2]; 155 vec[3] = 1; 156 break; 157 158 case RC_STATE_R300_VIEWPORT_OFFSET: 159 vec[0] = r300->viewport.translate[0]; 160 vec[1] = r300->viewport.translate[1]; 161 vec[2] = r300->viewport.translate[2]; 162 vec[3] = 1; 163 break; 164 165 default: 166 fprintf(stderr, "r300: Implementation error: " 167 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]); 168 vec[0] = 0; 169 vec[1] = 0; 170 vec[2] = 0; 171 vec[3] = 1; 172 } 173} 174 175/* Convert a normal single-precision float into the 7.16 format 176 * used by the R300 fragment shader. 177 */ 178uint32_t pack_float24(float f) 179{ 180 union { 181 float fl; 182 uint32_t u; 183 } u; 184 float mantissa; 185 int exponent; 186 uint32_t float24 = 0; 187 188 if (f == 0.0) 189 return 0; 190 191 u.fl = f; 192 193 mantissa = frexpf(f, &exponent); 194 195 /* Handle -ve */ 196 if (mantissa < 0) { 197 float24 |= (1 << 23); 198 mantissa = mantissa * -1.0; 199 } 200 /* Handle exponent, bias of 63 */ 201 exponent += 62; 202 float24 |= (exponent << 16); 203 /* Kill 7 LSB of mantissa */ 204 float24 |= (u.u & 0x7FFFFF) >> 7; 205 206 return float24; 207} 208 209void r300_emit_fs(struct r300_context* r300, unsigned size, void *state) 210{ 211 struct r300_fragment_shader *fs = r300_fs(r300); 212 CS_LOCALS(r300); 213 214 WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size); 215} 216 217void r300_emit_fs_constants(struct r300_context* r300, unsigned size, void *state) 218{ 219 struct r300_fragment_shader *fs = r300_fs(r300); 220 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state; 221 unsigned count = fs->shader->externals_count; 222 unsigned i, j; 223 CS_LOCALS(r300); 224 225 if (count == 0) 226 return; 227 228 BEGIN_CS(size); 229 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, count * 4); 230 if (buf->remap_table){ 231 for (i = 0; i < count; i++) { 232 float *data = (float*)&buf->ptr[buf->remap_table[i]*4]; 233 for (j = 0; j < 4; j++) 234 OUT_CS(pack_float24(data[j])); 235 } 236 } else { 237 for (i = 0; i < count; i++) 238 for (j = 0; j < 4; j++) 239 OUT_CS(pack_float24(*(float*)&buf->ptr[i*4+j])); 240 } 241 242 END_CS; 243} 244 245void r300_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state) 246{ 247 struct r300_fragment_shader *fs = r300_fs(r300); 248 struct rc_constant_list *constants = &fs->shader->code.constants; 249 unsigned i; 250 unsigned count = fs->shader->rc_state_count; 251 unsigned first = fs->shader->externals_count; 252 unsigned end = constants->Count; 253 unsigned j; 254 CS_LOCALS(r300); 255 256 if (count == 0) 257 return; 258 259 BEGIN_CS(size); 260 for(i = first; i < end; ++i) { 261 if (constants->Constants[i].Type == RC_CONSTANT_STATE) { 262 float data[4]; 263 264 get_rc_constant_state(data, r300, &constants->Constants[i]); 265 266 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X + i * 16, 4); 267 for (j = 0; j < 4; j++) 268 OUT_CS(pack_float24(data[j])); 269 } 270 } 271 END_CS; 272} 273 274void r500_emit_fs(struct r300_context* r300, unsigned size, void *state) 275{ 276 struct r300_fragment_shader *fs = r300_fs(r300); 277 CS_LOCALS(r300); 278 279 WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size); 280} 281 282void r500_emit_fs_constants(struct r300_context* r300, unsigned size, void *state) 283{ 284 struct r300_fragment_shader *fs = r300_fs(r300); 285 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state; 286 unsigned count = fs->shader->externals_count; 287 CS_LOCALS(r300); 288 289 if (count == 0) 290 return; 291 292 BEGIN_CS(size); 293 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST); 294 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, count * 4); 295 if (buf->remap_table){ 296 for (unsigned i = 0; i < count; i++) { 297 uint32_t *data = &buf->ptr[buf->remap_table[i]*4]; 298 OUT_CS_TABLE(data, 4); 299 } 300 } else { 301 OUT_CS_TABLE(buf->ptr, count * 4); 302 } 303 END_CS; 304} 305 306void r500_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state) 307{ 308 struct r300_fragment_shader *fs = r300_fs(r300); 309 struct rc_constant_list *constants = &fs->shader->code.constants; 310 unsigned i; 311 unsigned count = fs->shader->rc_state_count; 312 unsigned first = fs->shader->externals_count; 313 unsigned end = constants->Count; 314 CS_LOCALS(r300); 315 316 if (count == 0) 317 return; 318 319 BEGIN_CS(size); 320 for(i = first; i < end; ++i) { 321 if (constants->Constants[i].Type == RC_CONSTANT_STATE) { 322 float data[4]; 323 324 get_rc_constant_state(data, r300, &constants->Constants[i]); 325 326 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, 327 R500_GA_US_VECTOR_INDEX_TYPE_CONST | 328 (i & R500_GA_US_VECTOR_INDEX_MASK)); 329 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, 4); 330 OUT_CS_TABLE(data, 4); 331 } 332 } 333 END_CS; 334} 335 336void r300_emit_gpu_flush(struct r300_context *r300, unsigned size, void *state) 337{ 338 struct r300_gpu_flush *gpuflush = (struct r300_gpu_flush*)state; 339 struct pipe_framebuffer_state* fb = 340 (struct pipe_framebuffer_state*)r300->fb_state.state; 341 uint32_t height = fb->height; 342 uint32_t width = fb->width; 343 CS_LOCALS(r300); 344 345 if (r300->cbzb_clear) { 346 struct r300_surface *surf = r300_surface(fb->cbufs[0]); 347 348 height = surf->cbzb_height; 349 width = surf->cbzb_width; 350 } 351 352 DBG(r300, DBG_SCISSOR, 353 "r300: Scissor width: %i, height: %i, CBZB clear: %s\n", 354 width, height, r300->cbzb_clear ? "YES" : "NO"); 355 356 BEGIN_CS(size); 357 358 /* Set up scissors. 359 * By writing to the SC registers, SC & US assert idle. */ 360 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2); 361 if (r300->screen->caps.is_r500) { 362 OUT_CS(0); 363 OUT_CS(((width - 1) << R300_SCISSORS_X_SHIFT) | 364 ((height - 1) << R300_SCISSORS_Y_SHIFT)); 365 } else { 366 OUT_CS((1440 << R300_SCISSORS_X_SHIFT) | 367 (1440 << R300_SCISSORS_Y_SHIFT)); 368 OUT_CS(((width + 1440-1) << R300_SCISSORS_X_SHIFT) | 369 ((height + 1440-1) << R300_SCISSORS_Y_SHIFT)); 370 } 371 372 /* Flush CB & ZB caches and wait until the 3D engine is idle and clean. */ 373 OUT_CS_TABLE(gpuflush->cb_flush_clean, 6); 374 END_CS; 375} 376 377void r300_emit_aa_state(struct r300_context *r300, unsigned size, void *state) 378{ 379 struct r300_aa_state *aa = (struct r300_aa_state*)state; 380 CS_LOCALS(r300); 381 382 BEGIN_CS(size); 383 OUT_CS_REG(R300_GB_AA_CONFIG, aa->aa_config); 384 385 if (aa->dest) { 386 OUT_CS_REG_SEQ(R300_RB3D_AARESOLVE_OFFSET, 3); 387 OUT_CS(aa->dest->offset); 388 OUT_CS(aa->dest->pitch & R300_RB3D_AARESOLVE_PITCH_MASK); 389 OUT_CS(R300_RB3D_AARESOLVE_CTL_AARESOLVE_MODE_RESOLVE | 390 R300_RB3D_AARESOLVE_CTL_AARESOLVE_ALPHA_AVERAGE); 391 OUT_CS_RELOC(aa->dest); 392 } else { 393 OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, 0); 394 } 395 396 END_CS; 397} 398 399void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state) 400{ 401 struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state; 402 struct r300_surface* surf; 403 unsigned i; 404 uint32_t rb3d_cctl = 0; 405 406 CS_LOCALS(r300); 407 408 BEGIN_CS(size); 409 410 if (r300->screen->caps.is_r500) { 411 rb3d_cctl = R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE; 412 } 413 /* NUM_MULTIWRITES replicates COLOR[0] to all colorbuffers. */ 414 if (fb->nr_cbufs && r300->fb_multiwrite) { 415 rb3d_cctl |= R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs); 416 } 417 if (r300->cmask_in_use) { 418 rb3d_cctl |= R300_RB3D_CCTL_AA_COMPRESSION_ENABLE | 419 R300_RB3D_CCTL_CMASK_ENABLE; 420 } 421 422 OUT_CS_REG(R300_RB3D_CCTL, rb3d_cctl); 423 424 /* Set up colorbuffers. */ 425 for (i = 0; i < fb->nr_cbufs; i++) { 426 surf = r300_surface(r300_get_nonnull_cb(fb, i)); 427 428 OUT_CS_REG(R300_RB3D_COLOROFFSET0 + (4 * i), surf->offset); 429 OUT_CS_RELOC(surf); 430 431 OUT_CS_REG(R300_RB3D_COLORPITCH0 + (4 * i), surf->pitch); 432 OUT_CS_RELOC(surf); 433 434 if (r300->cmask_in_use && i == 0) { 435 OUT_CS_REG(R300_RB3D_CMASK_OFFSET0, 0); 436 OUT_CS_REG(R300_RB3D_CMASK_PITCH0, surf->pitch_cmask); 437 OUT_CS_REG(R300_RB3D_COLOR_CLEAR_VALUE, r300->color_clear_value); 438 if (r300->screen->caps.is_r500) { 439 OUT_CS_REG_SEQ(R500_RB3D_COLOR_CLEAR_VALUE_AR, 2); 440 OUT_CS(r300->color_clear_value_ar); 441 OUT_CS(r300->color_clear_value_gb); 442 } 443 } 444 } 445 446 /* Set up the ZB part of the CBZB clear. */ 447 if (r300->cbzb_clear) { 448 surf = r300_surface(fb->cbufs[0]); 449 450 OUT_CS_REG(R300_ZB_FORMAT, surf->cbzb_format); 451 452 OUT_CS_REG(R300_ZB_DEPTHOFFSET, surf->cbzb_midpoint_offset); 453 OUT_CS_RELOC(surf); 454 455 OUT_CS_REG(R300_ZB_DEPTHPITCH, surf->cbzb_pitch); 456 OUT_CS_RELOC(surf); 457 458 DBG(r300, DBG_CBZB, 459 "CBZB clearing cbuf %08x %08x\n", surf->cbzb_format, 460 surf->cbzb_pitch); 461 } 462 /* Set up a zbuffer. */ 463 else if (fb->zsbuf) { 464 surf = r300_surface(fb->zsbuf); 465 466 OUT_CS_REG(R300_ZB_FORMAT, surf->format); 467 468 OUT_CS_REG(R300_ZB_DEPTHOFFSET, surf->offset); 469 OUT_CS_RELOC(surf); 470 471 OUT_CS_REG(R300_ZB_DEPTHPITCH, surf->pitch); 472 OUT_CS_RELOC(surf); 473 474 if (r300->hyperz_enabled) { 475 /* HiZ RAM. */ 476 OUT_CS_REG(R300_ZB_HIZ_OFFSET, 0); 477 OUT_CS_REG(R300_ZB_HIZ_PITCH, surf->pitch_hiz); 478 /* Z Mask RAM. (compressed zbuffer) */ 479 OUT_CS_REG(R300_ZB_ZMASK_OFFSET, 0); 480 OUT_CS_REG(R300_ZB_ZMASK_PITCH, surf->pitch_zmask); 481 } 482 } 483 484 END_CS; 485} 486 487void r300_emit_hyperz_state(struct r300_context *r300, 488 unsigned size, void *state) 489{ 490 struct r300_hyperz_state *z = state; 491 CS_LOCALS(r300); 492 493 if (z->flush) 494 WRITE_CS_TABLE(&z->cb_flush_begin, size); 495 else 496 WRITE_CS_TABLE(&z->cb_begin, size - 2); 497} 498 499void r300_emit_hyperz_end(struct r300_context *r300) 500{ 501 struct r300_hyperz_state z = 502 *(struct r300_hyperz_state*)r300->hyperz_state.state; 503 504 z.flush = 1; 505 z.zb_bw_cntl = 0; 506 z.zb_depthclearvalue = 0; 507 z.sc_hyperz = R300_SC_HYPERZ_ADJ_2; 508 z.gb_z_peq_config = 0; 509 510 r300_emit_hyperz_state(r300, r300->hyperz_state.size, &z); 511} 512 513#define R300_NIBBLES(x0, y0, x1, y1, x2, y2, d0y, d0x) \ 514 (((x0) & 0xf) | (((y0) & 0xf) << 4) | \ 515 (((x1) & 0xf) << 8) | (((y1) & 0xf) << 12) | \ 516 (((x2) & 0xf) << 16) | (((y2) & 0xf) << 20) | \ 517 (((d0y) & 0xf) << 24) | (((d0x) & 0xf) << 28)) 518 519static unsigned r300_get_mspos(int index, unsigned *p) 520{ 521 unsigned reg, i, distx, disty, dist; 522 523 if (index == 0) { 524 /* MSPOS0 contains positions for samples 0,1,2 as (X,Y) pairs of nibbles, 525 * followed by a (Y,X) pair containing the minimum distance from the pixel 526 * edge: 527 * X0, Y0, X1, Y1, X2, Y2, D0_Y, D0_X 528 * 529 * There is a quirk when setting D0_X. The value represents the distance 530 * from the left edge of the pixel quad to the first sample in subpixels. 531 * All values less than eight should use the actual value, but „7‟ should 532 * be used for the distance „8‟. The hardware will convert 7 into 8 internally. 533 */ 534 distx = 11; 535 for (i = 0; i < 12; i += 2) { 536 if (p[i] < distx) 537 distx = p[i]; 538 } 539 540 disty = 11; 541 for (i = 1; i < 12; i += 2) { 542 if (p[i] < disty) 543 disty = p[i]; 544 } 545 546 if (distx == 8) 547 distx = 7; 548 549 reg = R300_NIBBLES(p[0], p[1], p[2], p[3], p[4], p[5], disty, distx); 550 } else { 551 /* MSPOS1 contains positions for samples 3,4,5 as (X,Y) pairs of nibbles, 552 * followed by the minimum distance from the pixel edge (not sure if X or Y): 553 * X3, Y3, X4, Y4, X5, Y5, D1 554 */ 555 dist = 11; 556 for (i = 0; i < 12; i++) { 557 if (p[i] < dist) 558 dist = p[i]; 559 } 560 561 reg = R300_NIBBLES(p[6], p[7], p[8], p[9], p[10], p[11], dist, 0); 562 } 563 return reg; 564} 565 566void r300_emit_fb_state_pipelined(struct r300_context *r300, 567 unsigned size, void *state) 568{ 569 /* The sample coordinates are in the range [0,11], because 570 * GB_TILE_CONFIG.SUBPIXEL is set to the 1/12 subpixel precision. 571 * 572 * Some sample coordinates reach to neighboring pixels and should not be used. 573 * (e.g. Y=11) 574 * 575 * The unused samples must be set to the positions of other valid samples. */ 576 static unsigned sample_locs_1x[12] = { 577 6,6, 6,6, 6,6, 6,6, 6,6, 6,6 578 }; 579 static unsigned sample_locs_2x[12] = { 580 3,9, 9,3, 9,3, 9,3, 9,3, 9,3 581 }; 582 static unsigned sample_locs_4x[12] = { 583 4,4, 8,8, 2,10, 10,2, 10,2, 10,2 584 }; 585 static unsigned sample_locs_6x[12] = { 586 3,1, 7,3, 11,5, 1,7, 5,9, 9,10 587 }; 588 589 struct pipe_framebuffer_state* fb = 590 (struct pipe_framebuffer_state*)r300->fb_state.state; 591 unsigned i, num_cbufs = fb->nr_cbufs; 592 unsigned mspos0, mspos1; 593 CS_LOCALS(r300); 594 595 /* If we use the multiwrite feature, the colorbuffers 2,3,4 must be 596 * marked as UNUSED in the US block. */ 597 if (r300->fb_multiwrite) { 598 num_cbufs = MIN2(num_cbufs, 1); 599 } 600 601 BEGIN_CS(size); 602 603 /* Colorbuffer format in the US block. 604 * (must be written after unpipelined regs) */ 605 OUT_CS_REG_SEQ(R300_US_OUT_FMT_0, 4); 606 for (i = 0; i < num_cbufs; i++) { 607 OUT_CS(r300_surface(r300_get_nonnull_cb(fb, i))->format); 608 } 609 for (; i < 1; i++) { 610 OUT_CS(R300_US_OUT_FMT_C4_8 | 611 R300_C0_SEL_B | R300_C1_SEL_G | 612 R300_C2_SEL_R | R300_C3_SEL_A); 613 } 614 for (; i < 4; i++) { 615 OUT_CS(R300_US_OUT_FMT_UNUSED); 616 } 617 618 /* Set sample positions. It depends on the framebuffer sample count. 619 * These are pipelined regs and as such cannot be moved to the AA state. 620 */ 621 switch (r300->num_samples) { 622 default: 623 mspos0 = r300_get_mspos(0, sample_locs_1x); 624 mspos1 = r300_get_mspos(1, sample_locs_1x); 625 break; 626 case 2: 627 mspos0 = r300_get_mspos(0, sample_locs_2x); 628 mspos1 = r300_get_mspos(1, sample_locs_2x); 629 break; 630 case 4: 631 mspos0 = r300_get_mspos(0, sample_locs_4x); 632 mspos1 = r300_get_mspos(1, sample_locs_4x); 633 break; 634 case 6: 635 mspos0 = r300_get_mspos(0, sample_locs_6x); 636 mspos1 = r300_get_mspos(1, sample_locs_6x); 637 break; 638 } 639 640 OUT_CS_REG_SEQ(R300_GB_MSPOS0, 2); 641 OUT_CS(mspos0); 642 OUT_CS(mspos1); 643 END_CS; 644} 645 646void r300_emit_query_start(struct r300_context *r300, unsigned size, void*state) 647{ 648 struct r300_query *query = r300->query_current; 649 CS_LOCALS(r300); 650 651 if (!query) 652 return; 653 654 BEGIN_CS(size); 655 if (r300->screen->caps.family == CHIP_RV530) { 656 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL); 657 } else { 658 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL); 659 } 660 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0); 661 END_CS; 662 query->begin_emitted = TRUE; 663} 664 665static void r300_emit_query_end_frag_pipes(struct r300_context *r300, 666 struct r300_query *query) 667{ 668 struct r300_capabilities* caps = &r300->screen->caps; 669 uint32_t gb_pipes = r300->screen->info.r300_num_gb_pipes; 670 CS_LOCALS(r300); 671 672 assert(gb_pipes); 673 674 BEGIN_CS(6 * gb_pipes + 2); 675 /* I'm not so sure I like this switch, but it's hard to be elegant 676 * when there's so many special cases... 677 * 678 * So here's the basic idea. For each pipe, enable writes to it only, 679 * then put out the relocation for ZPASS_ADDR, taking into account a 680 * 4-byte offset for each pipe. RV380 and older are special; they have 681 * only two pipes, and the second pipe's enable is on bit 3, not bit 1, 682 * so there's a chipset cap for that. */ 683 switch (gb_pipes) { 684 case 4: 685 /* pipe 3 only */ 686 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3); 687 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 3) * 4); 688 OUT_CS_RELOC(r300->query_current); 689 FALLTHROUGH; 690 case 3: 691 /* pipe 2 only */ 692 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2); 693 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 2) * 4); 694 OUT_CS_RELOC(r300->query_current); 695 FALLTHROUGH; 696 case 2: 697 /* pipe 1 only */ 698 /* As mentioned above, accommodate RV380 and older. */ 699 OUT_CS_REG(R300_SU_REG_DEST, 700 1 << (caps->high_second_pipe ? 3 : 1)); 701 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 1) * 4); 702 OUT_CS_RELOC(r300->query_current); 703 FALLTHROUGH; 704 case 1: 705 /* pipe 0 only */ 706 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0); 707 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 0) * 4); 708 OUT_CS_RELOC(r300->query_current); 709 break; 710 default: 711 fprintf(stderr, "r300: Implementation error: Chipset reports %d" 712 " pixel pipes!\n", gb_pipes); 713 abort(); 714 } 715 716 /* And, finally, reset it to normal... */ 717 OUT_CS_REG(R300_SU_REG_DEST, 0xF); 718 END_CS; 719} 720 721static void rv530_emit_query_end_single_z(struct r300_context *r300, 722 struct r300_query *query) 723{ 724 CS_LOCALS(r300); 725 726 BEGIN_CS(8); 727 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0); 728 OUT_CS_REG(R300_ZB_ZPASS_ADDR, query->num_results * 4); 729 OUT_CS_RELOC(r300->query_current); 730 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL); 731 END_CS; 732} 733 734static void rv530_emit_query_end_double_z(struct r300_context *r300, 735 struct r300_query *query) 736{ 737 CS_LOCALS(r300); 738 739 BEGIN_CS(14); 740 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0); 741 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 0) * 4); 742 OUT_CS_RELOC(r300->query_current); 743 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1); 744 OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 1) * 4); 745 OUT_CS_RELOC(r300->query_current); 746 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL); 747 END_CS; 748} 749 750void r300_emit_query_end(struct r300_context* r300) 751{ 752 struct r300_capabilities *caps = &r300->screen->caps; 753 struct r300_query *query = r300->query_current; 754 755 if (!query) 756 return; 757 758 if (query->begin_emitted == FALSE) 759 return; 760 761 if (caps->family == CHIP_RV530) { 762 if (r300->screen->info.r300_num_z_pipes == 2) 763 rv530_emit_query_end_double_z(r300, query); 764 else 765 rv530_emit_query_end_single_z(r300, query); 766 } else 767 r300_emit_query_end_frag_pipes(r300, query); 768 769 query->begin_emitted = FALSE; 770 query->num_results += query->num_pipes; 771 772 /* XXX grab all the results and reset the counter. */ 773 if (query->num_results >= query->buf->size / 4 - 4) { 774 query->num_results = (query->buf->size / 4) / 2; 775 fprintf(stderr, "r300: Rewinding OQBO...\n"); 776 } 777} 778 779void r300_emit_invariant_state(struct r300_context *r300, 780 unsigned size, void *state) 781{ 782 CS_LOCALS(r300); 783 WRITE_CS_TABLE(state, size); 784} 785 786void r300_emit_rs_state(struct r300_context* r300, unsigned size, void* state) 787{ 788 struct r300_rs_state* rs = state; 789 CS_LOCALS(r300); 790 791 BEGIN_CS(size); 792 OUT_CS_TABLE(rs->cb_main, RS_STATE_MAIN_SIZE); 793 if (rs->polygon_offset_enable) { 794 if (r300->zbuffer_bpp == 16) { 795 OUT_CS_TABLE(rs->cb_poly_offset_zb16, 5); 796 } else { 797 OUT_CS_TABLE(rs->cb_poly_offset_zb24, 5); 798 } 799 } 800 END_CS; 801} 802 803void r300_emit_rs_block_state(struct r300_context* r300, 804 unsigned size, void* state) 805{ 806 struct r300_rs_block* rs = (struct r300_rs_block*)state; 807 unsigned i; 808 /* It's the same for both INST and IP tables */ 809 unsigned count = (rs->inst_count & R300_RS_INST_COUNT_MASK) + 1; 810 CS_LOCALS(r300); 811 812 if (DBG_ON(r300, DBG_RS_BLOCK)) { 813 r500_dump_rs_block(rs); 814 815 fprintf(stderr, "r300: RS emit:\n"); 816 817 for (i = 0; i < count; i++) 818 fprintf(stderr, " : ip %d: 0x%08x\n", i, rs->ip[i]); 819 820 for (i = 0; i < count; i++) 821 fprintf(stderr, " : inst %d: 0x%08x\n", i, rs->inst[i]); 822 823 fprintf(stderr, " : count: 0x%08x inst_count: 0x%08x\n", 824 rs->count, rs->inst_count); 825 } 826 827 BEGIN_CS(size); 828 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2); 829 OUT_CS(rs->vap_vtx_state_cntl); 830 OUT_CS(rs->vap_vsm_vtx_assm); 831 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2); 832 OUT_CS(rs->vap_out_vtx_fmt[0]); 833 OUT_CS(rs->vap_out_vtx_fmt[1]); 834 OUT_CS_REG_SEQ(R300_GB_ENABLE, 1); 835 OUT_CS(rs->gb_enable); 836 837 if (r300->screen->caps.is_r500) { 838 OUT_CS_REG_SEQ(R500_RS_IP_0, count); 839 } else { 840 OUT_CS_REG_SEQ(R300_RS_IP_0, count); 841 } 842 OUT_CS_TABLE(rs->ip, count); 843 844 OUT_CS_REG_SEQ(R300_RS_COUNT, 2); 845 OUT_CS(rs->count); 846 OUT_CS(rs->inst_count); 847 848 if (r300->screen->caps.is_r500) { 849 OUT_CS_REG_SEQ(R500_RS_INST_0, count); 850 } else { 851 OUT_CS_REG_SEQ(R300_RS_INST_0, count); 852 } 853 OUT_CS_TABLE(rs->inst, count); 854 END_CS; 855} 856 857void r300_emit_sample_mask(struct r300_context *r300, 858 unsigned size, void *state) 859{ 860 unsigned mask = (*(unsigned*)state) & ((1 << 6)-1); 861 CS_LOCALS(r300); 862 863 BEGIN_CS(size); 864 OUT_CS_REG(R300_SC_SCREENDOOR, 865 mask | (mask << 6) | (mask << 12) | (mask << 18)); 866 END_CS; 867} 868 869void r300_emit_scissor_state(struct r300_context* r300, 870 unsigned size, void* state) 871{ 872 struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state; 873 CS_LOCALS(r300); 874 875 BEGIN_CS(size); 876 OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0, 2); 877 if (r300->screen->caps.is_r500) { 878 OUT_CS((scissor->minx << R300_CLIPRECT_X_SHIFT) | 879 (scissor->miny << R300_CLIPRECT_Y_SHIFT)); 880 OUT_CS(((scissor->maxx - 1) << R300_CLIPRECT_X_SHIFT) | 881 ((scissor->maxy - 1) << R300_CLIPRECT_Y_SHIFT)); 882 } else { 883 OUT_CS(((scissor->minx + 1440) << R300_CLIPRECT_X_SHIFT) | 884 ((scissor->miny + 1440) << R300_CLIPRECT_Y_SHIFT)); 885 OUT_CS(((scissor->maxx + 1440-1) << R300_CLIPRECT_X_SHIFT) | 886 ((scissor->maxy + 1440-1) << R300_CLIPRECT_Y_SHIFT)); 887 } 888 END_CS; 889} 890 891void r300_emit_textures_state(struct r300_context *r300, 892 unsigned size, void *state) 893{ 894 struct r300_textures_state *allstate = (struct r300_textures_state*)state; 895 struct r300_texture_sampler_state *texstate; 896 struct r300_resource *tex; 897 unsigned i; 898 boolean has_us_format = r300->screen->caps.has_us_format; 899 CS_LOCALS(r300); 900 901 BEGIN_CS(size); 902 OUT_CS_REG(R300_TX_ENABLE, allstate->tx_enable); 903 904 for (i = 0; i < allstate->count; i++) { 905 if ((1 << i) & allstate->tx_enable) { 906 texstate = &allstate->regs[i]; 907 tex = r300_resource(allstate->sampler_views[i]->base.texture); 908 909 OUT_CS_REG(R300_TX_FILTER0_0 + (i * 4), texstate->filter0); 910 OUT_CS_REG(R300_TX_FILTER1_0 + (i * 4), texstate->filter1); 911 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (i * 4), 912 texstate->border_color); 913 914 OUT_CS_REG(R300_TX_FORMAT0_0 + (i * 4), texstate->format.format0); 915 OUT_CS_REG(R300_TX_FORMAT1_0 + (i * 4), texstate->format.format1); 916 OUT_CS_REG(R300_TX_FORMAT2_0 + (i * 4), texstate->format.format2); 917 918 OUT_CS_REG(R300_TX_OFFSET_0 + (i * 4), texstate->format.tile_config); 919 OUT_CS_RELOC(tex); 920 921 if (has_us_format) { 922 OUT_CS_REG(R500_US_FORMAT0_0 + (i * 4), 923 texstate->format.us_format0); 924 } 925 } 926 } 927 END_CS; 928} 929 930void r300_emit_vertex_arrays(struct r300_context* r300, int offset, 931 boolean indexed, int instance_id) 932{ 933 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer; 934 struct pipe_vertex_element *velem = r300->velems->velem; 935 struct r300_resource *buf; 936 int i; 937 unsigned vertex_array_count = r300->velems->count; 938 unsigned packet_size = (vertex_array_count * 3 + 1) / 2; 939 struct pipe_vertex_buffer *vb1, *vb2; 940 unsigned *hw_format_size = r300->velems->format_size; 941 unsigned size1, size2, offset1, offset2, stride1, stride2; 942 CS_LOCALS(r300); 943 944 BEGIN_CS(2 + packet_size + vertex_array_count * 2); 945 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size); 946 OUT_CS(vertex_array_count | (!indexed ? R300_VC_FORCE_PREFETCH : 0)); 947 948 if (instance_id == -1) { 949 /* Non-instanced arrays. This ignores instance_divisor and instance_id. */ 950 for (i = 0; i < vertex_array_count - 1; i += 2) { 951 vb1 = &vbuf[velem[i].vertex_buffer_index]; 952 vb2 = &vbuf[velem[i+1].vertex_buffer_index]; 953 size1 = hw_format_size[i]; 954 size2 = hw_format_size[i+1]; 955 956 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) | 957 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride)); 958 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride); 959 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride); 960 } 961 962 if (vertex_array_count & 1) { 963 vb1 = &vbuf[velem[i].vertex_buffer_index]; 964 size1 = hw_format_size[i]; 965 966 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride)); 967 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride); 968 } 969 970 for (i = 0; i < vertex_array_count; i++) { 971 buf = r300_resource(vbuf[velem[i].vertex_buffer_index].buffer.resource); 972 OUT_CS_RELOC(buf); 973 } 974 } else { 975 /* Instanced arrays. */ 976 for (i = 0; i < vertex_array_count - 1; i += 2) { 977 vb1 = &vbuf[velem[i].vertex_buffer_index]; 978 vb2 = &vbuf[velem[i+1].vertex_buffer_index]; 979 size1 = hw_format_size[i]; 980 size2 = hw_format_size[i+1]; 981 982 if (velem[i].instance_divisor) { 983 stride1 = 0; 984 offset1 = vb1->buffer_offset + velem[i].src_offset + 985 (instance_id / velem[i].instance_divisor) * vb1->stride; 986 } else { 987 stride1 = vb1->stride; 988 offset1 = vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride; 989 } 990 if (velem[i+1].instance_divisor) { 991 stride2 = 0; 992 offset2 = vb2->buffer_offset + velem[i+1].src_offset + 993 (instance_id / velem[i+1].instance_divisor) * vb2->stride; 994 } else { 995 stride2 = vb2->stride; 996 offset2 = vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride; 997 } 998 999 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(stride1) | 1000 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(stride2)); 1001 OUT_CS(offset1); 1002 OUT_CS(offset2); 1003 } 1004 1005 if (vertex_array_count & 1) { 1006 vb1 = &vbuf[velem[i].vertex_buffer_index]; 1007 size1 = hw_format_size[i]; 1008 1009 if (velem[i].instance_divisor) { 1010 stride1 = 0; 1011 offset1 = vb1->buffer_offset + velem[i].src_offset + 1012 (instance_id / velem[i].instance_divisor) * vb1->stride; 1013 } else { 1014 stride1 = vb1->stride; 1015 offset1 = vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride; 1016 } 1017 1018 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(stride1)); 1019 OUT_CS(offset1); 1020 } 1021 1022 for (i = 0; i < vertex_array_count; i++) { 1023 buf = r300_resource(vbuf[velem[i].vertex_buffer_index].buffer.resource); 1024 OUT_CS_RELOC(buf); 1025 } 1026 } 1027 END_CS; 1028} 1029 1030void r300_emit_vertex_arrays_swtcl(struct r300_context *r300, boolean indexed) 1031{ 1032 CS_LOCALS(r300); 1033 1034 DBG(r300, DBG_SWTCL, "r300: Preparing vertex buffer %p for render, " 1035 "vertex size %d\n", r300->vbo, 1036 r300->vertex_info.size); 1037 /* Set the pointer to our vertex buffer. The emitted values are this: 1038 * PACKET3 [3D_LOAD_VBPNTR] 1039 * COUNT [1] 1040 * FORMAT [size | stride << 8] 1041 * OFFSET [offset into BO] 1042 * VBPNTR [relocated BO] 1043 */ 1044 BEGIN_CS(7); 1045 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3); 1046 OUT_CS(1 | (!indexed ? R300_VC_FORCE_PREFETCH : 0)); 1047 OUT_CS(r300->vertex_info.size | 1048 (r300->vertex_info.size << 8)); 1049 OUT_CS(r300->draw_vbo_offset); 1050 OUT_CS(0); 1051 1052 assert(r300->vbo); 1053 OUT_CS(0xc0001000); /* PKT3_NOP */ 1054 OUT_CS(r300->rws->cs_lookup_buffer(&r300->cs, r300->vbo) * 4); 1055 END_CS; 1056} 1057 1058void r300_emit_vertex_stream_state(struct r300_context* r300, 1059 unsigned size, void* state) 1060{ 1061 struct r300_vertex_stream_state *streams = 1062 (struct r300_vertex_stream_state*)state; 1063 unsigned i; 1064 CS_LOCALS(r300); 1065 1066 if (DBG_ON(r300, DBG_PSC)) { 1067 fprintf(stderr, "r300: PSC emit:\n"); 1068 1069 for (i = 0; i < streams->count; i++) { 1070 fprintf(stderr, " : prog_stream_cntl%d: 0x%08x\n", i, 1071 streams->vap_prog_stream_cntl[i]); 1072 } 1073 1074 for (i = 0; i < streams->count; i++) { 1075 fprintf(stderr, " : prog_stream_cntl_ext%d: 0x%08x\n", i, 1076 streams->vap_prog_stream_cntl_ext[i]); 1077 } 1078 } 1079 1080 BEGIN_CS(size); 1081 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, streams->count); 1082 OUT_CS_TABLE(streams->vap_prog_stream_cntl, streams->count); 1083 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, streams->count); 1084 OUT_CS_TABLE(streams->vap_prog_stream_cntl_ext, streams->count); 1085 END_CS; 1086} 1087 1088void r300_emit_pvs_flush(struct r300_context* r300, unsigned size, void* state) 1089{ 1090 CS_LOCALS(r300); 1091 1092 BEGIN_CS(size); 1093 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0); 1094 END_CS; 1095} 1096 1097void r300_emit_vap_invariant_state(struct r300_context *r300, 1098 unsigned size, void *state) 1099{ 1100 CS_LOCALS(r300); 1101 WRITE_CS_TABLE(state, size); 1102} 1103 1104void r300_emit_vs_state(struct r300_context* r300, unsigned size, void* state) 1105{ 1106 struct r300_vertex_shader_code* vs = ((struct r300_vertex_shader*)state)->shader; 1107 struct r300_vertex_program_code* code = &vs->code; 1108 struct r300_screen* r300screen = r300->screen; 1109 unsigned instruction_count = code->length / 4; 1110 1111 unsigned vtx_mem_size = r300screen->caps.is_r500 ? 128 : 72; 1112 unsigned input_count = MAX2(util_bitcount(code->InputsRead), 1); 1113 unsigned output_count = MAX2(util_bitcount(code->OutputsWritten), 1); 1114 unsigned temp_count = MAX2(code->num_temporaries, 1); 1115 1116 unsigned pvs_num_slots = MIN3(vtx_mem_size / input_count, 1117 vtx_mem_size / output_count, 10); 1118 unsigned pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 5); 1119 1120 CS_LOCALS(r300); 1121 1122 BEGIN_CS(size); 1123 1124 /* R300_VAP_PVS_CODE_CNTL_0 1125 * R300_VAP_PVS_CONST_CNTL 1126 * R300_VAP_PVS_CODE_CNTL_1 1127 * See the r5xx docs for instructions on how to use these. */ 1128 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0, R300_PVS_FIRST_INST(0) | 1129 R300_PVS_XYZW_VALID_INST(code->last_pos_write) | 1130 R300_PVS_LAST_INST(instruction_count - 1)); 1131 OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1, code->last_input_read); 1132 1133 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0); 1134 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length); 1135 OUT_CS_TABLE(code->body.d, code->length); 1136 1137 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) | 1138 R300_PVS_NUM_CNTLRS(pvs_num_controllers) | 1139 R300_PVS_NUM_FPUS(r300screen->caps.num_vert_fpus) | 1140 R300_PVS_VF_MAX_VTX_NUM(12) | 1141 (r300->clip_halfz ? R300_DX_CLIP_SPACE_DEF : 0) | 1142 (r300screen->caps.is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0)); 1143 1144 /* Emit flow control instructions. Even if there are no fc instructions, 1145 * we still need to write the registers to make sure they are cleared. */ 1146 OUT_CS_REG(R300_VAP_PVS_FLOW_CNTL_OPC, code->fc_ops); 1147 if (r300screen->caps.is_r500) { 1148 OUT_CS_REG_SEQ(R500_VAP_PVS_FLOW_CNTL_ADDRS_LW_0, R300_VS_MAX_FC_OPS * 2); 1149 OUT_CS_TABLE(code->fc_op_addrs.r500, R300_VS_MAX_FC_OPS * 2); 1150 } else { 1151 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_ADDRS_0, R300_VS_MAX_FC_OPS); 1152 OUT_CS_TABLE(code->fc_op_addrs.r300, R300_VS_MAX_FC_OPS); 1153 } 1154 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_LOOP_INDEX_0, R300_VS_MAX_FC_OPS); 1155 OUT_CS_TABLE(code->fc_loop_index, R300_VS_MAX_FC_OPS); 1156 1157 END_CS; 1158} 1159 1160void r300_emit_vs_constants(struct r300_context* r300, 1161 unsigned size, void *state) 1162{ 1163 unsigned count = r300_vs(r300)->shader->externals_count; 1164 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state; 1165 struct r300_vertex_shader_code *vs = r300_vs(r300)->shader; 1166 unsigned i; 1167 int imm_first = vs->externals_count; 1168 int imm_end = vs->code.constants.Count; 1169 int imm_count = vs->immediates_count; 1170 CS_LOCALS(r300); 1171 1172 BEGIN_CS(size); 1173 OUT_CS_REG(R300_VAP_PVS_CONST_CNTL, 1174 R300_PVS_CONST_BASE_OFFSET(buf->buffer_base) | 1175 R300_PVS_MAX_CONST_ADDR(MAX2(imm_end - 1, 0))); 1176 if (vs->externals_count) { 1177 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 1178 (r300->screen->caps.is_r500 ? 1179 R500_PVS_CONST_START : R300_PVS_CONST_START) + buf->buffer_base); 1180 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, count * 4); 1181 if (buf->remap_table){ 1182 for (i = 0; i < count; i++) { 1183 uint32_t *data = &buf->ptr[buf->remap_table[i]*4]; 1184 OUT_CS_TABLE(data, 4); 1185 } 1186 } else { 1187 OUT_CS_TABLE(buf->ptr, count * 4); 1188 } 1189 } 1190 1191 /* Emit immediates. */ 1192 if (imm_count) { 1193 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 1194 (r300->screen->caps.is_r500 ? 1195 R500_PVS_CONST_START : R300_PVS_CONST_START) + 1196 buf->buffer_base + imm_first); 1197 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, imm_count * 4); 1198 for (i = imm_first; i < imm_end; i++) { 1199 const float *data = vs->code.constants.Constants[i].u.Immediate; 1200 OUT_CS_TABLE(data, 4); 1201 } 1202 } 1203 END_CS; 1204} 1205 1206void r300_emit_viewport_state(struct r300_context* r300, 1207 unsigned size, void* state) 1208{ 1209 struct r300_viewport_state* viewport = (struct r300_viewport_state*)state; 1210 CS_LOCALS(r300); 1211 1212 BEGIN_CS(size); 1213 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6); 1214 OUT_CS_TABLE(&viewport->xscale, 6); 1215 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control); 1216 END_CS; 1217} 1218 1219void r300_emit_hiz_clear(struct r300_context *r300, unsigned size, void *state) 1220{ 1221 struct pipe_framebuffer_state *fb = 1222 (struct pipe_framebuffer_state*)r300->fb_state.state; 1223 struct r300_resource* tex; 1224 CS_LOCALS(r300); 1225 1226 tex = r300_resource(fb->zsbuf->texture); 1227 1228 BEGIN_CS(size); 1229 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_HIZ, 2); 1230 OUT_CS(0); 1231 OUT_CS(tex->tex.hiz_dwords[fb->zsbuf->u.tex.level]); 1232 OUT_CS(r300->hiz_clear_value); 1233 END_CS; 1234 1235 /* Mark the current zbuffer's hiz ram as in use. */ 1236 r300->hiz_in_use = TRUE; 1237 r300->hiz_func = HIZ_FUNC_NONE; 1238 r300_mark_atom_dirty(r300, &r300->hyperz_state); 1239} 1240 1241void r300_emit_zmask_clear(struct r300_context *r300, unsigned size, void *state) 1242{ 1243 struct pipe_framebuffer_state *fb = 1244 (struct pipe_framebuffer_state*)r300->fb_state.state; 1245 struct r300_resource *tex; 1246 CS_LOCALS(r300); 1247 1248 tex = r300_resource(fb->zsbuf->texture); 1249 1250 BEGIN_CS(size); 1251 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_ZMASK, 2); 1252 OUT_CS(0); 1253 OUT_CS(tex->tex.zmask_dwords[fb->zsbuf->u.tex.level]); 1254 OUT_CS(0); 1255 END_CS; 1256 1257 /* Mark the current zbuffer's zmask as in use. */ 1258 r300->zmask_in_use = TRUE; 1259 r300_mark_atom_dirty(r300, &r300->hyperz_state); 1260} 1261 1262void r300_emit_cmask_clear(struct r300_context *r300, unsigned size, void *state) 1263{ 1264 struct pipe_framebuffer_state *fb = 1265 (struct pipe_framebuffer_state*)r300->fb_state.state; 1266 struct r300_resource *tex; 1267 CS_LOCALS(r300); 1268 1269 tex = r300_resource(fb->cbufs[0]->texture); 1270 1271 BEGIN_CS(size); 1272 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_CMASK, 2); 1273 OUT_CS(0); 1274 OUT_CS(tex->tex.cmask_dwords); 1275 OUT_CS(0); 1276 END_CS; 1277 1278 /* Mark the current zbuffer's zmask as in use. */ 1279 r300->cmask_in_use = TRUE; 1280 r300_mark_fb_state_dirty(r300, R300_CHANGED_CMASK_ENABLE); 1281} 1282 1283void r300_emit_ztop_state(struct r300_context* r300, 1284 unsigned size, void* state) 1285{ 1286 struct r300_ztop_state* ztop = (struct r300_ztop_state*)state; 1287 CS_LOCALS(r300); 1288 1289 BEGIN_CS(size); 1290 OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top); 1291 END_CS; 1292} 1293 1294void r300_emit_texture_cache_inval(struct r300_context* r300, unsigned size, void* state) 1295{ 1296 CS_LOCALS(r300); 1297 1298 BEGIN_CS(size); 1299 OUT_CS_REG(R300_TX_INVALTAGS, 0); 1300 END_CS; 1301} 1302 1303boolean r300_emit_buffer_validate(struct r300_context *r300, 1304 boolean do_validate_vertex_buffers, 1305 struct pipe_resource *index_buffer) 1306{ 1307 struct pipe_framebuffer_state *fb = 1308 (struct pipe_framebuffer_state*)r300->fb_state.state; 1309 struct r300_aa_state *aa = (struct r300_aa_state*)r300->aa_state.state; 1310 struct r300_textures_state *texstate = 1311 (struct r300_textures_state*)r300->textures_state.state; 1312 struct r300_resource *tex; 1313 unsigned i; 1314 boolean flushed = FALSE; 1315 1316validate: 1317 if (r300->fb_state.dirty) { 1318 /* Color buffers... */ 1319 for (i = 0; i < fb->nr_cbufs; i++) { 1320 if (!fb->cbufs[i]) 1321 continue; 1322 tex = r300_resource(fb->cbufs[i]->texture); 1323 assert(tex && tex->buf && "cbuf is marked, but NULL!"); 1324 r300->rws->cs_add_buffer(&r300->cs, tex->buf, 1325 RADEON_USAGE_READWRITE | RADEON_USAGE_SYNCHRONIZED | 1326 (tex->b.nr_samples > 1 ? 1327 RADEON_PRIO_COLOR_BUFFER_MSAA : 1328 RADEON_PRIO_COLOR_BUFFER), 1329 r300_surface(fb->cbufs[i])->domain); 1330 } 1331 /* ...depth buffer... */ 1332 if (fb->zsbuf) { 1333 tex = r300_resource(fb->zsbuf->texture); 1334 assert(tex && tex->buf && "zsbuf is marked, but NULL!"); 1335 r300->rws->cs_add_buffer(&r300->cs, tex->buf, 1336 RADEON_USAGE_READWRITE | RADEON_USAGE_SYNCHRONIZED | 1337 (tex->b.nr_samples > 1 ? 1338 RADEON_PRIO_DEPTH_BUFFER_MSAA : 1339 RADEON_PRIO_DEPTH_BUFFER), 1340 r300_surface(fb->zsbuf)->domain); 1341 } 1342 } 1343 /* The AA resolve buffer. */ 1344 if (r300->aa_state.dirty) { 1345 if (aa->dest) { 1346 r300->rws->cs_add_buffer(&r300->cs, aa->dest->buf, 1347 RADEON_USAGE_WRITE | RADEON_USAGE_SYNCHRONIZED | 1348 RADEON_PRIO_COLOR_BUFFER, 1349 aa->dest->domain); 1350 } 1351 } 1352 if (r300->textures_state.dirty) { 1353 /* ...textures... */ 1354 for (i = 0; i < texstate->count; i++) { 1355 if (!(texstate->tx_enable & (1U << i))) { 1356 continue; 1357 } 1358 1359 tex = r300_resource(texstate->sampler_views[i]->base.texture); 1360 r300->rws->cs_add_buffer(&r300->cs, tex->buf, 1361 RADEON_USAGE_READ | RADEON_USAGE_SYNCHRONIZED | 1362 RADEON_PRIO_SAMPLER_TEXTURE, 1363 tex->domain); 1364 } 1365 } 1366 /* ...occlusion query buffer... */ 1367 if (r300->query_current) 1368 r300->rws->cs_add_buffer(&r300->cs, r300->query_current->buf, 1369 RADEON_USAGE_WRITE | RADEON_USAGE_SYNCHRONIZED | 1370 RADEON_PRIO_QUERY, 1371 RADEON_DOMAIN_GTT); 1372 /* ...vertex buffer for SWTCL path... */ 1373 if (r300->vbo) 1374 r300->rws->cs_add_buffer(&r300->cs, r300->vbo, 1375 RADEON_USAGE_READ | RADEON_USAGE_SYNCHRONIZED | 1376 RADEON_PRIO_VERTEX_BUFFER, 1377 RADEON_DOMAIN_GTT); 1378 /* ...vertex buffers for HWTCL path... */ 1379 if (do_validate_vertex_buffers && r300->vertex_arrays_dirty) { 1380 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer; 1381 struct pipe_vertex_buffer *last = r300->vertex_buffer + 1382 r300->nr_vertex_buffers; 1383 struct pipe_resource *buf; 1384 1385 for (; vbuf != last; vbuf++) { 1386 buf = vbuf->buffer.resource; 1387 if (!buf) 1388 continue; 1389 1390 r300->rws->cs_add_buffer(&r300->cs, r300_resource(buf)->buf, 1391 RADEON_USAGE_READ | RADEON_USAGE_SYNCHRONIZED | 1392 RADEON_PRIO_SAMPLER_BUFFER, 1393 r300_resource(buf)->domain); 1394 } 1395 } 1396 /* ...and index buffer for HWTCL path. */ 1397 if (index_buffer) 1398 r300->rws->cs_add_buffer(&r300->cs, r300_resource(index_buffer)->buf, 1399 RADEON_USAGE_READ | RADEON_USAGE_SYNCHRONIZED | 1400 RADEON_PRIO_INDEX_BUFFER, 1401 r300_resource(index_buffer)->domain); 1402 1403 /* Now do the validation (flush is called inside cs_validate on failure). */ 1404 if (!r300->rws->cs_validate(&r300->cs)) { 1405 /* Ooops, an infinite loop, give up. */ 1406 if (flushed) 1407 return FALSE; 1408 1409 flushed = TRUE; 1410 goto validate; 1411 } 1412 1413 return TRUE; 1414} 1415 1416unsigned r300_get_num_dirty_dwords(struct r300_context *r300) 1417{ 1418 struct r300_atom* atom; 1419 unsigned dwords = 0; 1420 1421 foreach_dirty_atom(r300, atom) { 1422 if (atom->dirty) { 1423 dwords += atom->size; 1424 } 1425 } 1426 1427 /* let's reserve some more, just in case */ 1428 dwords += 32; 1429 1430 return dwords; 1431} 1432 1433unsigned r300_get_num_cs_end_dwords(struct r300_context *r300) 1434{ 1435 unsigned dwords = 0; 1436 1437 /* Emitted in flush. */ 1438 dwords += 26; /* emit_query_end */ 1439 dwords += r300->hyperz_state.size + 2; /* emit_hyperz_end + zcache flush */ 1440 if (r300->screen->caps.is_r500) 1441 dwords += 2; /* emit_index_bias */ 1442 dwords += 3; /* MSPOS */ 1443 1444 return dwords; 1445} 1446 1447/* Emit all dirty state. */ 1448void r300_emit_dirty_state(struct r300_context* r300) 1449{ 1450 struct r300_atom *atom; 1451 1452 foreach_dirty_atom(r300, atom) { 1453 if (atom->dirty) { 1454 atom->emit(r300, atom->size, atom->state); 1455 atom->dirty = FALSE; 1456 } 1457 } 1458 1459 r300->first_dirty = NULL; 1460 r300->last_dirty = NULL; 1461 r300->dirty_hw++; 1462} 1463