1/*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 *
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 */
27
28#include "r500_fragprog.h"
29
30#include <stdio.h>
31
32#include "radeon_compiler_util.h"
33#include "radeon_list.h"
34#include "radeon_variable.h"
35#include "r300_reg.h"
36
37#include "util/compiler.h"
38
39/**
40 * Rewrite IF instructions to use the ALU result special register.
41 */
42int r500_transform_IF(
43	struct radeon_compiler * c,
44	struct rc_instruction * inst_if,
45	void *data)
46{
47	if (inst_if->U.I.Opcode != RC_OPCODE_IF)
48		return 0;
49
50	struct rc_variable * writer;
51	struct rc_list * writer_list, * list_ptr;
52	struct rc_list * var_list = rc_get_variables(c);
53	unsigned int generic_if = 0;
54	unsigned int alu_chan;
55
56	writer_list = rc_variable_list_get_writers(
57			var_list, inst_if->Type, &inst_if->U.I.SrcReg[0]);
58	if (!writer_list) {
59		generic_if = 1;
60	} else {
61
62		/* Make sure it is safe for the writers to write to
63		 * ALU Result */
64		for (list_ptr = writer_list; list_ptr;
65						list_ptr = list_ptr->Next) {
66			struct rc_instruction * inst;
67			writer = list_ptr->Item;
68			/* We are going to modify the destination register
69			 * of writer, so if it has a reader other than
70			 * inst_if (aka ReaderCount > 1) we must fall back to
71			 * our generic IF.
72			 * If the writer has a lower IP than inst_if, this
73			 * means that inst_if is above the writer in a loop.
74			 * I'm not sure why this would ever happen, but
75			 * if it does we want to make sure we fall back
76			 * to our generic IF. */
77			if (writer->ReaderCount > 1 || writer->Inst->IP < inst_if->IP) {
78				generic_if = 1;
79				break;
80			}
81
82			/* The ALU Result is not preserved across IF
83			 * instructions, so if there is another IF
84			 * instruction between writer and inst_if, then
85			 * we need to fall back to generic IF. */
86			for (inst = writer->Inst; inst != inst_if; inst = inst->Next) {
87				const struct rc_opcode_info * info =
88					rc_get_opcode_info(inst->U.I.Opcode);
89				if (info->IsFlowControl) {
90					generic_if = 1;
91					break;
92				}
93			}
94			if (generic_if) {
95				break;
96			}
97		}
98	}
99
100	if (GET_SWZ(inst_if->U.I.SrcReg[0].Swizzle, 0) == RC_SWIZZLE_X) {
101		alu_chan = RC_ALURESULT_X;
102	} else {
103		alu_chan = RC_ALURESULT_W;
104	}
105	if (generic_if) {
106		struct rc_instruction * inst_mov =
107				rc_insert_new_instruction(c, inst_if->Prev);
108
109		inst_mov->U.I.Opcode = RC_OPCODE_MOV;
110		inst_mov->U.I.DstReg.WriteMask = 0;
111		inst_mov->U.I.DstReg.File = RC_FILE_NONE;
112		inst_mov->U.I.ALUResultCompare = RC_COMPARE_FUNC_NOTEQUAL;
113		inst_mov->U.I.WriteALUResult = alu_chan;
114		inst_mov->U.I.SrcReg[0] = inst_if->U.I.SrcReg[0];
115		if (alu_chan == RC_ALURESULT_X) {
116			inst_mov->U.I.SrcReg[0].Swizzle = combine_swizzles4(
117					inst_mov->U.I.SrcReg[0].Swizzle,
118					RC_SWIZZLE_X, RC_SWIZZLE_UNUSED,
119					RC_SWIZZLE_UNUSED, RC_SWIZZLE_UNUSED);
120		} else {
121			inst_mov->U.I.SrcReg[0].Swizzle = combine_swizzles4(
122					inst_mov->U.I.SrcReg[0].Swizzle,
123					RC_SWIZZLE_UNUSED, RC_SWIZZLE_UNUSED,
124					RC_SWIZZLE_UNUSED, RC_SWIZZLE_Z);
125		}
126	} else {
127		rc_compare_func compare_func = RC_COMPARE_FUNC_NEVER;
128		unsigned int reverse_srcs = 0;
129		unsigned int preserve_opcode = 0;
130		for (list_ptr = writer_list; list_ptr;
131						list_ptr = list_ptr->Next) {
132			writer = list_ptr->Item;
133			switch(writer->Inst->U.I.Opcode) {
134			case RC_OPCODE_SEQ:
135				compare_func = RC_COMPARE_FUNC_EQUAL;
136				break;
137			case RC_OPCODE_SNE:
138				compare_func = RC_COMPARE_FUNC_NOTEQUAL;
139				break;
140			case RC_OPCODE_SLE:
141				reverse_srcs = 1;
142				FALLTHROUGH;
143			case RC_OPCODE_SGE:
144				compare_func = RC_COMPARE_FUNC_GEQUAL;
145				break;
146			case RC_OPCODE_SGT:
147				reverse_srcs = 1;
148				FALLTHROUGH;
149			case RC_OPCODE_SLT:
150				compare_func = RC_COMPARE_FUNC_LESS;
151				break;
152			default:
153				compare_func = RC_COMPARE_FUNC_NOTEQUAL;
154				preserve_opcode = 1;
155				break;
156			}
157			if (!preserve_opcode) {
158				writer->Inst->U.I.Opcode = RC_OPCODE_SUB;
159			}
160			writer->Inst->U.I.DstReg.WriteMask = 0;
161			writer->Inst->U.I.DstReg.File = RC_FILE_NONE;
162			writer->Inst->U.I.WriteALUResult = alu_chan;
163			writer->Inst->U.I.ALUResultCompare = compare_func;
164			if (reverse_srcs) {
165				struct rc_src_register temp_src;
166				temp_src = writer->Inst->U.I.SrcReg[0];
167				writer->Inst->U.I.SrcReg[0] =
168					writer->Inst->U.I.SrcReg[1];
169				writer->Inst->U.I.SrcReg[1] = temp_src;
170			}
171		}
172	}
173
174	inst_if->U.I.SrcReg[0].File = RC_FILE_SPECIAL;
175	inst_if->U.I.SrcReg[0].Index = RC_SPECIAL_ALU_RESULT;
176	inst_if->U.I.SrcReg[0].Swizzle = RC_MAKE_SWIZZLE(
177				RC_SWIZZLE_X, RC_SWIZZLE_UNUSED,
178				RC_SWIZZLE_UNUSED, RC_SWIZZLE_UNUSED);
179	inst_if->U.I.SrcReg[0].Negate = 0;
180
181	return 1;
182}
183
184static int r500_swizzle_is_native(rc_opcode opcode, struct rc_src_register reg)
185{
186	unsigned int relevant;
187	int i;
188
189	if (opcode == RC_OPCODE_TEX ||
190	    opcode == RC_OPCODE_TXB ||
191	    opcode == RC_OPCODE_TXP ||
192	    opcode == RC_OPCODE_TXD ||
193	    opcode == RC_OPCODE_TXL ||
194	    opcode == RC_OPCODE_KIL) {
195		if (reg.Abs)
196			return 0;
197
198		if (opcode == RC_OPCODE_KIL && (reg.Swizzle != RC_SWIZZLE_XYZW || reg.Negate != RC_MASK_NONE))
199			return 0;
200
201		for(i = 0; i < 4; ++i) {
202			unsigned int swz = GET_SWZ(reg.Swizzle, i);
203			if (swz == RC_SWIZZLE_UNUSED) {
204				reg.Negate &= ~(1 << i);
205				continue;
206			}
207			if (swz >= 4)
208				return 0;
209		}
210
211		if (reg.Negate)
212			return 0;
213
214		return 1;
215	} else if (opcode == RC_OPCODE_DDX || opcode == RC_OPCODE_DDY) {
216		/* DDX/MDH and DDY/MDV explicitly ignore incoming swizzles;
217		 * if it doesn't fit perfectly into a .xyzw case... */
218		if (reg.Swizzle == RC_SWIZZLE_XYZW && !reg.Abs && !reg.Negate)
219			return 1;
220
221		return 0;
222	} else {
223		/* ALU instructions support almost everything */
224		relevant = 0;
225		for(i = 0; i < 3; ++i) {
226			unsigned int swz = GET_SWZ(reg.Swizzle, i);
227			if (swz != RC_SWIZZLE_UNUSED && swz != RC_SWIZZLE_ZERO)
228				relevant |= 1 << i;
229		}
230		if ((reg.Negate & relevant) && ((reg.Negate & relevant) != relevant))
231			return 0;
232
233		return 1;
234	}
235}
236
237/**
238 * Split source register access.
239 *
240 * The only thing we *cannot* do in an ALU instruction is per-component
241 * negation.
242 */
243static void r500_swizzle_split(struct rc_src_register src, unsigned int usemask,
244		struct rc_swizzle_split * split)
245{
246	unsigned int negatebase[2] = { 0, 0 };
247	int i;
248
249	for(i = 0; i < 4; ++i) {
250		unsigned int swz = GET_SWZ(src.Swizzle, i);
251		if (swz == RC_SWIZZLE_UNUSED || !GET_BIT(usemask, i))
252			continue;
253		negatebase[GET_BIT(src.Negate, i)] |= 1 << i;
254	}
255
256	split->NumPhases = 0;
257
258	for(i = 0; i <= 1; ++i) {
259		if (!negatebase[i])
260			continue;
261
262		split->Phase[split->NumPhases++] = negatebase[i];
263	}
264}
265
266const struct rc_swizzle_caps r500_swizzle_caps = {
267	.IsNative = r500_swizzle_is_native,
268	.Split = r500_swizzle_split
269};
270
271static char *toswiz(int swiz_val) {
272  switch(swiz_val) {
273  case 0: return "R";
274  case 1: return "G";
275  case 2: return "B";
276  case 3: return "A";
277  case 4: return "0";
278  case 5: return "H";
279  case 6: return "1";
280  case 7: return "U";
281  }
282  return NULL;
283}
284
285static char *toop(int op_val)
286{
287  char *str = NULL;
288  switch (op_val) {
289  case 0: str = "MAD"; break;
290  case 1: str = "DP3"; break;
291  case 2: str = "DP4"; break;
292  case 3: str = "D2A"; break;
293  case 4: str = "MIN"; break;
294  case 5: str = "MAX"; break;
295  case 6: str = "Reserved"; break;
296  case 7: str = "CND"; break;
297  case 8: str = "CMP"; break;
298  case 9: str = "FRC"; break;
299  case 10: str = "SOP"; break;
300  case 11: str = "MDH"; break;
301  case 12: str = "MDV"; break;
302  }
303  return str;
304}
305
306static char *to_alpha_op(int op_val)
307{
308  char *str = NULL;
309  switch (op_val) {
310  case 0: str = "MAD"; break;
311  case 1: str = "DP"; break;
312  case 2: str = "MIN"; break;
313  case 3: str = "MAX"; break;
314  case 4: str = "Reserved"; break;
315  case 5: str = "CND"; break;
316  case 6: str = "CMP"; break;
317  case 7: str = "FRC"; break;
318  case 8: str = "EX2"; break;
319  case 9: str = "LN2"; break;
320  case 10: str = "RCP"; break;
321  case 11: str = "RSQ"; break;
322  case 12: str = "SIN"; break;
323  case 13: str = "COS"; break;
324  case 14: str = "MDH"; break;
325  case 15: str = "MDV"; break;
326  }
327  return str;
328}
329
330static char *to_mask(int val)
331{
332  char *str = NULL;
333  switch(val) {
334  case 0: str = "NONE"; break;
335  case 1: str = "R"; break;
336  case 2: str = "G"; break;
337  case 3: str = "RG"; break;
338  case 4: str = "B"; break;
339  case 5: str = "RB"; break;
340  case 6: str = "GB"; break;
341  case 7: str = "RGB"; break;
342  case 8: str = "A"; break;
343  case 9: str = "AR"; break;
344  case 10: str = "AG"; break;
345  case 11: str = "ARG"; break;
346  case 12: str = "AB"; break;
347  case 13: str = "ARB"; break;
348  case 14: str = "AGB"; break;
349  case 15: str = "ARGB"; break;
350  }
351  return str;
352}
353
354static char *to_texop(int val)
355{
356  switch(val) {
357  case 0: return "NOP";
358  case 1: return "LD";
359  case 2: return "TEXKILL";
360  case 3: return "PROJ";
361  case 4: return "LODBIAS";
362  case 5: return "LOD";
363  case 6: return "DXDY";
364  }
365  return NULL;
366}
367
368void r500FragmentProgramDump(struct radeon_compiler *c, void *user)
369{
370  struct r300_fragment_program_compiler *compiler = (struct r300_fragment_program_compiler*)c;
371  struct r500_fragment_program_code *code = &compiler->code->code.r500;
372  int n, i;
373  uint32_t inst;
374  uint32_t inst0;
375  char *str = NULL;
376  fprintf(stderr, "R500 Fragment Program:\n--------\n");
377
378  for (n = 0; n < code->inst_end+1; n++) {
379    inst0 = inst = code->inst[n].inst0;
380    fprintf(stderr,"%d\t0:CMN_INST   0x%08x:", n, inst);
381    switch(inst & 0x3) {
382    case R500_INST_TYPE_ALU: str = "ALU"; break;
383    case R500_INST_TYPE_OUT: str = "OUT"; break;
384    case R500_INST_TYPE_FC: str = "FC"; break;
385    case R500_INST_TYPE_TEX: str = "TEX"; break;
386    }
387    fprintf(stderr,"%s %s %s %s %s ", str,
388	    inst & R500_INST_TEX_SEM_WAIT ? "TEX_WAIT" : "",
389	    inst & R500_INST_LAST ? "LAST" : "",
390	    inst & R500_INST_NOP ? "NOP" : "",
391	    inst & R500_INST_ALU_WAIT ? "ALU WAIT" : "");
392    fprintf(stderr,"wmask: %s omask: %s\n", to_mask((inst >> 11) & 0xf),
393	    to_mask((inst >> 15) & 0xf));
394
395    switch(inst0 & 0x3) {
396    case R500_INST_TYPE_ALU:
397    case R500_INST_TYPE_OUT:
398      fprintf(stderr,"\t1:RGB_ADDR   0x%08x:", code->inst[n].inst1);
399      inst = code->inst[n].inst1;
400
401      fprintf(stderr,"Addr0: %d%c, Addr1: %d%c, Addr2: %d%c, srcp:%d\n",
402	      inst & 0xff, (inst & (1<<8)) ? 'c' : 't',
403	      (inst >> 10) & 0xff, (inst & (1<<18)) ? 'c' : 't',
404	      (inst >> 20) & 0xff, (inst & (1<<28)) ? 'c' : 't',
405	      (inst >> 30));
406
407      fprintf(stderr,"\t2:ALPHA_ADDR 0x%08x:", code->inst[n].inst2);
408      inst = code->inst[n].inst2;
409      fprintf(stderr,"Addr0: %d%c, Addr1: %d%c, Addr2: %d%c, srcp:%d\n",
410	      inst & 0xff, (inst & (1<<8)) ? 'c' : 't',
411	      (inst >> 10) & 0xff, (inst & (1<<18)) ? 'c' : 't',
412	      (inst >> 20) & 0xff, (inst & (1<<28)) ? 'c' : 't',
413	      (inst >> 30));
414      fprintf(stderr,"\t3 RGB_INST:  0x%08x:", code->inst[n].inst3);
415      inst = code->inst[n].inst3;
416      fprintf(stderr,"rgb_A_src:%d %s/%s/%s %d rgb_B_src:%d %s/%s/%s %d targ: %d\n",
417	      (inst) & 0x3, toswiz((inst >> 2) & 0x7), toswiz((inst >> 5) & 0x7), toswiz((inst >> 8) & 0x7),
418	      (inst >> 11) & 0x3,
419	      (inst >> 13) & 0x3, toswiz((inst >> 15) & 0x7), toswiz((inst >> 18) & 0x7), toswiz((inst >> 21) & 0x7),
420	      (inst >> 24) & 0x3, (inst >> 29) & 0x3);
421
422
423      fprintf(stderr,"\t4 ALPHA_INST:0x%08x:", code->inst[n].inst4);
424      inst = code->inst[n].inst4;
425      fprintf(stderr,"%s dest:%d%s alp_A_src:%d %s %d alp_B_src:%d %s %d targ %d w:%d\n", to_alpha_op(inst & 0xf),
426	      (inst >> 4) & 0x7f, inst & (1<<11) ? "(rel)":"",
427	      (inst >> 12) & 0x3, toswiz((inst >> 14) & 0x7), (inst >> 17) & 0x3,
428	      (inst >> 19) & 0x3, toswiz((inst >> 21) & 0x7), (inst >> 24) & 0x3,
429	      (inst >> 29) & 0x3,
430	      (inst >> 31) & 0x1);
431
432      fprintf(stderr,"\t5 RGBA_INST: 0x%08x:", code->inst[n].inst5);
433      inst = code->inst[n].inst5;
434      fprintf(stderr,"%s dest:%d%s rgb_C_src:%d %s/%s/%s %d alp_C_src:%d %s %d\n", toop(inst & 0xf),
435	      (inst >> 4) & 0x7f, inst & (1<<11) ? "(rel)":"",
436	      (inst >> 12) & 0x3, toswiz((inst >> 14) & 0x7), toswiz((inst >> 17) & 0x7), toswiz((inst >> 20) & 0x7),
437	      (inst >> 23) & 0x3,
438	      (inst >> 25) & 0x3, toswiz((inst >> 27) & 0x7), (inst >> 30) & 0x3);
439      break;
440    case R500_INST_TYPE_FC:
441      fprintf(stderr, "\t2:FC_INST    0x%08x:", code->inst[n].inst2);
442      inst = code->inst[n].inst2;
443      /* JUMP_FUNC JUMP_ANY*/
444      fprintf(stderr, "0x%02x %1x ", inst >> 8 & 0xff,
445          (inst & R500_FC_JUMP_ANY) >> 5);
446
447      /* OP */
448      switch(inst & 0x7){
449      case R500_FC_OP_JUMP:
450      	fprintf(stderr, "JUMP");
451        break;
452      case R500_FC_OP_LOOP:
453        fprintf(stderr, "LOOP");
454        break;
455      case R500_FC_OP_ENDLOOP:
456        fprintf(stderr, "ENDLOOP");
457        break;
458      case R500_FC_OP_REP:
459        fprintf(stderr, "REP");
460        break;
461      case R500_FC_OP_ENDREP:
462        fprintf(stderr, "ENDREP");
463        break;
464      case R500_FC_OP_BREAKLOOP:
465        fprintf(stderr, "BREAKLOOP");
466        break;
467      case R500_FC_OP_BREAKREP:
468        fprintf(stderr, "BREAKREP");
469	break;
470      case R500_FC_OP_CONTINUE:
471        fprintf(stderr, "CONTINUE");
472        break;
473      }
474      fprintf(stderr," ");
475      /* A_OP */
476      switch(inst & (0x3 << 6)){
477      case R500_FC_A_OP_NONE:
478        fprintf(stderr, "NONE");
479        break;
480      case R500_FC_A_OP_POP:
481	fprintf(stderr, "POP");
482        break;
483      case R500_FC_A_OP_PUSH:
484        fprintf(stderr, "PUSH");
485        break;
486      }
487      /* B_OP0 B_OP1 */
488      for(i=0; i<2; i++){
489        fprintf(stderr, " ");
490        switch(inst & (0x3 << (24 + (i * 2)))){
491        /* R500_FC_B_OP0_NONE
492	 * R500_FC_B_OP1_NONE */
493	case 0:
494          fprintf(stderr, "NONE");
495          break;
496        case R500_FC_B_OP0_DECR:
497        case R500_FC_B_OP1_DECR:
498          fprintf(stderr, "DECR");
499          break;
500        case R500_FC_B_OP0_INCR:
501        case R500_FC_B_OP1_INCR:
502          fprintf(stderr, "INCR");
503          break;
504        }
505      }
506      /*POP_CNT B_ELSE */
507      fprintf(stderr, " %d %1x", (inst >> 16) & 0x1f, (inst & R500_FC_B_ELSE) >> 4);
508      inst = code->inst[n].inst3;
509      /* JUMP_ADDR */
510      fprintf(stderr, " %d", inst >> 16);
511
512      if(code->inst[n].inst2 & R500_FC_IGNORE_UNCOVERED){
513        fprintf(stderr, " IGN_UNC");
514      }
515      inst = code->inst[n].inst3;
516      fprintf(stderr, "\n\t3:FC_ADDR    0x%08x:", inst);
517      fprintf(stderr, "BOOL: 0x%02x, INT: 0x%02x, JUMP_ADDR: %d, JMP_GLBL: %1x\n",
518      inst & 0x1f, (inst >> 8) & 0x1f, (inst >> 16) & 0x1ff, inst >> 31);
519      break;
520    case R500_INST_TYPE_TEX:
521      inst = code->inst[n].inst1;
522      fprintf(stderr,"\t1:TEX_INST:  0x%08x: id: %d op:%s, %s, %s %s\n", inst, (inst >> 16) & 0xf,
523	      to_texop((inst >> 22) & 0x7), (inst & (1<<25)) ? "ACQ" : "",
524	      (inst & (1<<26)) ? "IGNUNC" : "", (inst & (1<<27)) ? "UNSCALED" : "SCALED");
525      inst = code->inst[n].inst2;
526      fprintf(stderr,"\t2:TEX_ADDR:  0x%08x: src: %d%s %s/%s/%s/%s dst: %d%s %s/%s/%s/%s\n", inst,
527	      inst & 127, inst & (1<<7) ? "(rel)" : "",
528	      toswiz((inst >> 8) & 0x3), toswiz((inst >> 10) & 0x3),
529	      toswiz((inst >> 12) & 0x3), toswiz((inst >> 14) & 0x3),
530	      (inst >> 16) & 127, inst & (1<<23) ? "(rel)" : "",
531	      toswiz((inst >> 24) & 0x3), toswiz((inst >> 26) & 0x3),
532	      toswiz((inst >> 28) & 0x3), toswiz((inst >> 30) & 0x3));
533
534      fprintf(stderr,"\t3:TEX_DXDY:  0x%08x\n", code->inst[n].inst3);
535      break;
536    }
537    fprintf(stderr,"\n");
538  }
539
540}
541