1/* 2 * Copyright 2010 Christoph Bumiller 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23#include "pipe/p_defines.h" 24#include "util/u_framebuffer.h" 25#include "util/u_helpers.h" 26#include "util/u_inlines.h" 27#include "util/u_transfer.h" 28 29#include "tgsi/tgsi_parse.h" 30#include "compiler/nir/nir.h" 31#include "compiler/nir/nir_serialize.h" 32 33#include "nvc0/nvc0_stateobj.h" 34#include "nvc0/nvc0_context.h" 35#include "nvc0/nvc0_query_hw.h" 36 37#include "nvc0/nvc0_3d.xml.h" 38 39#include "nouveau_gldefs.h" 40 41static inline uint32_t 42nvc0_colormask(unsigned mask) 43{ 44 uint32_t ret = 0; 45 46 if (mask & PIPE_MASK_R) 47 ret |= 0x0001; 48 if (mask & PIPE_MASK_G) 49 ret |= 0x0010; 50 if (mask & PIPE_MASK_B) 51 ret |= 0x0100; 52 if (mask & PIPE_MASK_A) 53 ret |= 0x1000; 54 55 return ret; 56} 57 58#define NVC0_BLEND_FACTOR_CASE(a, b) \ 59 case PIPE_BLENDFACTOR_##a: return NV50_BLEND_FACTOR_##b 60 61static inline uint32_t 62nvc0_blend_fac(unsigned factor) 63{ 64 switch (factor) { 65 NVC0_BLEND_FACTOR_CASE(ONE, ONE); 66 NVC0_BLEND_FACTOR_CASE(SRC_COLOR, SRC_COLOR); 67 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA, SRC_ALPHA); 68 NVC0_BLEND_FACTOR_CASE(DST_ALPHA, DST_ALPHA); 69 NVC0_BLEND_FACTOR_CASE(DST_COLOR, DST_COLOR); 70 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA_SATURATE, SRC_ALPHA_SATURATE); 71 NVC0_BLEND_FACTOR_CASE(CONST_COLOR, CONSTANT_COLOR); 72 NVC0_BLEND_FACTOR_CASE(CONST_ALPHA, CONSTANT_ALPHA); 73 NVC0_BLEND_FACTOR_CASE(SRC1_COLOR, SRC1_COLOR); 74 NVC0_BLEND_FACTOR_CASE(SRC1_ALPHA, SRC1_ALPHA); 75 NVC0_BLEND_FACTOR_CASE(ZERO, ZERO); 76 NVC0_BLEND_FACTOR_CASE(INV_SRC_COLOR, ONE_MINUS_SRC_COLOR); 77 NVC0_BLEND_FACTOR_CASE(INV_SRC_ALPHA, ONE_MINUS_SRC_ALPHA); 78 NVC0_BLEND_FACTOR_CASE(INV_DST_ALPHA, ONE_MINUS_DST_ALPHA); 79 NVC0_BLEND_FACTOR_CASE(INV_DST_COLOR, ONE_MINUS_DST_COLOR); 80 NVC0_BLEND_FACTOR_CASE(INV_CONST_COLOR, ONE_MINUS_CONSTANT_COLOR); 81 NVC0_BLEND_FACTOR_CASE(INV_CONST_ALPHA, ONE_MINUS_CONSTANT_ALPHA); 82 NVC0_BLEND_FACTOR_CASE(INV_SRC1_COLOR, ONE_MINUS_SRC1_COLOR); 83 NVC0_BLEND_FACTOR_CASE(INV_SRC1_ALPHA, ONE_MINUS_SRC1_ALPHA); 84 default: 85 return NV50_BLEND_FACTOR_ZERO; 86 } 87} 88 89static void * 90nvc0_blend_state_create(struct pipe_context *pipe, 91 const struct pipe_blend_state *cso) 92{ 93 struct nvc0_blend_stateobj *so = CALLOC_STRUCT(nvc0_blend_stateobj); 94 int i; 95 int r; /* reference */ 96 uint32_t ms; 97 uint8_t blend_en = 0; 98 bool indep_masks = false; 99 bool indep_funcs = false; 100 101 so->pipe = *cso; 102 103 /* check which states actually have differing values */ 104 if (cso->independent_blend_enable) { 105 for (r = 0; r < 8 && !cso->rt[r].blend_enable; ++r); 106 blend_en |= 1 << r; 107 for (i = r + 1; i < 8; ++i) { 108 if (!cso->rt[i].blend_enable) 109 continue; 110 blend_en |= 1 << i; 111 if (cso->rt[i].rgb_func != cso->rt[r].rgb_func || 112 cso->rt[i].rgb_src_factor != cso->rt[r].rgb_src_factor || 113 cso->rt[i].rgb_dst_factor != cso->rt[r].rgb_dst_factor || 114 cso->rt[i].alpha_func != cso->rt[r].alpha_func || 115 cso->rt[i].alpha_src_factor != cso->rt[r].alpha_src_factor || 116 cso->rt[i].alpha_dst_factor != cso->rt[r].alpha_dst_factor) { 117 indep_funcs = true; 118 break; 119 } 120 } 121 for (; i < 8; ++i) 122 blend_en |= (cso->rt[i].blend_enable ? 1 : 0) << i; 123 124 for (i = 1; i < 8; ++i) { 125 if (cso->rt[i].colormask != cso->rt[0].colormask) { 126 indep_masks = true; 127 break; 128 } 129 } 130 } else { 131 r = 0; 132 if (cso->rt[0].blend_enable) 133 blend_en = 0xff; 134 } 135 136 if (cso->logicop_enable) { 137 SB_BEGIN_3D(so, LOGIC_OP_ENABLE, 2); 138 SB_DATA (so, 1); 139 SB_DATA (so, nvgl_logicop_func(cso->logicop_func)); 140 141 SB_IMMED_3D(so, MACRO_BLEND_ENABLES, 0); 142 } else { 143 SB_IMMED_3D(so, LOGIC_OP_ENABLE, 0); 144 145 SB_IMMED_3D(so, BLEND_INDEPENDENT, indep_funcs); 146 SB_IMMED_3D(so, MACRO_BLEND_ENABLES, blend_en); 147 if (indep_funcs) { 148 for (i = 0; i < 8; ++i) { 149 if (cso->rt[i].blend_enable) { 150 SB_BEGIN_3D(so, IBLEND_EQUATION_RGB(i), 6); 151 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].rgb_func)); 152 SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_src_factor)); 153 SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_dst_factor)); 154 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].alpha_func)); 155 SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_src_factor)); 156 SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_dst_factor)); 157 } 158 } 159 } else 160 if (blend_en) { 161 SB_BEGIN_3D(so, BLEND_EQUATION_RGB, 5); 162 SB_DATA (so, nvgl_blend_eqn(cso->rt[r].rgb_func)); 163 SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_src_factor)); 164 SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_dst_factor)); 165 SB_DATA (so, nvgl_blend_eqn(cso->rt[r].alpha_func)); 166 SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_src_factor)); 167 SB_BEGIN_3D(so, BLEND_FUNC_DST_ALPHA, 1); 168 SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_dst_factor)); 169 } 170 171 SB_IMMED_3D(so, COLOR_MASK_COMMON, !indep_masks); 172 if (indep_masks) { 173 SB_BEGIN_3D(so, COLOR_MASK(0), 8); 174 for (i = 0; i < 8; ++i) 175 SB_DATA(so, nvc0_colormask(cso->rt[i].colormask)); 176 } else { 177 SB_BEGIN_3D(so, COLOR_MASK(0), 1); 178 SB_DATA (so, nvc0_colormask(cso->rt[0].colormask)); 179 } 180 } 181 182 ms = 0; 183 if (cso->alpha_to_coverage) 184 ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_COVERAGE; 185 if (cso->alpha_to_one) 186 ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_ONE; 187 188 SB_BEGIN_3D(so, MULTISAMPLE_CTRL, 1); 189 SB_DATA (so, ms); 190 191 assert(so->size <= ARRAY_SIZE(so->state)); 192 return so; 193} 194 195static void 196nvc0_blend_state_bind(struct pipe_context *pipe, void *hwcso) 197{ 198 struct nvc0_context *nvc0 = nvc0_context(pipe); 199 200 nvc0->blend = hwcso; 201 nvc0->dirty_3d |= NVC0_NEW_3D_BLEND; 202} 203 204static void 205nvc0_blend_state_delete(struct pipe_context *pipe, void *hwcso) 206{ 207 FREE(hwcso); 208} 209 210/* NOTE: ignoring line_last_pixel */ 211static void * 212nvc0_rasterizer_state_create(struct pipe_context *pipe, 213 const struct pipe_rasterizer_state *cso) 214{ 215 struct nvc0_rasterizer_stateobj *so; 216 uint16_t class_3d = nouveau_screen(pipe->screen)->class_3d; 217 uint32_t reg; 218 219 so = CALLOC_STRUCT(nvc0_rasterizer_stateobj); 220 if (!so) 221 return NULL; 222 so->pipe = *cso; 223 224 /* Scissor enables are handled in scissor state, we will not want to 225 * always emit 16 commands, one for each scissor rectangle, here. 226 */ 227 228 SB_IMMED_3D(so, PROVOKING_VERTEX_LAST, !cso->flatshade_first); 229 SB_IMMED_3D(so, VERTEX_TWO_SIDE_ENABLE, cso->light_twoside); 230 231 SB_IMMED_3D(so, VERT_COLOR_CLAMP_EN, cso->clamp_vertex_color); 232 SB_BEGIN_3D(so, FRAG_COLOR_CLAMP_EN, 1); 233 SB_DATA (so, cso->clamp_fragment_color ? 0x11111111 : 0x00000000); 234 235 SB_IMMED_3D(so, MULTISAMPLE_ENABLE, cso->multisample); 236 237 SB_IMMED_3D(so, LINE_SMOOTH_ENABLE, cso->line_smooth); 238 if (cso->line_smooth || cso->multisample) 239 SB_BEGIN_3D(so, LINE_WIDTH_SMOOTH, 1); 240 else 241 SB_BEGIN_3D(so, LINE_WIDTH_ALIASED, 1); 242 SB_DATA (so, fui(cso->line_width)); 243 244 SB_IMMED_3D(so, LINE_STIPPLE_ENABLE, cso->line_stipple_enable); 245 if (cso->line_stipple_enable) { 246 SB_BEGIN_3D(so, LINE_STIPPLE_PATTERN, 1); 247 SB_DATA (so, (cso->line_stipple_pattern << 8) | 248 cso->line_stipple_factor); 249 250 } 251 252 SB_IMMED_3D(so, VP_POINT_SIZE, cso->point_size_per_vertex); 253 if (!cso->point_size_per_vertex) { 254 SB_BEGIN_3D(so, POINT_SIZE, 1); 255 SB_DATA (so, fui(cso->point_size)); 256 } 257 258 reg = (cso->sprite_coord_mode == PIPE_SPRITE_COORD_UPPER_LEFT) ? 259 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_UPPER_LEFT : 260 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_LOWER_LEFT; 261 262 SB_BEGIN_3D(so, POINT_COORD_REPLACE, 1); 263 SB_DATA (so, ((cso->sprite_coord_enable & 0xff) << 3) | reg); 264 SB_IMMED_3D(so, POINT_SPRITE_ENABLE, cso->point_quad_rasterization); 265 SB_IMMED_3D(so, POINT_SMOOTH_ENABLE, cso->point_smooth); 266 267 if (class_3d >= GM200_3D_CLASS) { 268 SB_IMMED_3D(so, FILL_RECTANGLE, 269 cso->fill_front == PIPE_POLYGON_MODE_FILL_RECTANGLE ? 270 NVC0_3D_FILL_RECTANGLE_ENABLE : 0); 271 } 272 273 SB_BEGIN_3D(so, MACRO_POLYGON_MODE_FRONT, 1); 274 SB_DATA (so, nvgl_polygon_mode(cso->fill_front)); 275 SB_BEGIN_3D(so, MACRO_POLYGON_MODE_BACK, 1); 276 SB_DATA (so, nvgl_polygon_mode(cso->fill_back)); 277 SB_IMMED_3D(so, POLYGON_SMOOTH_ENABLE, cso->poly_smooth); 278 279 SB_BEGIN_3D(so, CULL_FACE_ENABLE, 3); 280 SB_DATA (so, cso->cull_face != PIPE_FACE_NONE); 281 SB_DATA (so, cso->front_ccw ? NVC0_3D_FRONT_FACE_CCW : 282 NVC0_3D_FRONT_FACE_CW); 283 switch (cso->cull_face) { 284 case PIPE_FACE_FRONT_AND_BACK: 285 SB_DATA(so, NVC0_3D_CULL_FACE_FRONT_AND_BACK); 286 break; 287 case PIPE_FACE_FRONT: 288 SB_DATA(so, NVC0_3D_CULL_FACE_FRONT); 289 break; 290 case PIPE_FACE_BACK: 291 default: 292 SB_DATA(so, NVC0_3D_CULL_FACE_BACK); 293 break; 294 } 295 296 SB_IMMED_3D(so, POLYGON_STIPPLE_ENABLE, cso->poly_stipple_enable); 297 SB_BEGIN_3D(so, POLYGON_OFFSET_POINT_ENABLE, 3); 298 SB_DATA (so, cso->offset_point); 299 SB_DATA (so, cso->offset_line); 300 SB_DATA (so, cso->offset_tri); 301 302 if (cso->offset_point || cso->offset_line || cso->offset_tri) { 303 SB_BEGIN_3D(so, POLYGON_OFFSET_FACTOR, 1); 304 SB_DATA (so, fui(cso->offset_scale)); 305 if (!cso->offset_units_unscaled) { 306 SB_BEGIN_3D(so, POLYGON_OFFSET_UNITS, 1); 307 SB_DATA (so, fui(cso->offset_units * 2.0f)); 308 } 309 SB_BEGIN_3D(so, POLYGON_OFFSET_CLAMP, 1); 310 SB_DATA (so, fui(cso->offset_clamp)); 311 } 312 313 if (cso->depth_clip_near) 314 reg = NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1; 315 else 316 reg = 317 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1 | 318 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_NEAR | 319 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_FAR | 320 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK2; 321 322 SB_BEGIN_3D(so, VIEW_VOLUME_CLIP_CTRL, 1); 323 SB_DATA (so, reg); 324 325 SB_IMMED_3D(so, DEPTH_CLIP_NEGATIVE_Z, cso->clip_halfz); 326 327 SB_IMMED_3D(so, PIXEL_CENTER_INTEGER, !cso->half_pixel_center); 328 329 if (class_3d >= GM200_3D_CLASS) { 330 if (cso->conservative_raster_mode != PIPE_CONSERVATIVE_RASTER_OFF) { 331 bool post_snap = cso->conservative_raster_mode == 332 PIPE_CONSERVATIVE_RASTER_POST_SNAP; 333 uint32_t state = cso->subpixel_precision_x; 334 state |= cso->subpixel_precision_y << 4; 335 state |= (uint32_t)(cso->conservative_raster_dilate * 4) << 8; 336 state |= (post_snap || class_3d < GP100_3D_CLASS) ? 1 << 10 : 0; 337 SB_IMMED_3D(so, MACRO_CONSERVATIVE_RASTER_STATE, state); 338 } else { 339 SB_IMMED_3D(so, CONSERVATIVE_RASTER, 0); 340 } 341 } 342 343 assert(so->size <= ARRAY_SIZE(so->state)); 344 return (void *)so; 345} 346 347static void 348nvc0_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso) 349{ 350 struct nvc0_context *nvc0 = nvc0_context(pipe); 351 352 nvc0->rast = hwcso; 353 nvc0->dirty_3d |= NVC0_NEW_3D_RASTERIZER; 354} 355 356static void 357nvc0_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso) 358{ 359 FREE(hwcso); 360} 361 362static void * 363nvc0_zsa_state_create(struct pipe_context *pipe, 364 const struct pipe_depth_stencil_alpha_state *cso) 365{ 366 struct nvc0_zsa_stateobj *so = CALLOC_STRUCT(nvc0_zsa_stateobj); 367 368 so->pipe = *cso; 369 370 SB_IMMED_3D(so, DEPTH_TEST_ENABLE, cso->depth_enabled); 371 if (cso->depth_enabled) { 372 SB_IMMED_3D(so, DEPTH_WRITE_ENABLE, cso->depth_writemask); 373 SB_BEGIN_3D(so, DEPTH_TEST_FUNC, 1); 374 SB_DATA (so, nvgl_comparison_op(cso->depth_func)); 375 } 376 377 SB_IMMED_3D(so, DEPTH_BOUNDS_EN, cso->depth_bounds_test); 378 if (cso->depth_bounds_test) { 379 SB_BEGIN_3D(so, DEPTH_BOUNDS(0), 2); 380 SB_DATA (so, fui(cso->depth_bounds_min)); 381 SB_DATA (so, fui(cso->depth_bounds_max)); 382 } 383 384 if (cso->stencil[0].enabled) { 385 SB_BEGIN_3D(so, STENCIL_ENABLE, 5); 386 SB_DATA (so, 1); 387 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].fail_op)); 388 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zfail_op)); 389 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zpass_op)); 390 SB_DATA (so, nvgl_comparison_op(cso->stencil[0].func)); 391 SB_BEGIN_3D(so, STENCIL_FRONT_FUNC_MASK, 2); 392 SB_DATA (so, cso->stencil[0].valuemask); 393 SB_DATA (so, cso->stencil[0].writemask); 394 } else { 395 SB_IMMED_3D(so, STENCIL_ENABLE, 0); 396 } 397 398 if (cso->stencil[1].enabled) { 399 assert(cso->stencil[0].enabled); 400 SB_BEGIN_3D(so, STENCIL_TWO_SIDE_ENABLE, 5); 401 SB_DATA (so, 1); 402 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].fail_op)); 403 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zfail_op)); 404 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zpass_op)); 405 SB_DATA (so, nvgl_comparison_op(cso->stencil[1].func)); 406 SB_BEGIN_3D(so, STENCIL_BACK_MASK, 2); 407 SB_DATA (so, cso->stencil[1].writemask); 408 SB_DATA (so, cso->stencil[1].valuemask); 409 } else 410 if (cso->stencil[0].enabled) { 411 SB_IMMED_3D(so, STENCIL_TWO_SIDE_ENABLE, 0); 412 } 413 414 SB_IMMED_3D(so, ALPHA_TEST_ENABLE, cso->alpha_enabled); 415 if (cso->alpha_enabled) { 416 SB_BEGIN_3D(so, ALPHA_TEST_REF, 2); 417 SB_DATA (so, fui(cso->alpha_ref_value)); 418 SB_DATA (so, nvgl_comparison_op(cso->alpha_func)); 419 } 420 421 assert(so->size <= ARRAY_SIZE(so->state)); 422 return (void *)so; 423} 424 425static void 426nvc0_zsa_state_bind(struct pipe_context *pipe, void *hwcso) 427{ 428 struct nvc0_context *nvc0 = nvc0_context(pipe); 429 430 nvc0->zsa = hwcso; 431 nvc0->dirty_3d |= NVC0_NEW_3D_ZSA; 432} 433 434static void 435nvc0_zsa_state_delete(struct pipe_context *pipe, void *hwcso) 436{ 437 FREE(hwcso); 438} 439 440/* ====================== SAMPLERS AND TEXTURES ================================ 441 */ 442 443#define NV50_TSC_WRAP_CASE(n) \ 444 case PIPE_TEX_WRAP_##n: return NV50_TSC_WRAP_##n 445 446static void 447nvc0_sampler_state_delete(struct pipe_context *pipe, void *hwcso) 448{ 449 unsigned s, i; 450 451 for (s = 0; s < 6; ++s) 452 for (i = 0; i < nvc0_context(pipe)->num_samplers[s]; ++i) 453 if (nvc0_context(pipe)->samplers[s][i] == hwcso) 454 nvc0_context(pipe)->samplers[s][i] = NULL; 455 456 nvc0_screen_tsc_free(nvc0_context(pipe)->screen, nv50_tsc_entry(hwcso)); 457 458 FREE(hwcso); 459} 460 461static inline void 462nvc0_stage_sampler_states_bind(struct nvc0_context *nvc0, 463 unsigned s, 464 unsigned nr, void **hwcsos) 465{ 466 unsigned highest_found = 0; 467 unsigned i; 468 469 for (i = 0; i < nr; ++i) { 470 struct nv50_tsc_entry *hwcso = hwcsos ? nv50_tsc_entry(hwcsos[i]) : NULL; 471 struct nv50_tsc_entry *old = nvc0->samplers[s][i]; 472 473 if (hwcso) 474 highest_found = i; 475 476 if (hwcso == old) 477 continue; 478 nvc0->samplers_dirty[s] |= 1 << i; 479 480 nvc0->samplers[s][i] = hwcso; 481 if (old) 482 nvc0_screen_tsc_unlock(nvc0->screen, old); 483 } 484 if (nr >= nvc0->num_samplers[s]) 485 nvc0->num_samplers[s] = highest_found + 1; 486} 487 488static void 489nvc0_bind_sampler_states(struct pipe_context *pipe, 490 enum pipe_shader_type shader, 491 unsigned start, unsigned nr, void **samplers) 492{ 493 const unsigned s = nvc0_shader_stage(shader); 494 495 assert(start == 0); 496 nvc0_stage_sampler_states_bind(nvc0_context(pipe), s, nr, samplers); 497 498 if (s == 5) 499 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SAMPLERS; 500 else 501 nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_SAMPLERS; 502} 503 504 505/* NOTE: only called when not referenced anywhere, won't be bound */ 506static void 507nvc0_sampler_view_destroy(struct pipe_context *pipe, 508 struct pipe_sampler_view *view) 509{ 510 pipe_resource_reference(&view->texture, NULL); 511 512 nvc0_screen_tic_free(nvc0_context(pipe)->screen, nv50_tic_entry(view)); 513 514 FREE(nv50_tic_entry(view)); 515} 516 517static inline void 518nvc0_stage_set_sampler_views(struct nvc0_context *nvc0, int s, 519 unsigned nr, bool take_ownership, 520 struct pipe_sampler_view **views) 521{ 522 unsigned i; 523 524 for (i = 0; i < nr; ++i) { 525 struct pipe_sampler_view *view = views ? views[i] : NULL; 526 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]); 527 528 if (view == nvc0->textures[s][i]) { 529 if (take_ownership) 530 pipe_sampler_view_reference(&view, NULL); 531 continue; 532 } 533 nvc0->textures_dirty[s] |= 1 << i; 534 535 if (view && view->texture) { 536 struct pipe_resource *res = view->texture; 537 if (res->target == PIPE_BUFFER && 538 (res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)) 539 nvc0->textures_coherent[s] |= 1 << i; 540 else 541 nvc0->textures_coherent[s] &= ~(1 << i); 542 } else { 543 nvc0->textures_coherent[s] &= ~(1 << i); 544 } 545 546 if (old) { 547 if (s == 5) 548 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_TEX(i)); 549 else 550 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(s, i)); 551 nvc0_screen_tic_unlock(nvc0->screen, old); 552 } 553 554 if (take_ownership) { 555 pipe_sampler_view_reference(&nvc0->textures[s][i], NULL); 556 nvc0->textures[s][i] = view; 557 } else { 558 pipe_sampler_view_reference(&nvc0->textures[s][i], view); 559 } 560 } 561 562 for (i = nr; i < nvc0->num_textures[s]; ++i) { 563 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]); 564 if (old) { 565 if (s == 5) 566 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_TEX(i)); 567 else 568 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(s, i)); 569 nvc0_screen_tic_unlock(nvc0->screen, old); 570 pipe_sampler_view_reference(&nvc0->textures[s][i], NULL); 571 } 572 } 573 574 nvc0->num_textures[s] = nr; 575} 576 577static void 578nvc0_set_sampler_views(struct pipe_context *pipe, enum pipe_shader_type shader, 579 unsigned start, unsigned nr, 580 unsigned unbind_num_trailing_slots, 581 bool take_ownership, 582 struct pipe_sampler_view **views) 583{ 584 const unsigned s = nvc0_shader_stage(shader); 585 586 assert(start == 0); 587 nvc0_stage_set_sampler_views(nvc0_context(pipe), s, nr, take_ownership, views); 588 589 if (s == 5) 590 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_TEXTURES; 591 else 592 nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_TEXTURES; 593} 594 595/* ============================= SHADERS ======================================= 596 */ 597 598static void * 599nvc0_sp_state_create(struct pipe_context *pipe, 600 const struct pipe_shader_state *cso, unsigned type) 601{ 602 struct nvc0_program *prog; 603 604 prog = CALLOC_STRUCT(nvc0_program); 605 if (!prog) 606 return NULL; 607 608 prog->type = type; 609 prog->pipe.type = cso->type; 610 611 switch(cso->type) { 612 case PIPE_SHADER_IR_TGSI: 613 prog->pipe.tokens = tgsi_dup_tokens(cso->tokens); 614 break; 615 case PIPE_SHADER_IR_NIR: 616 prog->pipe.ir.nir = cso->ir.nir; 617 break; 618 default: 619 assert(!"unsupported IR!"); 620 free(prog); 621 return NULL; 622 } 623 624 if (cso->stream_output.num_outputs) 625 prog->pipe.stream_output = cso->stream_output; 626 627 prog->translated = nvc0_program_translate( 628 prog, nvc0_context(pipe)->screen->base.device->chipset, 629 nvc0_context(pipe)->screen->base.disk_shader_cache, 630 &nouveau_context(pipe)->debug); 631 632 return (void *)prog; 633} 634 635static void 636nvc0_sp_state_delete(struct pipe_context *pipe, void *hwcso) 637{ 638 struct nvc0_program *prog = (struct nvc0_program *)hwcso; 639 640 nvc0_program_destroy(nvc0_context(pipe), prog); 641 642 if (prog->pipe.type == PIPE_SHADER_IR_TGSI) 643 FREE((void *)prog->pipe.tokens); 644 else if (prog->pipe.type == PIPE_SHADER_IR_NIR) 645 ralloc_free(prog->pipe.ir.nir); 646 FREE(prog); 647} 648 649static void * 650nvc0_vp_state_create(struct pipe_context *pipe, 651 const struct pipe_shader_state *cso) 652{ 653 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_VERTEX); 654} 655 656static void 657nvc0_vp_state_bind(struct pipe_context *pipe, void *hwcso) 658{ 659 struct nvc0_context *nvc0 = nvc0_context(pipe); 660 661 nvc0->vertprog = hwcso; 662 nvc0->dirty_3d |= NVC0_NEW_3D_VERTPROG; 663} 664 665static void * 666nvc0_fp_state_create(struct pipe_context *pipe, 667 const struct pipe_shader_state *cso) 668{ 669 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_FRAGMENT); 670} 671 672static void 673nvc0_fp_state_bind(struct pipe_context *pipe, void *hwcso) 674{ 675 struct nvc0_context *nvc0 = nvc0_context(pipe); 676 677 nvc0->fragprog = hwcso; 678 nvc0->dirty_3d |= NVC0_NEW_3D_FRAGPROG; 679} 680 681static void * 682nvc0_gp_state_create(struct pipe_context *pipe, 683 const struct pipe_shader_state *cso) 684{ 685 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_GEOMETRY); 686} 687 688static void 689nvc0_gp_state_bind(struct pipe_context *pipe, void *hwcso) 690{ 691 struct nvc0_context *nvc0 = nvc0_context(pipe); 692 693 nvc0->gmtyprog = hwcso; 694 nvc0->dirty_3d |= NVC0_NEW_3D_GMTYPROG; 695} 696 697static void * 698nvc0_tcp_state_create(struct pipe_context *pipe, 699 const struct pipe_shader_state *cso) 700{ 701 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_CTRL); 702} 703 704static void 705nvc0_tcp_state_bind(struct pipe_context *pipe, void *hwcso) 706{ 707 struct nvc0_context *nvc0 = nvc0_context(pipe); 708 709 nvc0->tctlprog = hwcso; 710 nvc0->dirty_3d |= NVC0_NEW_3D_TCTLPROG; 711} 712 713static void * 714nvc0_tep_state_create(struct pipe_context *pipe, 715 const struct pipe_shader_state *cso) 716{ 717 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_EVAL); 718} 719 720static void 721nvc0_tep_state_bind(struct pipe_context *pipe, void *hwcso) 722{ 723 struct nvc0_context *nvc0 = nvc0_context(pipe); 724 725 nvc0->tevlprog = hwcso; 726 nvc0->dirty_3d |= NVC0_NEW_3D_TEVLPROG; 727} 728 729static void * 730nvc0_cp_state_create(struct pipe_context *pipe, 731 const struct pipe_compute_state *cso) 732{ 733 struct nvc0_program *prog; 734 735 prog = CALLOC_STRUCT(nvc0_program); 736 if (!prog) 737 return NULL; 738 prog->type = PIPE_SHADER_COMPUTE; 739 prog->pipe.type = cso->ir_type; 740 741 prog->cp.smem_size = cso->req_local_mem; 742 prog->cp.lmem_size = cso->req_private_mem; 743 prog->parm_size = cso->req_input_mem; 744 745 switch(cso->ir_type) { 746 case PIPE_SHADER_IR_TGSI: 747 prog->pipe.tokens = tgsi_dup_tokens((const struct tgsi_token *)cso->prog); 748 break; 749 case PIPE_SHADER_IR_NIR: 750 prog->pipe.ir.nir = (nir_shader *)cso->prog; 751 break; 752 case PIPE_SHADER_IR_NIR_SERIALIZED: { 753 struct blob_reader reader; 754 const struct pipe_binary_program_header *hdr = cso->prog; 755 756 blob_reader_init(&reader, hdr->blob, hdr->num_bytes); 757 prog->pipe.ir.nir = nir_deserialize(NULL, pipe->screen->get_compiler_options(pipe->screen, PIPE_SHADER_IR_NIR, PIPE_SHADER_COMPUTE), &reader); 758 prog->pipe.type = PIPE_SHADER_IR_NIR; 759 break; 760 } 761 default: 762 assert(!"unsupported IR!"); 763 free(prog); 764 return NULL; 765 } 766 767 prog->translated = nvc0_program_translate( 768 prog, nvc0_context(pipe)->screen->base.device->chipset, 769 nvc0_context(pipe)->screen->base.disk_shader_cache, 770 &nouveau_context(pipe)->debug); 771 772 return (void *)prog; 773} 774 775static void 776nvc0_cp_state_bind(struct pipe_context *pipe, void *hwcso) 777{ 778 struct nvc0_context *nvc0 = nvc0_context(pipe); 779 780 nvc0->compprog = hwcso; 781 nvc0->dirty_cp |= NVC0_NEW_CP_PROGRAM; 782} 783 784static void 785nvc0_set_constant_buffer(struct pipe_context *pipe, 786 enum pipe_shader_type shader, uint index, 787 bool take_ownership, 788 const struct pipe_constant_buffer *cb) 789{ 790 struct nvc0_context *nvc0 = nvc0_context(pipe); 791 struct pipe_resource *res = cb ? cb->buffer : NULL; 792 const unsigned s = nvc0_shader_stage(shader); 793 const unsigned i = index; 794 795 if (unlikely(shader == PIPE_SHADER_COMPUTE)) { 796 if (nvc0->constbuf[s][i].user) 797 nvc0->constbuf[s][i].u.buf = NULL; 798 else 799 if (nvc0->constbuf[s][i].u.buf) 800 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_CB(i)); 801 802 nvc0->dirty_cp |= NVC0_NEW_CP_CONSTBUF; 803 } else { 804 if (nvc0->constbuf[s][i].user) 805 nvc0->constbuf[s][i].u.buf = NULL; 806 else 807 if (nvc0->constbuf[s][i].u.buf) 808 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_CB(s, i)); 809 810 nvc0->dirty_3d |= NVC0_NEW_3D_CONSTBUF; 811 } 812 nvc0->constbuf_dirty[s] |= 1 << i; 813 814 if (nvc0->constbuf[s][i].u.buf) 815 nv04_resource(nvc0->constbuf[s][i].u.buf)->cb_bindings[s] &= ~(1 << i); 816 817 if (take_ownership) { 818 pipe_resource_reference(&nvc0->constbuf[s][i].u.buf, NULL); 819 nvc0->constbuf[s][i].u.buf = res; 820 } else { 821 pipe_resource_reference(&nvc0->constbuf[s][i].u.buf, res); 822 } 823 824 nvc0->constbuf[s][i].user = (cb && cb->user_buffer) ? true : false; 825 if (nvc0->constbuf[s][i].user) { 826 nvc0->constbuf[s][i].u.data = cb->user_buffer; 827 nvc0->constbuf[s][i].size = MIN2(cb->buffer_size, 0x10000); 828 nvc0->constbuf_valid[s] |= 1 << i; 829 nvc0->constbuf_coherent[s] &= ~(1 << i); 830 } else 831 if (cb) { 832 nvc0->constbuf[s][i].offset = cb->buffer_offset; 833 nvc0->constbuf[s][i].size = MIN2(align(cb->buffer_size, 0x100), 0x10000); 834 nvc0->constbuf_valid[s] |= 1 << i; 835 if (res && res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT) 836 nvc0->constbuf_coherent[s] |= 1 << i; 837 else 838 nvc0->constbuf_coherent[s] &= ~(1 << i); 839 } 840 else { 841 nvc0->constbuf_valid[s] &= ~(1 << i); 842 nvc0->constbuf_coherent[s] &= ~(1 << i); 843 } 844} 845 846/* ============================================================================= 847 */ 848 849static void 850nvc0_set_blend_color(struct pipe_context *pipe, 851 const struct pipe_blend_color *bcol) 852{ 853 struct nvc0_context *nvc0 = nvc0_context(pipe); 854 855 nvc0->blend_colour = *bcol; 856 nvc0->dirty_3d |= NVC0_NEW_3D_BLEND_COLOUR; 857} 858 859static void 860nvc0_set_stencil_ref(struct pipe_context *pipe, 861 const struct pipe_stencil_ref sr) 862{ 863 struct nvc0_context *nvc0 = nvc0_context(pipe); 864 865 nvc0->stencil_ref = sr; 866 nvc0->dirty_3d |= NVC0_NEW_3D_STENCIL_REF; 867} 868 869static void 870nvc0_set_clip_state(struct pipe_context *pipe, 871 const struct pipe_clip_state *clip) 872{ 873 struct nvc0_context *nvc0 = nvc0_context(pipe); 874 875 memcpy(nvc0->clip.ucp, clip->ucp, sizeof(clip->ucp)); 876 877 nvc0->dirty_3d |= NVC0_NEW_3D_CLIP; 878} 879 880static void 881nvc0_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask) 882{ 883 struct nvc0_context *nvc0 = nvc0_context(pipe); 884 885 nvc0->sample_mask = sample_mask; 886 nvc0->dirty_3d |= NVC0_NEW_3D_SAMPLE_MASK; 887} 888 889static void 890nvc0_set_min_samples(struct pipe_context *pipe, unsigned min_samples) 891{ 892 struct nvc0_context *nvc0 = nvc0_context(pipe); 893 894 if (nvc0->min_samples != min_samples) { 895 nvc0->min_samples = min_samples; 896 nvc0->dirty_3d |= NVC0_NEW_3D_MIN_SAMPLES; 897 } 898} 899 900static void 901nvc0_set_framebuffer_state(struct pipe_context *pipe, 902 const struct pipe_framebuffer_state *fb) 903{ 904 struct nvc0_context *nvc0 = nvc0_context(pipe); 905 906 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_FB); 907 908 util_copy_framebuffer_state(&nvc0->framebuffer, fb); 909 910 nvc0->dirty_3d |= NVC0_NEW_3D_FRAMEBUFFER | NVC0_NEW_3D_SAMPLE_LOCATIONS | 911 NVC0_NEW_3D_TEXTURES; 912 nvc0->dirty_cp |= NVC0_NEW_CP_TEXTURES; 913} 914 915static void 916nvc0_set_sample_locations(struct pipe_context *pipe, 917 size_t size, const uint8_t *locations) 918{ 919 struct nvc0_context *nvc0 = nvc0_context(pipe); 920 921 nvc0->sample_locations_enabled = size && locations; 922 if (size > sizeof(nvc0->sample_locations)) 923 size = sizeof(nvc0->sample_locations); 924 memcpy(nvc0->sample_locations, locations, size); 925 926 nvc0->dirty_3d |= NVC0_NEW_3D_SAMPLE_LOCATIONS; 927} 928 929static void 930nvc0_set_polygon_stipple(struct pipe_context *pipe, 931 const struct pipe_poly_stipple *stipple) 932{ 933 struct nvc0_context *nvc0 = nvc0_context(pipe); 934 935 nvc0->stipple = *stipple; 936 nvc0->dirty_3d |= NVC0_NEW_3D_STIPPLE; 937} 938 939static void 940nvc0_set_scissor_states(struct pipe_context *pipe, 941 unsigned start_slot, 942 unsigned num_scissors, 943 const struct pipe_scissor_state *scissor) 944{ 945 struct nvc0_context *nvc0 = nvc0_context(pipe); 946 int i; 947 948 assert(start_slot + num_scissors <= NVC0_MAX_VIEWPORTS); 949 for (i = 0; i < num_scissors; i++) { 950 if (!memcmp(&nvc0->scissors[start_slot + i], &scissor[i], sizeof(*scissor))) 951 continue; 952 nvc0->scissors[start_slot + i] = scissor[i]; 953 nvc0->scissors_dirty |= 1 << (start_slot + i); 954 nvc0->dirty_3d |= NVC0_NEW_3D_SCISSOR; 955 } 956} 957 958static void 959nvc0_set_viewport_states(struct pipe_context *pipe, 960 unsigned start_slot, 961 unsigned num_viewports, 962 const struct pipe_viewport_state *vpt) 963{ 964 struct nvc0_context *nvc0 = nvc0_context(pipe); 965 int i; 966 967 assert(start_slot + num_viewports <= NVC0_MAX_VIEWPORTS); 968 for (i = 0; i < num_viewports; i++) { 969 if (!memcmp(&nvc0->viewports[start_slot + i], &vpt[i], sizeof(*vpt))) 970 continue; 971 nvc0->viewports[start_slot + i] = vpt[i]; 972 nvc0->viewports_dirty |= 1 << (start_slot + i); 973 nvc0->dirty_3d |= NVC0_NEW_3D_VIEWPORT; 974 } 975 976} 977 978static void 979nvc0_set_window_rectangles(struct pipe_context *pipe, 980 bool include, 981 unsigned num_rectangles, 982 const struct pipe_scissor_state *rectangles) 983{ 984 struct nvc0_context *nvc0 = nvc0_context(pipe); 985 986 nvc0->window_rect.inclusive = include; 987 nvc0->window_rect.rects = MIN2(num_rectangles, NVC0_MAX_WINDOW_RECTANGLES); 988 memcpy(nvc0->window_rect.rect, rectangles, 989 sizeof(struct pipe_scissor_state) * nvc0->window_rect.rects); 990 991 nvc0->dirty_3d |= NVC0_NEW_3D_WINDOW_RECTS; 992} 993 994static void 995nvc0_set_tess_state(struct pipe_context *pipe, 996 const float default_tess_outer[4], 997 const float default_tess_inner[2]) 998{ 999 struct nvc0_context *nvc0 = nvc0_context(pipe); 1000 1001 memcpy(nvc0->default_tess_outer, default_tess_outer, 4 * sizeof(float)); 1002 memcpy(nvc0->default_tess_inner, default_tess_inner, 2 * sizeof(float)); 1003 nvc0->dirty_3d |= NVC0_NEW_3D_TESSFACTOR; 1004} 1005 1006static void 1007nvc0_set_patch_vertices(struct pipe_context *pipe, uint8_t patch_vertices) 1008{ 1009 struct nvc0_context *nvc0 = nvc0_context(pipe); 1010 1011 nvc0->patch_vertices = patch_vertices; 1012} 1013 1014static void 1015nvc0_set_vertex_buffers(struct pipe_context *pipe, 1016 unsigned start_slot, unsigned count, 1017 unsigned unbind_num_trailing_slots, 1018 bool take_ownership, 1019 const struct pipe_vertex_buffer *vb) 1020{ 1021 struct nvc0_context *nvc0 = nvc0_context(pipe); 1022 unsigned i; 1023 1024 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_VTX); 1025 nvc0->dirty_3d |= NVC0_NEW_3D_ARRAYS; 1026 1027 util_set_vertex_buffers_count(nvc0->vtxbuf, &nvc0->num_vtxbufs, vb, 1028 start_slot, count, 1029 unbind_num_trailing_slots, 1030 take_ownership); 1031 1032 unsigned clear_mask = ~u_bit_consecutive(start_slot + count, unbind_num_trailing_slots); 1033 nvc0->vbo_user &= clear_mask; 1034 nvc0->constant_vbos &= clear_mask; 1035 nvc0->vtxbufs_coherent &= clear_mask; 1036 1037 if (!vb) { 1038 clear_mask = ~u_bit_consecutive(start_slot, count); 1039 nvc0->vbo_user &= clear_mask; 1040 nvc0->constant_vbos &= clear_mask; 1041 nvc0->vtxbufs_coherent &= clear_mask; 1042 return; 1043 } 1044 1045 for (i = 0; i < count; ++i) { 1046 unsigned dst_index = start_slot + i; 1047 1048 if (vb[i].is_user_buffer) { 1049 nvc0->vbo_user |= 1 << dst_index; 1050 if (!vb[i].stride && nvc0->screen->eng3d->oclass < GM107_3D_CLASS) 1051 nvc0->constant_vbos |= 1 << dst_index; 1052 else 1053 nvc0->constant_vbos &= ~(1 << dst_index); 1054 nvc0->vtxbufs_coherent &= ~(1 << dst_index); 1055 } else { 1056 nvc0->vbo_user &= ~(1 << dst_index); 1057 nvc0->constant_vbos &= ~(1 << dst_index); 1058 1059 if (vb[i].buffer.resource && 1060 vb[i].buffer.resource->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT) 1061 nvc0->vtxbufs_coherent |= (1 << dst_index); 1062 else 1063 nvc0->vtxbufs_coherent &= ~(1 << dst_index); 1064 } 1065 } 1066} 1067 1068static void 1069nvc0_vertex_state_bind(struct pipe_context *pipe, void *hwcso) 1070{ 1071 struct nvc0_context *nvc0 = nvc0_context(pipe); 1072 1073 nvc0->vertex = hwcso; 1074 nvc0->dirty_3d |= NVC0_NEW_3D_VERTEX; 1075} 1076 1077static struct pipe_stream_output_target * 1078nvc0_so_target_create(struct pipe_context *pipe, 1079 struct pipe_resource *res, 1080 unsigned offset, unsigned size) 1081{ 1082 struct nv04_resource *buf = (struct nv04_resource *)res; 1083 struct nvc0_so_target *targ = MALLOC_STRUCT(nvc0_so_target); 1084 if (!targ) 1085 return NULL; 1086 1087 targ->pq = pipe->create_query(pipe, NVC0_HW_QUERY_TFB_BUFFER_OFFSET, 0); 1088 if (!targ->pq) { 1089 FREE(targ); 1090 return NULL; 1091 } 1092 targ->clean = true; 1093 1094 targ->pipe.buffer_size = size; 1095 targ->pipe.buffer_offset = offset; 1096 targ->pipe.context = pipe; 1097 targ->pipe.buffer = NULL; 1098 pipe_resource_reference(&targ->pipe.buffer, res); 1099 pipe_reference_init(&targ->pipe.reference, 1); 1100 1101 assert(buf->base.target == PIPE_BUFFER); 1102 util_range_add(&buf->base, &buf->valid_buffer_range, offset, offset + size); 1103 1104 return &targ->pipe; 1105} 1106 1107static void 1108nvc0_so_target_save_offset(struct pipe_context *pipe, 1109 struct pipe_stream_output_target *ptarg, 1110 unsigned index, bool *serialize) 1111{ 1112 struct nvc0_so_target *targ = nvc0_so_target(ptarg); 1113 1114 if (*serialize) { 1115 *serialize = false; 1116 PUSH_SPACE(nvc0_context(pipe)->base.pushbuf, 1); 1117 IMMED_NVC0(nvc0_context(pipe)->base.pushbuf, NVC0_3D(SERIALIZE), 0); 1118 1119 NOUVEAU_DRV_STAT(nouveau_screen(pipe->screen), gpu_serialize_count, 1); 1120 } 1121 1122 nvc0_query(targ->pq)->index = index; 1123 pipe->end_query(pipe, targ->pq); 1124} 1125 1126static void 1127nvc0_so_target_destroy(struct pipe_context *pipe, 1128 struct pipe_stream_output_target *ptarg) 1129{ 1130 struct nvc0_so_target *targ = nvc0_so_target(ptarg); 1131 pipe->destroy_query(pipe, targ->pq); 1132 pipe_resource_reference(&targ->pipe.buffer, NULL); 1133 FREE(targ); 1134} 1135 1136static void 1137nvc0_set_transform_feedback_targets(struct pipe_context *pipe, 1138 unsigned num_targets, 1139 struct pipe_stream_output_target **targets, 1140 const unsigned *offsets) 1141{ 1142 struct nvc0_context *nvc0 = nvc0_context(pipe); 1143 unsigned i; 1144 bool serialize = true; 1145 1146 assert(num_targets <= 4); 1147 1148 for (i = 0; i < num_targets; ++i) { 1149 const bool changed = nvc0->tfbbuf[i] != targets[i]; 1150 const bool append = (offsets[i] == ((unsigned)-1)); 1151 if (!changed && append) 1152 continue; 1153 nvc0->tfbbuf_dirty |= 1 << i; 1154 1155 if (nvc0->tfbbuf[i] && changed) 1156 nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize); 1157 1158 if (targets[i] && !append) 1159 nvc0_so_target(targets[i])->clean = true; 1160 1161 pipe_so_target_reference(&nvc0->tfbbuf[i], targets[i]); 1162 } 1163 for (; i < nvc0->num_tfbbufs; ++i) { 1164 if (nvc0->tfbbuf[i]) { 1165 nvc0->tfbbuf_dirty |= 1 << i; 1166 nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize); 1167 pipe_so_target_reference(&nvc0->tfbbuf[i], NULL); 1168 } 1169 } 1170 nvc0->num_tfbbufs = num_targets; 1171 1172 if (nvc0->tfbbuf_dirty) { 1173 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TFB); 1174 nvc0->dirty_3d |= NVC0_NEW_3D_TFB_TARGETS; 1175 } 1176} 1177 1178static void 1179nvc0_bind_surfaces_range(struct nvc0_context *nvc0, const unsigned t, 1180 unsigned start, unsigned nr, 1181 struct pipe_surface **psurfaces) 1182{ 1183 const unsigned end = start + nr; 1184 const unsigned mask = ((1 << nr) - 1) << start; 1185 unsigned i; 1186 1187 if (psurfaces) { 1188 for (i = start; i < end; ++i) { 1189 const unsigned p = i - start; 1190 if (psurfaces[p]) 1191 nvc0->surfaces_valid[t] |= (1 << i); 1192 else 1193 nvc0->surfaces_valid[t] &= ~(1 << i); 1194 pipe_surface_reference(&nvc0->surfaces[t][i], psurfaces[p]); 1195 } 1196 } else { 1197 for (i = start; i < end; ++i) 1198 pipe_surface_reference(&nvc0->surfaces[t][i], NULL); 1199 nvc0->surfaces_valid[t] &= ~mask; 1200 } 1201 nvc0->surfaces_dirty[t] |= mask; 1202 1203 if (t == 0) 1204 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_SUF); 1205 else 1206 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_SUF); 1207} 1208 1209static void 1210nvc0_set_compute_resources(struct pipe_context *pipe, 1211 unsigned start, unsigned nr, 1212 struct pipe_surface **resources) 1213{ 1214 nvc0_bind_surfaces_range(nvc0_context(pipe), 1, start, nr, resources); 1215 1216 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SURFACES; 1217} 1218 1219static bool 1220nvc0_bind_images_range(struct nvc0_context *nvc0, const unsigned s, 1221 unsigned start, unsigned nr, 1222 const struct pipe_image_view *pimages) 1223{ 1224 const unsigned end = start + nr; 1225 unsigned mask = 0; 1226 unsigned i; 1227 1228 assert(s < 6); 1229 1230 if (pimages) { 1231 for (i = start; i < end; ++i) { 1232 struct pipe_image_view *img = &nvc0->images[s][i]; 1233 const unsigned p = i - start; 1234 1235 if (img->resource == pimages[p].resource && 1236 img->format == pimages[p].format && 1237 img->access == pimages[p].access) { 1238 if (img->resource == NULL) 1239 continue; 1240 if (img->resource->target == PIPE_BUFFER && 1241 img->u.buf.offset == pimages[p].u.buf.offset && 1242 img->u.buf.size == pimages[p].u.buf.size) 1243 continue; 1244 if (img->resource->target != PIPE_BUFFER && 1245 img->u.tex.first_layer == pimages[p].u.tex.first_layer && 1246 img->u.tex.last_layer == pimages[p].u.tex.last_layer && 1247 img->u.tex.level == pimages[p].u.tex.level) 1248 continue; 1249 } 1250 1251 mask |= (1 << i); 1252 if (pimages[p].resource) 1253 nvc0->images_valid[s] |= (1 << i); 1254 else 1255 nvc0->images_valid[s] &= ~(1 << i); 1256 1257 img->format = pimages[p].format; 1258 img->access = pimages[p].access; 1259 if (pimages[p].resource && pimages[p].resource->target == PIPE_BUFFER) 1260 img->u.buf = pimages[p].u.buf; 1261 else 1262 img->u.tex = pimages[p].u.tex; 1263 1264 pipe_resource_reference( 1265 &img->resource, pimages[p].resource); 1266 1267 if (nvc0->screen->base.class_3d >= GM107_3D_CLASS) { 1268 if (nvc0->images_tic[s][i]) { 1269 struct nv50_tic_entry *old = 1270 nv50_tic_entry(nvc0->images_tic[s][i]); 1271 nvc0_screen_tic_unlock(nvc0->screen, old); 1272 pipe_sampler_view_reference(&nvc0->images_tic[s][i], NULL); 1273 } 1274 1275 nvc0->images_tic[s][i] = 1276 gm107_create_texture_view_from_image(&nvc0->base.pipe, 1277 &pimages[p]); 1278 } 1279 } 1280 if (!mask) 1281 return false; 1282 } else { 1283 mask = ((1 << nr) - 1) << start; 1284 if (!(nvc0->images_valid[s] & mask)) 1285 return false; 1286 for (i = start; i < end; ++i) { 1287 pipe_resource_reference(&nvc0->images[s][i].resource, NULL); 1288 if (nvc0->screen->base.class_3d >= GM107_3D_CLASS) { 1289 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->images_tic[s][i]); 1290 if (old) { 1291 nvc0_screen_tic_unlock(nvc0->screen, old); 1292 pipe_sampler_view_reference(&nvc0->images_tic[s][i], NULL); 1293 } 1294 } 1295 } 1296 nvc0->images_valid[s] &= ~mask; 1297 } 1298 nvc0->images_dirty[s] |= mask; 1299 1300 if (s == 5) 1301 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_SUF); 1302 else 1303 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_SUF); 1304 1305 return true; 1306} 1307 1308static void 1309nvc0_set_shader_images(struct pipe_context *pipe, 1310 enum pipe_shader_type shader, 1311 unsigned start, unsigned nr, 1312 unsigned unbind_num_trailing_slots, 1313 const struct pipe_image_view *images) 1314{ 1315 const unsigned s = nvc0_shader_stage(shader); 1316 1317 nvc0_bind_images_range(nvc0_context(pipe), s, start + nr, 1318 unbind_num_trailing_slots, NULL); 1319 1320 if (!nvc0_bind_images_range(nvc0_context(pipe), s, start, nr, images)) 1321 return; 1322 1323 if (s == 5) 1324 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SURFACES; 1325 else 1326 nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_SURFACES; 1327} 1328 1329static bool 1330nvc0_bind_buffers_range(struct nvc0_context *nvc0, const unsigned t, 1331 unsigned start, unsigned nr, 1332 const struct pipe_shader_buffer *pbuffers) 1333{ 1334 const unsigned end = start + nr; 1335 unsigned mask = 0; 1336 unsigned i; 1337 1338 assert(t < 6); 1339 1340 if (pbuffers) { 1341 for (i = start; i < end; ++i) { 1342 struct pipe_shader_buffer *buf = &nvc0->buffers[t][i]; 1343 const unsigned p = i - start; 1344 if (buf->buffer == pbuffers[p].buffer && 1345 buf->buffer_offset == pbuffers[p].buffer_offset && 1346 buf->buffer_size == pbuffers[p].buffer_size) 1347 continue; 1348 1349 mask |= (1 << i); 1350 if (pbuffers[p].buffer) 1351 nvc0->buffers_valid[t] |= (1 << i); 1352 else 1353 nvc0->buffers_valid[t] &= ~(1 << i); 1354 buf->buffer_offset = pbuffers[p].buffer_offset; 1355 buf->buffer_size = pbuffers[p].buffer_size; 1356 pipe_resource_reference(&buf->buffer, pbuffers[p].buffer); 1357 } 1358 if (!mask) 1359 return false; 1360 } else { 1361 mask = ((1 << nr) - 1) << start; 1362 if (!(nvc0->buffers_valid[t] & mask)) 1363 return false; 1364 for (i = start; i < end; ++i) 1365 pipe_resource_reference(&nvc0->buffers[t][i].buffer, NULL); 1366 nvc0->buffers_valid[t] &= ~mask; 1367 } 1368 nvc0->buffers_dirty[t] |= mask; 1369 1370 if (t == 5) 1371 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_BUF); 1372 else 1373 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_BUF); 1374 1375 return true; 1376} 1377 1378static void 1379nvc0_set_shader_buffers(struct pipe_context *pipe, 1380 enum pipe_shader_type shader, 1381 unsigned start, unsigned nr, 1382 const struct pipe_shader_buffer *buffers, 1383 unsigned writable_bitmask) 1384{ 1385 const unsigned s = nvc0_shader_stage(shader); 1386 if (!nvc0_bind_buffers_range(nvc0_context(pipe), s, start, nr, buffers)) 1387 return; 1388 1389 if (s == 5) 1390 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_BUFFERS; 1391 else 1392 nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_BUFFERS; 1393} 1394 1395static inline void 1396nvc0_set_global_handle(uint32_t *phandle, struct pipe_resource *res) 1397{ 1398 struct nv04_resource *buf = nv04_resource(res); 1399 if (buf) { 1400 uint64_t address = buf->address + *phandle; 1401 /* even though it's a pointer to uint32_t that's fine */ 1402 memcpy(phandle, &address, 8); 1403 } else { 1404 *phandle = 0; 1405 } 1406} 1407 1408static void 1409nvc0_set_global_bindings(struct pipe_context *pipe, 1410 unsigned start, unsigned nr, 1411 struct pipe_resource **resources, 1412 uint32_t **handles) 1413{ 1414 struct nvc0_context *nvc0 = nvc0_context(pipe); 1415 struct pipe_resource **ptr; 1416 unsigned i; 1417 const unsigned end = start + nr; 1418 1419 if (!nr) 1420 return; 1421 1422 if (nvc0->global_residents.size <= (end * sizeof(struct pipe_resource *))) { 1423 const unsigned old_size = nvc0->global_residents.size; 1424 if (util_dynarray_resize(&nvc0->global_residents, struct pipe_resource *, end)) { 1425 memset((uint8_t *)nvc0->global_residents.data + old_size, 0, 1426 nvc0->global_residents.size - old_size); 1427 } else { 1428 NOUVEAU_ERR("Could not resize global residents array\n"); 1429 return; 1430 } 1431 } 1432 1433 if (resources) { 1434 ptr = util_dynarray_element( 1435 &nvc0->global_residents, struct pipe_resource *, start); 1436 for (i = 0; i < nr; ++i) { 1437 pipe_resource_reference(&ptr[i], resources[i]); 1438 nvc0_set_global_handle(handles[i], resources[i]); 1439 } 1440 } else { 1441 ptr = util_dynarray_element( 1442 &nvc0->global_residents, struct pipe_resource *, start); 1443 for (i = 0; i < nr; ++i) 1444 pipe_resource_reference(&ptr[i], NULL); 1445 } 1446 1447 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_GLOBAL); 1448 1449 nvc0->dirty_cp |= NVC0_NEW_CP_GLOBALS; 1450} 1451 1452void 1453nvc0_init_state_functions(struct nvc0_context *nvc0) 1454{ 1455 struct pipe_context *pipe = &nvc0->base.pipe; 1456 1457 pipe->create_blend_state = nvc0_blend_state_create; 1458 pipe->bind_blend_state = nvc0_blend_state_bind; 1459 pipe->delete_blend_state = nvc0_blend_state_delete; 1460 1461 pipe->create_rasterizer_state = nvc0_rasterizer_state_create; 1462 pipe->bind_rasterizer_state = nvc0_rasterizer_state_bind; 1463 pipe->delete_rasterizer_state = nvc0_rasterizer_state_delete; 1464 1465 pipe->create_depth_stencil_alpha_state = nvc0_zsa_state_create; 1466 pipe->bind_depth_stencil_alpha_state = nvc0_zsa_state_bind; 1467 pipe->delete_depth_stencil_alpha_state = nvc0_zsa_state_delete; 1468 1469 pipe->create_sampler_state = nv50_sampler_state_create; 1470 pipe->delete_sampler_state = nvc0_sampler_state_delete; 1471 pipe->bind_sampler_states = nvc0_bind_sampler_states; 1472 1473 pipe->create_sampler_view = nvc0_create_sampler_view; 1474 pipe->sampler_view_destroy = nvc0_sampler_view_destroy; 1475 pipe->set_sampler_views = nvc0_set_sampler_views; 1476 1477 pipe->create_vs_state = nvc0_vp_state_create; 1478 pipe->create_fs_state = nvc0_fp_state_create; 1479 pipe->create_gs_state = nvc0_gp_state_create; 1480 pipe->create_tcs_state = nvc0_tcp_state_create; 1481 pipe->create_tes_state = nvc0_tep_state_create; 1482 pipe->bind_vs_state = nvc0_vp_state_bind; 1483 pipe->bind_fs_state = nvc0_fp_state_bind; 1484 pipe->bind_gs_state = nvc0_gp_state_bind; 1485 pipe->bind_tcs_state = nvc0_tcp_state_bind; 1486 pipe->bind_tes_state = nvc0_tep_state_bind; 1487 pipe->delete_vs_state = nvc0_sp_state_delete; 1488 pipe->delete_fs_state = nvc0_sp_state_delete; 1489 pipe->delete_gs_state = nvc0_sp_state_delete; 1490 pipe->delete_tcs_state = nvc0_sp_state_delete; 1491 pipe->delete_tes_state = nvc0_sp_state_delete; 1492 1493 pipe->create_compute_state = nvc0_cp_state_create; 1494 pipe->bind_compute_state = nvc0_cp_state_bind; 1495 pipe->delete_compute_state = nvc0_sp_state_delete; 1496 1497 pipe->set_blend_color = nvc0_set_blend_color; 1498 pipe->set_stencil_ref = nvc0_set_stencil_ref; 1499 pipe->set_clip_state = nvc0_set_clip_state; 1500 pipe->set_sample_mask = nvc0_set_sample_mask; 1501 pipe->set_min_samples = nvc0_set_min_samples; 1502 pipe->set_constant_buffer = nvc0_set_constant_buffer; 1503 pipe->set_framebuffer_state = nvc0_set_framebuffer_state; 1504 pipe->set_sample_locations = nvc0_set_sample_locations; 1505 pipe->set_polygon_stipple = nvc0_set_polygon_stipple; 1506 pipe->set_scissor_states = nvc0_set_scissor_states; 1507 pipe->set_viewport_states = nvc0_set_viewport_states; 1508 pipe->set_window_rectangles = nvc0_set_window_rectangles; 1509 pipe->set_tess_state = nvc0_set_tess_state; 1510 pipe->set_patch_vertices = nvc0_set_patch_vertices; 1511 1512 pipe->create_vertex_elements_state = nvc0_vertex_state_create; 1513 pipe->delete_vertex_elements_state = nvc0_vertex_state_delete; 1514 pipe->bind_vertex_elements_state = nvc0_vertex_state_bind; 1515 1516 pipe->set_vertex_buffers = nvc0_set_vertex_buffers; 1517 1518 pipe->create_stream_output_target = nvc0_so_target_create; 1519 pipe->stream_output_target_destroy = nvc0_so_target_destroy; 1520 pipe->set_stream_output_targets = nvc0_set_transform_feedback_targets; 1521 1522 pipe->set_global_binding = nvc0_set_global_bindings; 1523 pipe->set_compute_resources = nvc0_set_compute_resources; 1524 pipe->set_shader_images = nvc0_set_shader_images; 1525 pipe->set_shader_buffers = nvc0_set_shader_buffers; 1526 1527 nvc0->sample_mask = ~0; 1528 nvc0->min_samples = 1; 1529 nvc0->default_tess_outer[0] = 1530 nvc0->default_tess_outer[1] = 1531 nvc0->default_tess_outer[2] = 1532 nvc0->default_tess_outer[3] = 1.0; 1533 nvc0->default_tess_inner[0] = 1534 nvc0->default_tess_inner[1] = 1.0; 1535} 1536