1/* 2 * Copyright 2010 Christoph Bumiller 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23#include "pipe/p_context.h" 24#include "pipe/p_state.h" 25#include "util/u_draw.h" 26#include "util/u_inlines.h" 27#include "util/u_prim.h" 28#include "util/format/u_format.h" 29#include "translate/translate.h" 30 31#include "nv50/nv50_context.h" 32#include "nv50/nv50_query_hw.h" 33#include "nv50/nv50_resource.h" 34 35#include "nv50/nv50_3d.xml.h" 36 37void 38nv50_vertex_state_delete(struct pipe_context *pipe, 39 void *hwcso) 40{ 41 struct nv50_vertex_stateobj *so = hwcso; 42 43 if (so->translate) 44 so->translate->release(so->translate); 45 FREE(hwcso); 46} 47 48void * 49nv50_vertex_state_create(struct pipe_context *pipe, 50 unsigned num_elements, 51 const struct pipe_vertex_element *elements) 52{ 53 struct nv50_vertex_stateobj *so; 54 struct translate_key transkey; 55 unsigned i; 56 57 so = MALLOC(sizeof(*so) + 58 num_elements * sizeof(struct nv50_vertex_element)); 59 if (!so) 60 return NULL; 61 so->num_elements = num_elements; 62 so->instance_elts = 0; 63 so->instance_bufs = 0; 64 so->need_conversion = false; 65 66 memset(so->vb_access_size, 0, sizeof(so->vb_access_size)); 67 68 for (i = 0; i < PIPE_MAX_ATTRIBS; ++i) 69 so->min_instance_div[i] = 0xffffffff; 70 71 transkey.nr_elements = 0; 72 transkey.output_stride = 0; 73 74 for (i = 0; i < num_elements; ++i) { 75 const struct pipe_vertex_element *ve = &elements[i]; 76 const unsigned vbi = ve->vertex_buffer_index; 77 unsigned size; 78 enum pipe_format fmt = ve->src_format; 79 80 so->element[i].pipe = elements[i]; 81 so->element[i].state = nv50_vertex_format[fmt].vtx; 82 83 if (!so->element[i].state) { 84 switch (util_format_get_nr_components(fmt)) { 85 case 1: fmt = PIPE_FORMAT_R32_FLOAT; break; 86 case 2: fmt = PIPE_FORMAT_R32G32_FLOAT; break; 87 case 3: fmt = PIPE_FORMAT_R32G32B32_FLOAT; break; 88 case 4: fmt = PIPE_FORMAT_R32G32B32A32_FLOAT; break; 89 default: 90 assert(0); 91 FREE(so); 92 return NULL; 93 } 94 so->element[i].state = nv50_vertex_format[fmt].vtx; 95 so->need_conversion = true; 96 util_debug_message(&nouveau_context(pipe)->debug, FALLBACK, 97 "Converting vertex element %d, no hw format %s", 98 i, util_format_name(ve->src_format)); 99 } 100 so->element[i].state |= i; 101 102 size = util_format_get_blocksize(fmt); 103 if (so->vb_access_size[vbi] < (ve->src_offset + size)) 104 so->vb_access_size[vbi] = ve->src_offset + size; 105 106 if (1) { 107 unsigned j = transkey.nr_elements++; 108 109 transkey.element[j].type = TRANSLATE_ELEMENT_NORMAL; 110 transkey.element[j].input_format = ve->src_format; 111 transkey.element[j].input_buffer = vbi; 112 transkey.element[j].input_offset = ve->src_offset; 113 transkey.element[j].instance_divisor = ve->instance_divisor; 114 115 transkey.element[j].output_format = fmt; 116 transkey.element[j].output_offset = transkey.output_stride; 117 transkey.output_stride += (util_format_get_stride(fmt, 1) + 3) & ~3; 118 119 if (unlikely(ve->instance_divisor)) { 120 so->instance_elts |= 1 << i; 121 so->instance_bufs |= 1 << vbi; 122 if (ve->instance_divisor < so->min_instance_div[vbi]) 123 so->min_instance_div[vbi] = ve->instance_divisor; 124 } 125 } 126 } 127 128 so->translate = translate_create(&transkey); 129 so->vertex_size = transkey.output_stride / 4; 130 so->packet_vertex_limit = NV04_PFIFO_MAX_PACKET_LEN / 131 MAX2(so->vertex_size, 1); 132 133 return so; 134} 135 136#define NV50_3D_VERTEX_ATTRIB_INACTIVE \ 137 NV50_3D_VERTEX_ARRAY_ATTRIB_TYPE_FLOAT | \ 138 NV50_3D_VERTEX_ARRAY_ATTRIB_FORMAT_32_32_32_32 | \ 139 NV50_3D_VERTEX_ARRAY_ATTRIB_CONST 140 141static void 142nv50_emit_vtxattr(struct nv50_context *nv50, struct pipe_vertex_buffer *vb, 143 struct pipe_vertex_element *ve, unsigned attr) 144{ 145 struct nouveau_pushbuf *push = nv50->base.pushbuf; 146 const void *data = (const uint8_t *)vb->buffer.user + ve->src_offset; 147 float v[4]; 148 const unsigned nc = util_format_get_nr_components(ve->src_format); 149 150 assert(vb->is_user_buffer); 151 152 util_format_unpack_rgba(ve->src_format, v, data, 1); 153 154 switch (nc) { 155 case 4: 156 BEGIN_NV04(push, NV50_3D(VTX_ATTR_4F_X(attr)), 4); 157 PUSH_DATAf(push, v[0]); 158 PUSH_DATAf(push, v[1]); 159 PUSH_DATAf(push, v[2]); 160 PUSH_DATAf(push, v[3]); 161 break; 162 case 3: 163 BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(attr)), 3); 164 PUSH_DATAf(push, v[0]); 165 PUSH_DATAf(push, v[1]); 166 PUSH_DATAf(push, v[2]); 167 break; 168 case 2: 169 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(attr)), 2); 170 PUSH_DATAf(push, v[0]); 171 PUSH_DATAf(push, v[1]); 172 break; 173 case 1: 174 if (attr == nv50->vertprog->vp.edgeflag) { 175 BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1); 176 PUSH_DATA (push, v[0] ? 1 : 0); 177 } 178 BEGIN_NV04(push, NV50_3D(VTX_ATTR_1F(attr)), 1); 179 PUSH_DATAf(push, v[0]); 180 break; 181 default: 182 assert(0); 183 break; 184 } 185} 186 187static inline void 188nv50_user_vbuf_range(struct nv50_context *nv50, unsigned vbi, 189 uint32_t *base, uint32_t *size) 190{ 191 assert(vbi < PIPE_MAX_ATTRIBS); 192 if (unlikely(nv50->vertex->instance_bufs & (1 << vbi))) { 193 const uint32_t div = nv50->vertex->min_instance_div[vbi]; 194 *base = nv50->instance_off * nv50->vtxbuf[vbi].stride; 195 *size = (nv50->instance_max / div) * nv50->vtxbuf[vbi].stride + 196 nv50->vertex->vb_access_size[vbi]; 197 } else { 198 /* NOTE: if there are user buffers, we *must* have index bounds */ 199 assert(nv50->vb_elt_limit != ~0); 200 *base = nv50->vb_elt_first * nv50->vtxbuf[vbi].stride; 201 *size = nv50->vb_elt_limit * nv50->vtxbuf[vbi].stride + 202 nv50->vertex->vb_access_size[vbi]; 203 } 204} 205 206static void 207nv50_upload_user_buffers(struct nv50_context *nv50, 208 uint64_t addrs[], uint32_t limits[]) 209{ 210 unsigned b; 211 212 assert(nv50->num_vtxbufs <= PIPE_MAX_ATTRIBS); 213 for (b = 0; b < nv50->num_vtxbufs; ++b) { 214 struct nouveau_bo *bo; 215 const struct pipe_vertex_buffer *vb = &nv50->vtxbuf[b]; 216 uint32_t base, size; 217 218 if (!(nv50->vbo_user & (1 << b)) || !vb->stride) 219 continue; 220 nv50_user_vbuf_range(nv50, b, &base, &size); 221 222 limits[b] = base + size - 1; 223 addrs[b] = nouveau_scratch_data(&nv50->base, vb->buffer.user, base, size, 224 &bo); 225 if (addrs[b]) 226 BCTX_REFN_bo(nv50->bufctx_3d, 3D_VERTEX_TMP, NOUVEAU_BO_GART | 227 NOUVEAU_BO_RD, bo); 228 } 229 nv50->base.vbo_dirty = true; 230} 231 232static void 233nv50_update_user_vbufs(struct nv50_context *nv50) 234{ 235 uint64_t address[PIPE_MAX_ATTRIBS]; 236 struct nouveau_pushbuf *push = nv50->base.pushbuf; 237 unsigned i; 238 uint32_t written = 0; 239 240 for (i = 0; i < nv50->vertex->num_elements; ++i) { 241 struct pipe_vertex_element *ve = &nv50->vertex->element[i].pipe; 242 const unsigned b = ve->vertex_buffer_index; 243 struct pipe_vertex_buffer *vb; 244 uint32_t base, size; 245 246 assert(b < PIPE_MAX_ATTRIBS); 247 vb = &nv50->vtxbuf[b]; 248 249 if (!(nv50->vbo_user & (1 << b))) 250 continue; 251 252 if (!vb->stride) { 253 nv50_emit_vtxattr(nv50, vb, ve, i); 254 continue; 255 } 256 nv50_user_vbuf_range(nv50, b, &base, &size); 257 258 if (!(written & (1 << b))) { 259 struct nouveau_bo *bo; 260 const uint32_t bo_flags = NOUVEAU_BO_GART | NOUVEAU_BO_RD; 261 written |= 1 << b; 262 address[b] = nouveau_scratch_data(&nv50->base, vb->buffer.user, 263 base, size, &bo); 264 if (address[b]) 265 BCTX_REFN_bo(nv50->bufctx_3d, 3D_VERTEX_TMP, bo_flags, bo); 266 } 267 268 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2); 269 PUSH_DATAh(push, address[b] + base + size - 1); 270 PUSH_DATA (push, address[b] + base + size - 1); 271 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_START_HIGH(i)), 2); 272 PUSH_DATAh(push, address[b] + ve->src_offset); 273 PUSH_DATA (push, address[b] + ve->src_offset); 274 } 275 nv50->base.vbo_dirty = true; 276} 277 278static inline void 279nv50_release_user_vbufs(struct nv50_context *nv50) 280{ 281 if (nv50->vbo_user) { 282 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_VERTEX_TMP); 283 nouveau_scratch_done(&nv50->base); 284 } 285} 286 287void 288nv50_vertex_arrays_validate(struct nv50_context *nv50) 289{ 290 uint64_t addrs[PIPE_MAX_ATTRIBS]; 291 uint32_t limits[PIPE_MAX_ATTRIBS]; 292 struct nouveau_pushbuf *push = nv50->base.pushbuf; 293 struct nv50_vertex_stateobj *vertex = nv50->vertex; 294 struct pipe_vertex_buffer *vb; 295 struct nv50_vertex_element *ve; 296 uint32_t mask; 297 uint32_t refd = 0; 298 unsigned i; 299 const unsigned n = MAX2(vertex->num_elements, nv50->state.num_vtxelts); 300 301 if (unlikely(vertex->need_conversion)) 302 nv50->vbo_fifo = ~0; 303 else 304 if (nv50->vbo_user & ~nv50->vbo_constant) 305 nv50->vbo_fifo = nv50->vbo_push_hint ? ~0 : 0; 306 else 307 nv50->vbo_fifo = 0; 308 309 if (!nv50->vbo_fifo) { 310 /* if vertex buffer was written by GPU - flush VBO cache */ 311 assert(nv50->num_vtxbufs <= PIPE_MAX_ATTRIBS); 312 for (i = 0; i < nv50->num_vtxbufs; ++i) { 313 struct nv04_resource *buf = nv04_resource(nv50->vtxbuf[i].buffer.resource); 314 if (!nv50->vtxbuf[i].is_user_buffer && 315 buf && buf->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) { 316 buf->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING; 317 nv50->base.vbo_dirty = true; 318 } 319 } 320 } 321 322 /* update vertex format state */ 323 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_ATTRIB(0)), n); 324 if (nv50->vbo_fifo) { 325 nv50->state.num_vtxelts = vertex->num_elements; 326 for (i = 0; i < vertex->num_elements; ++i) 327 PUSH_DATA (push, vertex->element[i].state); 328 for (; i < n; ++i) 329 PUSH_DATA (push, NV50_3D_VERTEX_ATTRIB_INACTIVE); 330 for (i = 0; i < n; ++i) { 331 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1); 332 PUSH_DATA (push, 0); 333 } 334 return; 335 } 336 for (i = 0; i < vertex->num_elements; ++i) { 337 const unsigned b = vertex->element[i].pipe.vertex_buffer_index; 338 339 assert(b < PIPE_MAX_ATTRIBS); 340 ve = &vertex->element[i]; 341 vb = &nv50->vtxbuf[b]; 342 343 if (likely(vb->stride) || !(nv50->vbo_user & (1 << b))) 344 PUSH_DATA(push, ve->state); 345 else 346 PUSH_DATA(push, ve->state | NV50_3D_VERTEX_ARRAY_ATTRIB_CONST); 347 } 348 for (; i < n; ++i) 349 PUSH_DATA(push, NV50_3D_VERTEX_ATTRIB_INACTIVE); 350 351 /* update per-instance enables */ 352 mask = vertex->instance_elts ^ nv50->state.instance_elts; 353 while (mask) { 354 const int i = ffs(mask) - 1; 355 mask &= ~(1 << i); 356 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 1); 357 PUSH_DATA (push, (vertex->instance_elts >> i) & 1); 358 } 359 nv50->state.instance_elts = vertex->instance_elts; 360 361 if (nv50->vbo_user & ~nv50->vbo_constant) 362 nv50_upload_user_buffers(nv50, addrs, limits); 363 364 /* update buffers and set constant attributes */ 365 for (i = 0; i < vertex->num_elements; ++i) { 366 uint64_t address, limit; 367 const unsigned b = vertex->element[i].pipe.vertex_buffer_index; 368 369 assert(b < PIPE_MAX_ATTRIBS); 370 ve = &vertex->element[i]; 371 vb = &nv50->vtxbuf[b]; 372 373 if (unlikely(nv50->vbo_constant & (1 << b))) { 374 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1); 375 PUSH_DATA (push, 0); 376 nv50_emit_vtxattr(nv50, vb, &ve->pipe, i); 377 continue; 378 } else 379 if (nv50->vbo_user & (1 << b)) { 380 address = addrs[b] + ve->pipe.src_offset; 381 limit = addrs[b] + limits[b]; 382 } else 383 if (!vb->buffer.resource) { 384 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1); 385 PUSH_DATA (push, 0); 386 continue; 387 } else { 388 struct nv04_resource *buf = nv04_resource(vb->buffer.resource); 389 if (!(refd & (1 << b))) { 390 refd |= 1 << b; 391 BCTX_REFN(nv50->bufctx_3d, 3D_VERTEX, buf, RD); 392 } 393 address = buf->address + vb->buffer_offset + ve->pipe.src_offset; 394 limit = buf->address + buf->base.width0 - 1; 395 } 396 397 if (unlikely(ve->pipe.instance_divisor)) { 398 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 4); 399 PUSH_DATA (push, NV50_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride); 400 PUSH_DATAh(push, address); 401 PUSH_DATA (push, address); 402 PUSH_DATA (push, ve->pipe.instance_divisor); 403 } else { 404 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 3); 405 PUSH_DATA (push, NV50_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride); 406 PUSH_DATAh(push, address); 407 PUSH_DATA (push, address); 408 } 409 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2); 410 PUSH_DATAh(push, limit); 411 PUSH_DATA (push, limit); 412 } 413 for (; i < nv50->state.num_vtxelts; ++i) { 414 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1); 415 PUSH_DATA (push, 0); 416 } 417 nv50->state.num_vtxelts = vertex->num_elements; 418} 419 420#define NV50_PRIM_GL_CASE(n) \ 421 case PIPE_PRIM_##n: return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_##n 422 423static inline unsigned 424nv50_prim_gl(unsigned prim) 425{ 426 switch (prim) { 427 NV50_PRIM_GL_CASE(POINTS); 428 NV50_PRIM_GL_CASE(LINES); 429 NV50_PRIM_GL_CASE(LINE_LOOP); 430 NV50_PRIM_GL_CASE(LINE_STRIP); 431 NV50_PRIM_GL_CASE(TRIANGLES); 432 NV50_PRIM_GL_CASE(TRIANGLE_STRIP); 433 NV50_PRIM_GL_CASE(TRIANGLE_FAN); 434 NV50_PRIM_GL_CASE(QUADS); 435 NV50_PRIM_GL_CASE(QUAD_STRIP); 436 NV50_PRIM_GL_CASE(POLYGON); 437 NV50_PRIM_GL_CASE(LINES_ADJACENCY); 438 NV50_PRIM_GL_CASE(LINE_STRIP_ADJACENCY); 439 NV50_PRIM_GL_CASE(TRIANGLES_ADJACENCY); 440 NV50_PRIM_GL_CASE(TRIANGLE_STRIP_ADJACENCY); 441 default: 442 return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_POINTS; 443 break; 444 } 445} 446 447/* For pre-nva0 transform feedback. */ 448static const uint8_t nv50_pipe_prim_to_prim_size[PIPE_PRIM_MAX + 1] = 449{ 450 [PIPE_PRIM_POINTS] = 1, 451 [PIPE_PRIM_LINES] = 2, 452 [PIPE_PRIM_LINE_LOOP] = 2, 453 [PIPE_PRIM_LINE_STRIP] = 2, 454 [PIPE_PRIM_TRIANGLES] = 3, 455 [PIPE_PRIM_TRIANGLE_STRIP] = 3, 456 [PIPE_PRIM_TRIANGLE_FAN] = 3, 457 [PIPE_PRIM_QUADS] = 3, 458 [PIPE_PRIM_QUAD_STRIP] = 3, 459 [PIPE_PRIM_POLYGON] = 3, 460 [PIPE_PRIM_LINES_ADJACENCY] = 2, 461 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = 2, 462 [PIPE_PRIM_TRIANGLES_ADJACENCY] = 3, 463 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = 3 464}; 465 466static void 467nv50_draw_arrays(struct nv50_context *nv50, 468 unsigned mode, unsigned start, unsigned count, 469 unsigned instance_count) 470{ 471 struct nouveau_pushbuf *push = nv50->base.pushbuf; 472 unsigned prim; 473 474 if (nv50->state.index_bias) { 475 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1); 476 PUSH_DATA (push, 0); 477 if (nv50->screen->base.class_3d >= NV84_3D_CLASS) { 478 BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1); 479 PUSH_DATA (push, 0); 480 } 481 nv50->state.index_bias = 0; 482 } 483 484 prim = nv50_prim_gl(mode); 485 486 while (instance_count--) { 487 BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1); 488 PUSH_DATA (push, prim); 489 BEGIN_NV04(push, NV50_3D(VERTEX_BUFFER_FIRST), 2); 490 PUSH_DATA (push, start); 491 PUSH_DATA (push, count); 492 BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1); 493 PUSH_DATA (push, 0); 494 495 prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT; 496 } 497} 498 499static void 500nv50_draw_elements_inline_u08(struct nouveau_pushbuf *push, const uint8_t *map, 501 unsigned start, unsigned count) 502{ 503 map += start; 504 505 if (count & 3) { 506 unsigned i; 507 BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U32), count & 3); 508 for (i = 0; i < (count & 3); ++i) 509 PUSH_DATA(push, *map++); 510 count &= ~3; 511 } 512 while (count) { 513 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 4) / 4; 514 515 BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U8), nr); 516 for (i = 0; i < nr; ++i) { 517 PUSH_DATA(push, 518 (map[3] << 24) | (map[2] << 16) | (map[1] << 8) | map[0]); 519 map += 4; 520 } 521 count -= nr * 4; 522 } 523} 524 525static void 526nv50_draw_elements_inline_u16(struct nouveau_pushbuf *push, const uint16_t *map, 527 unsigned start, unsigned count) 528{ 529 map += start; 530 531 if (count & 1) { 532 count &= ~1; 533 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U32), 1); 534 PUSH_DATA (push, *map++); 535 } 536 while (count) { 537 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2; 538 539 BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U16), nr); 540 for (i = 0; i < nr; ++i) { 541 PUSH_DATA(push, (map[1] << 16) | map[0]); 542 map += 2; 543 } 544 count -= nr * 2; 545 } 546} 547 548static void 549nv50_draw_elements_inline_u32(struct nouveau_pushbuf *push, const uint32_t *map, 550 unsigned start, unsigned count) 551{ 552 map += start; 553 554 while (count) { 555 const unsigned nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN); 556 557 BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U32), nr); 558 PUSH_DATAp(push, map, nr); 559 560 map += nr; 561 count -= nr; 562 } 563} 564 565static void 566nv50_draw_elements_inline_u32_short(struct nouveau_pushbuf *push, 567 const uint32_t *map, 568 unsigned start, unsigned count) 569{ 570 map += start; 571 572 if (count & 1) { 573 count--; 574 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U32), 1); 575 PUSH_DATA (push, *map++); 576 } 577 while (count) { 578 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2; 579 580 BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U16), nr); 581 for (i = 0; i < nr; ++i) { 582 PUSH_DATA(push, (map[1] << 16) | map[0]); 583 map += 2; 584 } 585 count -= nr * 2; 586 } 587} 588 589static void 590nv50_draw_elements(struct nv50_context *nv50, bool shorten, 591 const struct pipe_draw_info *info, 592 unsigned mode, unsigned start, unsigned count, 593 unsigned instance_count, int32_t index_bias, 594 unsigned index_size) 595{ 596 struct nouveau_pushbuf *push = nv50->base.pushbuf; 597 unsigned prim; 598 599 prim = nv50_prim_gl(mode); 600 601 if (index_bias != nv50->state.index_bias) { 602 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1); 603 PUSH_DATA (push, index_bias); 604 if (nv50->screen->base.class_3d >= NV84_3D_CLASS) { 605 BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1); 606 PUSH_DATA (push, index_bias); 607 } 608 nv50->state.index_bias = index_bias; 609 } 610 611 if (!info->has_user_indices) { 612 struct nv04_resource *buf = nv04_resource(info->index.resource); 613 unsigned pb_start; 614 unsigned pb_bytes; 615 const unsigned base = buf->offset & ~3; 616 617 start += (buf->offset & 3) >> (index_size >> 1); 618 619 assert(nouveau_resource_mapped_by_gpu(info->index.resource)); 620 621 /* This shouldn't have to be here. The going theory is that the buffer 622 * is being filled in by PGRAPH, and it's not done yet by the time it 623 * gets submitted to PFIFO, which in turn starts immediately prefetching 624 * the not-yet-written data. Ideally this wait would only happen on 625 * pushbuf submit, but it's probably not a big performance difference. 626 */ 627 if (buf->fence_wr && !nouveau_fence_signalled(buf->fence_wr)) 628 nouveau_fence_wait(buf->fence_wr, &nv50->base.debug); 629 630 while (instance_count--) { 631 BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1); 632 PUSH_DATA (push, prim); 633 634 nouveau_pushbuf_space(push, 16, 0, 1); 635 PUSH_REFN(push, buf->bo, NOUVEAU_BO_RD | buf->domain); 636 637 switch (index_size) { 638 case 4: 639 BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U32), count); 640 nouveau_pushbuf_data(push, buf->bo, base + start * 4, count * 4); 641 break; 642 case 2: 643 pb_start = (start & ~1) * 2; 644 pb_bytes = ((start + count + 1) & ~1) * 2 - pb_start; 645 646 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U16_SETUP), 1); 647 PUSH_DATA (push, (start << 31) | count); 648 BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U16), pb_bytes / 4); 649 nouveau_pushbuf_data(push, buf->bo, base + pb_start, pb_bytes); 650 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U16_SETUP), 1); 651 PUSH_DATA (push, 0); 652 break; 653 default: 654 assert(index_size == 1); 655 pb_start = start & ~3; 656 pb_bytes = ((start + count + 3) & ~3) - pb_start; 657 658 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U8_SETUP), 1); 659 PUSH_DATA (push, (start << 30) | count); 660 BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U8), pb_bytes / 4); 661 nouveau_pushbuf_data(push, buf->bo, base + pb_start, pb_bytes); 662 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U8_SETUP), 1); 663 PUSH_DATA (push, 0); 664 break; 665 } 666 BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1); 667 PUSH_DATA (push, 0); 668 669 prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT; 670 } 671 } else { 672 const void *data = info->index.user; 673 674 while (instance_count--) { 675 BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1); 676 PUSH_DATA (push, prim); 677 switch (index_size) { 678 case 1: 679 nv50_draw_elements_inline_u08(push, data, start, count); 680 break; 681 case 2: 682 nv50_draw_elements_inline_u16(push, data, start, count); 683 break; 684 case 4: 685 if (shorten) 686 nv50_draw_elements_inline_u32_short(push, data, start, count); 687 else 688 nv50_draw_elements_inline_u32(push, data, start, count); 689 break; 690 default: 691 assert(0); 692 return; 693 } 694 BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1); 695 PUSH_DATA (push, 0); 696 697 prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT; 698 } 699 } 700 NOUVEAU_DRV_STAT(&nv50->screen->base, draw_calls_indexed, 1); 701} 702 703static void 704nva0_draw_stream_output(struct nv50_context *nv50, 705 const struct pipe_draw_info *info, 706 const struct pipe_draw_indirect_info *indirect) 707{ 708 struct nouveau_pushbuf *push = nv50->base.pushbuf; 709 struct nv50_so_target *so = nv50_so_target(indirect->count_from_stream_output); 710 struct nv04_resource *res = nv04_resource(so->pipe.buffer); 711 unsigned num_instances = info->instance_count; 712 unsigned mode = nv50_prim_gl(info->mode); 713 714 if (unlikely(nv50->screen->base.class_3d < NVA0_3D_CLASS)) { 715 /* A proper implementation without waiting doesn't seem possible, 716 * so don't bother. 717 */ 718 NOUVEAU_ERR("draw_stream_output not supported on pre-NVA0 cards\n"); 719 return; 720 } 721 722 if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) { 723 res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING; 724 PUSH_SPACE(push, 4); 725 BEGIN_NV04(push, SUBC_3D(NV50_GRAPH_SERIALIZE), 1); 726 PUSH_DATA (push, 0); 727 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FLUSH), 1); 728 PUSH_DATA (push, 0); 729 } 730 731 assert(num_instances); 732 do { 733 PUSH_SPACE(push, 8); 734 BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1); 735 PUSH_DATA (push, mode); 736 BEGIN_NV04(push, NVA0_3D(DRAW_TFB_BASE), 1); 737 PUSH_DATA (push, 0); 738 BEGIN_NV04(push, NVA0_3D(DRAW_TFB_STRIDE), 1); 739 PUSH_DATA (push, so->stride); 740 nv50_hw_query_pushbuf_submit(push, NVA0_3D_DRAW_TFB_BYTES, 741 nv50_query(so->pq), 0x4); 742 BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1); 743 PUSH_DATA (push, 0); 744 745 mode |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT; 746 } while (--num_instances); 747} 748 749static void 750nv50_draw_vbo_kick_notify(struct nouveau_pushbuf *chan) 751{ 752 struct nv50_screen *screen = chan->user_priv; 753 754 nouveau_fence_update(&screen->base, true); 755 756 nv50_bufctx_fence(screen->cur_ctx->bufctx_3d, true); 757} 758 759void 760nv50_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info, 761 unsigned drawid_offset, 762 const struct pipe_draw_indirect_info *indirect, 763 const struct pipe_draw_start_count_bias *draws, 764 unsigned num_draws) 765{ 766 if (num_draws > 1) { 767 util_draw_multi(pipe, info, drawid_offset, indirect, draws, num_draws); 768 return; 769 } 770 771 if (!indirect && (!draws[0].count || !info->instance_count)) 772 return; 773 774 /* We don't actually support indirect draws, so add a fallback for ES 3.1's 775 * benefit. 776 */ 777 if (indirect && indirect->buffer) { 778 util_draw_indirect(pipe, info, indirect); 779 return; 780 } 781 782 struct nv50_context *nv50 = nv50_context(pipe); 783 struct nouveau_pushbuf *push = nv50->base.pushbuf; 784 bool tex_dirty = false; 785 int s; 786 787 if (info->index_size && !info->has_user_indices) 788 BCTX_REFN(nv50->bufctx_3d, 3D_INDEX, nv04_resource(info->index.resource), RD); 789 790 /* NOTE: caller must ensure that (min_index + index_bias) is >= 0 */ 791 if (info->index_bounds_valid) { 792 nv50->vb_elt_first = info->min_index + (info->index_size ? draws->index_bias : 0); 793 nv50->vb_elt_limit = info->max_index - info->min_index; 794 } else { 795 nv50->vb_elt_first = 0; 796 nv50->vb_elt_limit = ~0; 797 } 798 nv50->instance_off = info->start_instance; 799 nv50->instance_max = info->instance_count - 1; 800 801 /* For picking only a few vertices from a large user buffer, push is better, 802 * if index count is larger and we expect repeated vertices, suggest upload. 803 */ 804 nv50->vbo_push_hint = /* the 64 is heuristic */ 805 !(info->index_size && ((nv50->vb_elt_limit + 64) < draws[0].count)); 806 807 if (nv50->vbo_user && !(nv50->dirty_3d & (NV50_NEW_3D_ARRAYS | NV50_NEW_3D_VERTEX))) { 808 if (!!nv50->vbo_fifo != nv50->vbo_push_hint) 809 nv50->dirty_3d |= NV50_NEW_3D_ARRAYS; 810 else 811 if (!nv50->vbo_fifo) 812 nv50_update_user_vbufs(nv50); 813 } 814 815 if (unlikely(nv50->num_so_targets && !nv50->gmtyprog)) 816 nv50->state.prim_size = nv50_pipe_prim_to_prim_size[info->mode]; 817 818 nv50_state_validate_3d(nv50, ~0); 819 820 push->kick_notify = nv50_draw_vbo_kick_notify; 821 822 for (s = 0; s < NV50_MAX_3D_SHADER_STAGES && !nv50->cb_dirty; ++s) { 823 if (nv50->constbuf_coherent[s]) 824 nv50->cb_dirty = true; 825 } 826 827 /* If there are any coherent constbufs, flush the cache */ 828 if (nv50->cb_dirty) { 829 BEGIN_NV04(push, NV50_3D(CODE_CB_FLUSH), 1); 830 PUSH_DATA (push, 0); 831 nv50->cb_dirty = false; 832 } 833 834 for (s = 0; s < NV50_MAX_3D_SHADER_STAGES && !tex_dirty; ++s) { 835 if (nv50->textures_coherent[s]) 836 tex_dirty = true; 837 } 838 839 if (tex_dirty) { 840 BEGIN_NV04(push, NV50_3D(TEX_CACHE_CTL), 1); 841 PUSH_DATA (push, 0x20); 842 } 843 844 if (nv50->screen->base.class_3d >= NVA0_3D_CLASS && 845 nv50->seamless_cube_map != nv50->state.seamless_cube_map) { 846 nv50->state.seamless_cube_map = nv50->seamless_cube_map; 847 BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1); 848 PUSH_DATA (push, nv50->seamless_cube_map ? NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP : 0); 849 } 850 851 if (nv50->vertprog->mul_zero_wins != nv50->state.mul_zero_wins) { 852 nv50->state.mul_zero_wins = nv50->vertprog->mul_zero_wins; 853 BEGIN_NV04(push, NV50_3D(UNK1690), 1); 854 PUSH_DATA (push, 0x00010000 * !!nv50->state.mul_zero_wins); 855 } 856 857 /* Make starting/pausing streamout work pre-NVA0 enough for ES3.0. This 858 * means counting vertices in a vertex shader when it has so outputs. 859 */ 860 if (nv50->screen->base.class_3d < NVA0_3D_CLASS && 861 nv50->vertprog->pipe.stream_output.num_outputs) { 862 for (int i = 0; i < nv50->num_so_targets; i++) { 863 nv50->so_used[i] += info->instance_count * 864 u_stream_outputs_for_vertices(info->mode, draws[0].count) * 865 nv50->vertprog->pipe.stream_output.stride[i] * 4; 866 } 867 } 868 869 if (nv50->vbo_fifo) { 870 nv50_push_vbo(nv50, info, indirect, &draws[0]); 871 goto cleanup; 872 } 873 874 if (nv50->state.instance_base != info->start_instance) { 875 nv50->state.instance_base = info->start_instance; 876 /* NOTE: this does not affect the shader input, should it ? */ 877 BEGIN_NV04(push, NV50_3D(VB_INSTANCE_BASE), 1); 878 PUSH_DATA (push, info->start_instance); 879 } 880 881 nv50->base.vbo_dirty |= !!nv50->vtxbufs_coherent; 882 883 if (nv50->base.vbo_dirty) { 884 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FLUSH), 1); 885 PUSH_DATA (push, 0); 886 nv50->base.vbo_dirty = false; 887 } 888 889 if (info->index_size) { 890 bool shorten = info->index_bounds_valid && info->max_index <= 65535; 891 892 if (info->primitive_restart != nv50->state.prim_restart) { 893 if (info->primitive_restart) { 894 BEGIN_NV04(push, NV50_3D(PRIM_RESTART_ENABLE), 2); 895 PUSH_DATA (push, 1); 896 PUSH_DATA (push, info->restart_index); 897 898 if (info->restart_index > 65535) 899 shorten = false; 900 } else { 901 BEGIN_NV04(push, NV50_3D(PRIM_RESTART_ENABLE), 1); 902 PUSH_DATA (push, 0); 903 } 904 nv50->state.prim_restart = info->primitive_restart; 905 } else 906 if (info->primitive_restart) { 907 BEGIN_NV04(push, NV50_3D(PRIM_RESTART_INDEX), 1); 908 PUSH_DATA (push, info->restart_index); 909 910 if (info->restart_index > 65535) 911 shorten = false; 912 } 913 914 nv50_draw_elements(nv50, shorten, info, 915 info->mode, draws[0].start, draws[0].count, 916 info->instance_count, draws->index_bias, info->index_size); 917 } else 918 if (unlikely(indirect && indirect->count_from_stream_output)) { 919 nva0_draw_stream_output(nv50, info, indirect); 920 } else { 921 nv50_draw_arrays(nv50, 922 info->mode, draws[0].start, draws[0].count, 923 info->instance_count); 924 } 925 926cleanup: 927 push->kick_notify = nv50_default_kick_notify; 928 929 nv50_release_user_vbufs(nv50); 930 931 nouveau_pushbuf_bufctx(push, NULL); 932 933 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_INDEX); 934} 935