1/* 2 * Copyright © 2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 * DEALINGS IN THE SOFTWARE. 21 */ 22 23#include <stdio.h> 24#include <errno.h> 25#include "pipe/p_defines.h" 26#include "pipe/p_state.h" 27#include "pipe/p_context.h" 28#include "pipe/p_screen.h" 29#include "util/u_inlines.h" 30#include "util/format/u_format.h" 31#include "util/u_upload_mgr.h" 32#include "util/ralloc.h" 33#include "iris_context.h" 34#include "iris_resource.h" 35#include "iris_screen.h" 36#include "intel/compiler/brw_compiler.h" 37 38static bool 39iris_is_color_fast_clear_compatible(struct iris_context *ice, 40 enum isl_format format, 41 const union isl_color_value color) 42{ 43 struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER]; 44 const struct intel_device_info *devinfo = &batch->screen->devinfo; 45 46 if (isl_format_has_int_channel(format)) { 47 perf_debug(&ice->dbg, "Integer fast clear not enabled for %s\n", 48 isl_format_get_name(format)); 49 return false; 50 } 51 52 for (int i = 0; i < 4; i++) { 53 if (!isl_format_has_color_component(format, i)) { 54 continue; 55 } 56 57 if (devinfo->ver < 9 && 58 color.f32[i] != 0.0f && color.f32[i] != 1.0f) { 59 return false; 60 } 61 } 62 63 return true; 64} 65 66static bool 67can_fast_clear_color(struct iris_context *ice, 68 struct pipe_resource *p_res, 69 unsigned level, 70 const struct pipe_box *box, 71 bool render_condition_enabled, 72 enum isl_format render_format, 73 union isl_color_value color) 74{ 75 struct iris_resource *res = (void *) p_res; 76 77 if (INTEL_DEBUG(DEBUG_NO_FAST_CLEAR)) 78 return false; 79 80 if (!isl_aux_usage_has_fast_clears(res->aux.usage)) 81 return false; 82 83 /* Check for partial clear */ 84 if (box->x > 0 || box->y > 0 || 85 box->width < u_minify(p_res->width0, level) || 86 box->height < u_minify(p_res->height0, level)) { 87 return false; 88 } 89 90 /* Avoid conditional fast clears to maintain correct tracking of the aux 91 * state (see iris_resource_finish_write for more info). Note that partial 92 * fast clears (if they existed) would not pose a problem with conditional 93 * rendering. 94 */ 95 if (render_condition_enabled && 96 ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT) { 97 return false; 98 } 99 100 /* Disable sRGB fast-clears for non-0/1 color values. For texturing and 101 * draw calls, HW expects the clear color to be in two different color 102 * spaces after sRGB fast-clears - sRGB in the former and linear in the 103 * latter. By limiting the allowable values to 0/1, both color space 104 * requirements are satisfied. 105 */ 106 if (isl_format_is_srgb(render_format) && 107 !isl_color_value_is_zero_one(color, render_format)) { 108 return false; 109 } 110 111 /* We store clear colors as floats or uints as needed. If there are 112 * texture views in play, the formats will not properly be respected 113 * during resolves because the resolve operations only know about the 114 * resource and not the renderbuffer. 115 */ 116 if (!iris_render_formats_color_compatible(render_format, res->surf.format, 117 color, false)) { 118 return false; 119 } 120 121 if (!iris_is_color_fast_clear_compatible(ice, res->surf.format, color)) 122 return false; 123 124 /* The RENDER_SURFACE_STATE page for TGL says: 125 * 126 * For an 8 bpp surface with NUM_MULTISAMPLES = 1, Surface Width not 127 * multiple of 64 pixels and more than 1 mip level in the view, Fast Clear 128 * is not supported when AUX_CCS_E is set in this field. 129 * 130 * The granularity of a fast-clear is one CCS element. For an 8 bpp primary 131 * surface, this maps to 32px x 4rows. Due to the surface layout parameters, 132 * if LOD0's width isn't a multiple of 64px, LOD1 and LOD2+ will share CCS 133 * elements. Assuming LOD2 exists, don't fast-clear any level above LOD0 134 * to avoid stomping on other LODs. 135 */ 136 if (level > 0 && util_format_get_blocksizebits(p_res->format) == 8 && 137 res->aux.usage == ISL_AUX_USAGE_GFX12_CCS_E && p_res->width0 % 64) { 138 return false; 139 } 140 141 return true; 142} 143 144static union isl_color_value 145convert_clear_color(enum pipe_format format, 146 const union pipe_color_union *color) 147{ 148 uint32_t pixel[4]; 149 util_format_pack_rgba(format, pixel, color, 1); 150 151 union isl_color_value converted_color; 152 util_format_unpack_rgba(format, &converted_color, pixel, 1); 153 154 /* The converted clear color has channels that are: 155 * - clamped 156 * - quantized 157 * - filled with 0/1 if missing from the format 158 * - swizzled for luminance and intensity formats 159 */ 160 return converted_color; 161} 162 163static void 164fast_clear_color(struct iris_context *ice, 165 struct iris_resource *res, 166 unsigned level, 167 const struct pipe_box *box, 168 union isl_color_value color) 169{ 170 struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER]; 171 const struct intel_device_info *devinfo = &batch->screen->devinfo; 172 struct pipe_resource *p_res = (void *) res; 173 174 bool color_changed = res->aux.clear_color_unknown || 175 memcmp(&res->aux.clear_color, &color, sizeof(color)) != 0; 176 177 if (color_changed) { 178 /* If we are clearing to a new clear value, we need to resolve fast 179 * clears from other levels/layers first, since we can't have different 180 * levels/layers with different fast clear colors. 181 */ 182 for (unsigned res_lvl = 0; res_lvl < res->surf.levels; res_lvl++) { 183 const unsigned level_layers = 184 iris_get_num_logical_layers(res, res_lvl); 185 for (unsigned layer = 0; layer < level_layers; layer++) { 186 if (res_lvl == level && 187 layer >= box->z && 188 layer < box->z + box->depth) { 189 /* We're going to clear this layer anyway. Leave it alone. */ 190 continue; 191 } 192 193 enum isl_aux_state aux_state = 194 iris_resource_get_aux_state(res, res_lvl, layer); 195 196 if (aux_state != ISL_AUX_STATE_CLEAR && 197 aux_state != ISL_AUX_STATE_PARTIAL_CLEAR && 198 aux_state != ISL_AUX_STATE_COMPRESSED_CLEAR) { 199 /* This slice doesn't have any fast-cleared bits. */ 200 continue; 201 } 202 203 /* If we got here, then the level may have fast-clear bits that use 204 * the old clear value. We need to do a color resolve to get rid 205 * of their use of the clear color before we can change it. 206 * Fortunately, few applications ever change their clear color at 207 * different levels/layers, so this shouldn't happen often. 208 */ 209 iris_resource_prepare_access(ice, res, 210 res_lvl, 1, layer, 1, 211 res->aux.usage, 212 false); 213 if (res->aux.clear_color_unknown) { 214 perf_debug(&ice->dbg, 215 "Resolving resource (%p) level %d, layer %d: color changing from " 216 "(unknown) to (%0.2f, %0.2f, %0.2f, %0.2f)\n", 217 res, res_lvl, layer, 218 color.f32[0], color.f32[1], color.f32[2], color.f32[3]); 219 } else { 220 perf_debug(&ice->dbg, 221 "Resolving resource (%p) level %d, layer %d: color changing from " 222 "(%0.2f, %0.2f, %0.2f, %0.2f) to " 223 "(%0.2f, %0.2f, %0.2f, %0.2f)\n", 224 res, res_lvl, layer, 225 res->aux.clear_color.f32[0], 226 res->aux.clear_color.f32[1], 227 res->aux.clear_color.f32[2], 228 res->aux.clear_color.f32[3], 229 color.f32[0], color.f32[1], color.f32[2], color.f32[3]); 230 } 231 } 232 } 233 } 234 235 iris_resource_set_clear_color(ice, res, color); 236 237 /* If the buffer is already in ISL_AUX_STATE_CLEAR, and the color hasn't 238 * changed, the clear is redundant and can be skipped. 239 */ 240 const enum isl_aux_state aux_state = 241 iris_resource_get_aux_state(res, level, box->z); 242 if (!color_changed && box->depth == 1 && aux_state == ISL_AUX_STATE_CLEAR) 243 return; 244 245 /* Ivybridge PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)": 246 * 247 * "Any transition from any value in {Clear, Render, Resolve} to a 248 * different value in {Clear, Render, Resolve} requires end of pipe 249 * synchronization." 250 * 251 * In other words, fast clear ops are not properly synchronized with 252 * other drawing. We need to use a PIPE_CONTROL to ensure that the 253 * contents of the previous draw hit the render target before we resolve 254 * and again afterwards to ensure that the resolve is complete before we 255 * do any more regular drawing. 256 */ 257 iris_emit_end_of_pipe_sync(batch, 258 "fast clear: pre-flush", 259 PIPE_CONTROL_RENDER_TARGET_FLUSH | 260 PIPE_CONTROL_TILE_CACHE_FLUSH | 261 (devinfo->verx10 == 120 ? 262 PIPE_CONTROL_DEPTH_STALL : 0) | 263 (devinfo->verx10 == 125 ? 264 PIPE_CONTROL_FLUSH_HDC | 265 PIPE_CONTROL_DATA_CACHE_FLUSH : 0) | 266 PIPE_CONTROL_PSS_STALL_SYNC); 267 268 iris_batch_sync_region_start(batch); 269 270 /* If we reach this point, we need to fast clear to change the state to 271 * ISL_AUX_STATE_CLEAR, or to update the fast clear color (or both). 272 */ 273 enum blorp_batch_flags blorp_flags = 0; 274 blorp_flags |= color_changed ? 0 : BLORP_BATCH_NO_UPDATE_CLEAR_COLOR; 275 276 struct blorp_batch blorp_batch; 277 blorp_batch_init(&ice->blorp, &blorp_batch, batch, blorp_flags); 278 279 struct blorp_surf surf; 280 iris_blorp_surf_for_resource(&batch->screen->isl_dev, &surf, 281 p_res, res->aux.usage, level, true); 282 283 blorp_fast_clear(&blorp_batch, &surf, res->surf.format, 284 ISL_SWIZZLE_IDENTITY, 285 level, box->z, box->depth, 286 box->x, box->y, box->x + box->width, 287 box->y + box->height); 288 blorp_batch_finish(&blorp_batch); 289 iris_emit_end_of_pipe_sync(batch, 290 "fast clear: post flush", 291 PIPE_CONTROL_RENDER_TARGET_FLUSH | 292 (devinfo->verx10 == 120 ? 293 PIPE_CONTROL_TILE_CACHE_FLUSH | 294 PIPE_CONTROL_DEPTH_STALL : 0) | 295 PIPE_CONTROL_PSS_STALL_SYNC); 296 iris_batch_sync_region_end(batch); 297 298 iris_resource_set_aux_state(ice, res, level, box->z, 299 box->depth, ISL_AUX_STATE_CLEAR); 300 ice->state.dirty |= IRIS_DIRTY_RENDER_BUFFER; 301 ice->state.stage_dirty |= IRIS_ALL_STAGE_DIRTY_BINDINGS; 302 return; 303} 304 305static void 306clear_color(struct iris_context *ice, 307 struct pipe_resource *p_res, 308 unsigned level, 309 const struct pipe_box *box, 310 bool render_condition_enabled, 311 enum isl_format format, 312 struct isl_swizzle swizzle, 313 union isl_color_value color) 314{ 315 struct iris_resource *res = (void *) p_res; 316 317 struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER]; 318 const struct intel_device_info *devinfo = &batch->screen->devinfo; 319 enum blorp_batch_flags blorp_flags = iris_blorp_flags_for_batch(batch); 320 321 if (render_condition_enabled) { 322 if (ice->state.predicate == IRIS_PREDICATE_STATE_DONT_RENDER) 323 return; 324 325 if (ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT) 326 blorp_flags |= BLORP_BATCH_PREDICATE_ENABLE; 327 } 328 329 if (p_res->target == PIPE_BUFFER) 330 util_range_add(&res->base.b, &res->valid_buffer_range, box->x, box->x + box->width); 331 332 iris_batch_maybe_flush(batch, 1500); 333 334 bool can_fast_clear = can_fast_clear_color(ice, p_res, level, box, 335 render_condition_enabled, 336 format, color); 337 if (can_fast_clear) { 338 fast_clear_color(ice, res, level, box, color); 339 return; 340 } 341 342 enum isl_aux_usage aux_usage = 343 iris_resource_render_aux_usage(ice, res, level, format, false); 344 345 iris_resource_prepare_render(ice, res, level, box->z, box->depth, 346 aux_usage); 347 iris_emit_buffer_barrier_for(batch, res->bo, IRIS_DOMAIN_RENDER_WRITE); 348 349 struct blorp_surf surf; 350 iris_blorp_surf_for_resource(&batch->screen->isl_dev, &surf, 351 p_res, aux_usage, level, true); 352 353 iris_batch_sync_region_start(batch); 354 355 struct blorp_batch blorp_batch; 356 blorp_batch_init(&ice->blorp, &blorp_batch, batch, blorp_flags); 357 358 if (!isl_format_supports_rendering(devinfo, format) && 359 isl_format_is_rgbx(format)) 360 format = isl_format_rgbx_to_rgba(format); 361 362 blorp_clear(&blorp_batch, &surf, format, swizzle, 363 level, box->z, box->depth, box->x, box->y, 364 box->x + box->width, box->y + box->height, 365 color, 0 /* color_write_disable */); 366 367 blorp_batch_finish(&blorp_batch); 368 iris_batch_sync_region_end(batch); 369 370 iris_dirty_for_history(ice, res); 371 372 iris_resource_finish_render(ice, res, level, 373 box->z, box->depth, aux_usage); 374} 375 376static bool 377can_fast_clear_depth(struct iris_context *ice, 378 struct iris_resource *res, 379 unsigned level, 380 const struct pipe_box *box, 381 bool render_condition_enabled, 382 float depth) 383{ 384 struct pipe_resource *p_res = (void *) res; 385 struct pipe_context *ctx = (void *) ice; 386 struct iris_screen *screen = (void *) ctx->screen; 387 const struct intel_device_info *devinfo = &screen->devinfo; 388 389 if (INTEL_DEBUG(DEBUG_NO_FAST_CLEAR)) 390 return false; 391 392 /* Check for partial clears */ 393 if (box->x > 0 || box->y > 0 || 394 box->width < u_minify(p_res->width0, level) || 395 box->height < u_minify(p_res->height0, level)) { 396 return false; 397 } 398 399 /* Avoid conditional fast clears to maintain correct tracking of the aux 400 * state (see iris_resource_finish_write for more info). Note that partial 401 * fast clears would not pose a problem with conditional rendering. 402 */ 403 if (render_condition_enabled && 404 ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT) { 405 return false; 406 } 407 408 if (!iris_resource_level_has_hiz(res, level)) 409 return false; 410 411 if (!blorp_can_hiz_clear_depth(devinfo, &res->surf, res->aux.usage, 412 level, box->z, box->x, box->y, 413 box->x + box->width, 414 box->y + box->height)) { 415 return false; 416 } 417 418 return true; 419} 420 421static void 422fast_clear_depth(struct iris_context *ice, 423 struct iris_resource *res, 424 unsigned level, 425 const struct pipe_box *box, 426 float depth) 427{ 428 struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER]; 429 430 bool update_clear_depth = false; 431 432 /* If we're clearing to a new clear value, then we need to resolve any clear 433 * flags out of the HiZ buffer into the real depth buffer. 434 */ 435 if (res->aux.clear_color_unknown || res->aux.clear_color.f32[0] != depth) { 436 for (unsigned res_level = 0; res_level < res->surf.levels; res_level++) { 437 const unsigned level_layers = 438 iris_get_num_logical_layers(res, res_level); 439 for (unsigned layer = 0; layer < level_layers; layer++) { 440 if (res_level == level && 441 layer >= box->z && 442 layer < box->z + box->depth) { 443 /* We're going to clear this layer anyway. Leave it alone. */ 444 continue; 445 } 446 447 enum isl_aux_state aux_state = 448 iris_resource_get_aux_state(res, res_level, layer); 449 450 if (aux_state != ISL_AUX_STATE_CLEAR && 451 aux_state != ISL_AUX_STATE_COMPRESSED_CLEAR) { 452 /* This slice doesn't have any fast-cleared bits. */ 453 continue; 454 } 455 456 /* If we got here, then the level may have fast-clear bits that 457 * use the old clear value. We need to do a depth resolve to get 458 * rid of their use of the clear value before we can change it. 459 * Fortunately, few applications ever change their depth clear 460 * value so this shouldn't happen often. 461 */ 462 iris_hiz_exec(ice, batch, res, res_level, layer, 1, 463 ISL_AUX_OP_FULL_RESOLVE, false); 464 iris_resource_set_aux_state(ice, res, res_level, layer, 1, 465 ISL_AUX_STATE_RESOLVED); 466 } 467 } 468 const union isl_color_value clear_value = { .f32 = {depth, } }; 469 iris_resource_set_clear_color(ice, res, clear_value); 470 update_clear_depth = true; 471 } 472 473 if (res->aux.usage == ISL_AUX_USAGE_HIZ_CCS_WT) { 474 /* From Bspec 47010 (Depth Buffer Clear): 475 * 476 * Since the fast clear cycles to CCS are not cached in TileCache, 477 * any previous depth buffer writes to overlapping pixels must be 478 * flushed out of TileCache before a succeeding Depth Buffer Clear. 479 * This restriction only applies to Depth Buffer with write-thru 480 * enabled, since fast clears to CCS only occur for write-thru mode. 481 * 482 * There may have been a write to this depth buffer. Flush it from the 483 * tile cache just in case. 484 */ 485 iris_emit_pipe_control_flush(batch, "hiz_ccs_wt: before fast clear", 486 PIPE_CONTROL_DEPTH_CACHE_FLUSH | 487 PIPE_CONTROL_TILE_CACHE_FLUSH); 488 } 489 490 for (unsigned l = 0; l < box->depth; l++) { 491 enum isl_aux_state aux_state = 492 iris_resource_get_aux_state(res, level, box->z + l); 493 if (update_clear_depth || aux_state != ISL_AUX_STATE_CLEAR) { 494 if (aux_state == ISL_AUX_STATE_CLEAR) { 495 perf_debug(&ice->dbg, "Performing HiZ clear just to update the " 496 "depth clear value\n"); 497 } 498 iris_hiz_exec(ice, batch, res, level, 499 box->z + l, 1, ISL_AUX_OP_FAST_CLEAR, 500 update_clear_depth); 501 } 502 } 503 504 iris_resource_set_aux_state(ice, res, level, box->z, box->depth, 505 ISL_AUX_STATE_CLEAR); 506 ice->state.dirty |= IRIS_DIRTY_DEPTH_BUFFER; 507 ice->state.stage_dirty |= IRIS_ALL_STAGE_DIRTY_BINDINGS; 508} 509 510static void 511clear_depth_stencil(struct iris_context *ice, 512 struct pipe_resource *p_res, 513 unsigned level, 514 const struct pipe_box *box, 515 bool render_condition_enabled, 516 bool clear_depth, 517 bool clear_stencil, 518 float depth, 519 uint8_t stencil) 520{ 521 struct iris_resource *res = (void *) p_res; 522 523 struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER]; 524 enum blorp_batch_flags blorp_flags = 0; 525 526 if (render_condition_enabled) { 527 if (ice->state.predicate == IRIS_PREDICATE_STATE_DONT_RENDER) 528 return; 529 530 if (ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT) 531 blorp_flags |= BLORP_BATCH_PREDICATE_ENABLE; 532 } 533 534 iris_batch_maybe_flush(batch, 1500); 535 536 struct iris_resource *z_res; 537 struct iris_resource *stencil_res; 538 struct blorp_surf z_surf; 539 struct blorp_surf stencil_surf; 540 541 iris_get_depth_stencil_resources(p_res, &z_res, &stencil_res); 542 if (z_res && clear_depth && 543 can_fast_clear_depth(ice, z_res, level, box, render_condition_enabled, 544 depth)) { 545 fast_clear_depth(ice, z_res, level, box, depth); 546 iris_dirty_for_history(ice, res); 547 clear_depth = false; 548 z_res = false; 549 } 550 551 /* At this point, we might have fast cleared the depth buffer. So if there's 552 * no stencil clear pending, return early. 553 */ 554 if (!(clear_depth || (clear_stencil && stencil_res))) { 555 return; 556 } 557 558 if (clear_depth && z_res) { 559 const enum isl_aux_usage aux_usage = 560 iris_resource_render_aux_usage(ice, z_res, level, z_res->surf.format, 561 false); 562 iris_resource_prepare_render(ice, z_res, level, box->z, box->depth, 563 aux_usage); 564 iris_emit_buffer_barrier_for(batch, z_res->bo, IRIS_DOMAIN_DEPTH_WRITE); 565 iris_blorp_surf_for_resource(&batch->screen->isl_dev, &z_surf, 566 &z_res->base.b, aux_usage, level, true); 567 } 568 569 uint8_t stencil_mask = clear_stencil && stencil_res ? 0xff : 0; 570 if (stencil_mask) { 571 iris_resource_prepare_access(ice, stencil_res, level, 1, box->z, 572 box->depth, stencil_res->aux.usage, false); 573 iris_emit_buffer_barrier_for(batch, stencil_res->bo, 574 IRIS_DOMAIN_DEPTH_WRITE); 575 iris_blorp_surf_for_resource(&batch->screen->isl_dev, 576 &stencil_surf, &stencil_res->base.b, 577 stencil_res->aux.usage, level, true); 578 } 579 580 iris_batch_sync_region_start(batch); 581 582 struct blorp_batch blorp_batch; 583 blorp_batch_init(&ice->blorp, &blorp_batch, batch, blorp_flags); 584 585 blorp_clear_depth_stencil(&blorp_batch, &z_surf, &stencil_surf, 586 level, box->z, box->depth, 587 box->x, box->y, 588 box->x + box->width, 589 box->y + box->height, 590 clear_depth && z_res, depth, 591 stencil_mask, stencil); 592 593 blorp_batch_finish(&blorp_batch); 594 iris_batch_sync_region_end(batch); 595 596 iris_dirty_for_history(ice, res); 597 598 if (clear_depth && z_res) { 599 iris_resource_finish_render(ice, z_res, level, box->z, box->depth, 600 z_surf.aux_usage); 601 } 602 603 if (stencil_mask) { 604 iris_resource_finish_write(ice, stencil_res, level, box->z, box->depth, 605 stencil_res->aux.usage); 606 } 607} 608 609/** 610 * The pipe->clear() driver hook. 611 * 612 * This clears buffers attached to the current draw framebuffer. 613 */ 614static void 615iris_clear(struct pipe_context *ctx, 616 unsigned buffers, 617 const struct pipe_scissor_state *scissor_state, 618 const union pipe_color_union *p_color, 619 double depth, 620 unsigned stencil) 621{ 622 struct iris_context *ice = (void *) ctx; 623 struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer; 624 625 assert(buffers != 0); 626 627 struct pipe_box box = { 628 .width = cso_fb->width, 629 .height = cso_fb->height, 630 }; 631 632 if (scissor_state) { 633 box.x = scissor_state->minx; 634 box.y = scissor_state->miny; 635 box.width = MIN2(box.width, scissor_state->maxx - scissor_state->minx); 636 box.height = MIN2(box.height, scissor_state->maxy - scissor_state->miny); 637 } 638 639 if (buffers & PIPE_CLEAR_DEPTHSTENCIL) { 640 struct pipe_surface *psurf = cso_fb->zsbuf; 641 642 box.depth = psurf->u.tex.last_layer - psurf->u.tex.first_layer + 1; 643 box.z = psurf->u.tex.first_layer, 644 clear_depth_stencil(ice, psurf->texture, psurf->u.tex.level, &box, true, 645 buffers & PIPE_CLEAR_DEPTH, 646 buffers & PIPE_CLEAR_STENCIL, 647 depth, stencil); 648 } 649 650 if (buffers & PIPE_CLEAR_COLOR) { 651 for (unsigned i = 0; i < cso_fb->nr_cbufs; i++) { 652 if (buffers & (PIPE_CLEAR_COLOR0 << i)) { 653 struct pipe_surface *psurf = cso_fb->cbufs[i]; 654 struct iris_surface *isurf = (void *) psurf; 655 box.depth = psurf->u.tex.last_layer - psurf->u.tex.first_layer + 1, 656 box.z = psurf->u.tex.first_layer, 657 658 clear_color(ice, psurf->texture, psurf->u.tex.level, &box, 659 true, isurf->view.format, isurf->view.swizzle, 660 convert_clear_color(psurf->format, p_color)); 661 } 662 } 663 } 664} 665 666/** 667 * The pipe->clear_texture() driver hook. 668 * 669 * This clears the given texture resource. 670 */ 671static void 672iris_clear_texture(struct pipe_context *ctx, 673 struct pipe_resource *p_res, 674 unsigned level, 675 const struct pipe_box *box, 676 const void *data) 677{ 678 struct iris_context *ice = (void *) ctx; 679 struct iris_screen *screen = (void *) ctx->screen; 680 const struct intel_device_info *devinfo = &screen->devinfo; 681 682 if (util_format_is_depth_or_stencil(p_res->format)) { 683 const struct util_format_unpack_description *unpack = 684 util_format_unpack_description(p_res->format); 685 686 float depth = 0.0; 687 uint8_t stencil = 0; 688 689 if (unpack->unpack_z_float) 690 util_format_unpack_z_float(p_res->format, &depth, data, 1); 691 692 if (unpack->unpack_s_8uint) 693 util_format_unpack_s_8uint(p_res->format, &stencil, data, 1); 694 695 clear_depth_stencil(ice, p_res, level, box, true, true, true, 696 depth, stencil); 697 } else { 698 union isl_color_value color; 699 struct iris_resource *res = (void *) p_res; 700 enum isl_format format = res->surf.format; 701 702 if (!isl_format_supports_rendering(devinfo, format)) { 703 const struct isl_format_layout *fmtl = isl_format_get_layout(format); 704 // XXX: actually just get_copy_format_for_bpb from BLORP 705 // XXX: don't cut and paste this 706 switch (fmtl->bpb) { 707 case 8: format = ISL_FORMAT_R8_UINT; break; 708 case 16: format = ISL_FORMAT_R8G8_UINT; break; 709 case 24: format = ISL_FORMAT_R8G8B8_UINT; break; 710 case 32: format = ISL_FORMAT_R8G8B8A8_UINT; break; 711 case 48: format = ISL_FORMAT_R16G16B16_UINT; break; 712 case 64: format = ISL_FORMAT_R16G16B16A16_UINT; break; 713 case 96: format = ISL_FORMAT_R32G32B32_UINT; break; 714 case 128: format = ISL_FORMAT_R32G32B32A32_UINT; break; 715 default: 716 unreachable("Unknown format bpb"); 717 } 718 719 /* No aux surfaces for non-renderable surfaces */ 720 assert(res->aux.usage == ISL_AUX_USAGE_NONE); 721 } 722 723 isl_color_value_unpack(&color, format, data); 724 725 clear_color(ice, p_res, level, box, true, format, 726 ISL_SWIZZLE_IDENTITY, color); 727 } 728} 729 730/** 731 * The pipe->clear_render_target() driver hook. 732 * 733 * This clears the given render target surface. 734 */ 735static void 736iris_clear_render_target(struct pipe_context *ctx, 737 struct pipe_surface *psurf, 738 const union pipe_color_union *p_color, 739 unsigned dst_x, unsigned dst_y, 740 unsigned width, unsigned height, 741 bool render_condition_enabled) 742{ 743 struct iris_context *ice = (void *) ctx; 744 struct iris_surface *isurf = (void *) psurf; 745 struct pipe_box box = { 746 .x = dst_x, 747 .y = dst_y, 748 .z = psurf->u.tex.first_layer, 749 .width = width, 750 .height = height, 751 .depth = psurf->u.tex.last_layer - psurf->u.tex.first_layer + 1 752 }; 753 754 clear_color(ice, psurf->texture, psurf->u.tex.level, &box, 755 render_condition_enabled, 756 isurf->view.format, isurf->view.swizzle, 757 convert_clear_color(psurf->format, p_color)); 758} 759 760/** 761 * The pipe->clear_depth_stencil() driver hook. 762 * 763 * This clears the given depth/stencil surface. 764 */ 765static void 766iris_clear_depth_stencil(struct pipe_context *ctx, 767 struct pipe_surface *psurf, 768 unsigned flags, 769 double depth, 770 unsigned stencil, 771 unsigned dst_x, unsigned dst_y, 772 unsigned width, unsigned height, 773 bool render_condition_enabled) 774{ 775 struct iris_context *ice = (void *) ctx; 776 struct pipe_box box = { 777 .x = dst_x, 778 .y = dst_y, 779 .z = psurf->u.tex.first_layer, 780 .width = width, 781 .height = height, 782 .depth = psurf->u.tex.last_layer - psurf->u.tex.first_layer + 1 783 }; 784 785 assert(util_format_is_depth_or_stencil(psurf->texture->format)); 786 787 clear_depth_stencil(ice, psurf->texture, psurf->u.tex.level, &box, 788 render_condition_enabled, 789 flags & PIPE_CLEAR_DEPTH, flags & PIPE_CLEAR_STENCIL, 790 depth, stencil); 791} 792 793void 794iris_init_clear_functions(struct pipe_context *ctx) 795{ 796 ctx->clear = iris_clear; 797 ctx->clear_texture = iris_clear_texture; 798 ctx->clear_render_target = iris_clear_render_target; 799 ctx->clear_depth_stencil = iris_clear_depth_stencil; 800} 801