1/**************************************************************************
2 *
3 * Copyright 2003 VMware, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28#include "pipe/p_context.h"
29#include "pipe/p_state.h"
30
31#include "i915_context.h"
32#include "i915_reg.h"
33#include "i915_resource.h"
34#include "i915_state.h"
35#include "i915_state_inlines.h"
36
37/*
38 * A note about min_lod & max_lod.
39 *
40 * There is a circular dependancy between the sampler state
41 * and the map state to be submitted to hw.
42 *
43 * Two condition must be meet:
44 * min_lod =< max_lod == true
45 * max_lod =< last_level == true
46 *
47 *
48 * This is all fine and dandy if it were for the fact that max_lod
49 * is set on the map state instead of the sampler state. That is
50 * the max_lod we submit on map is:
51 * max_lod = MIN2(last_level, max_lod);
52 *
53 * So we need to update the map state when we change samplers and
54 * we need to change the sampler state when map state is changed.
55 * The first part is done by calling update_texture in update_samplers
56 * and the second part is done else where in code tracking the state
57 * changes.
58 */
59
60/***********************************************************************
61 * Samplers
62 */
63
64/**
65 * Compute i915 texture sampling state.
66 *
67 * Recalculate all state from scratch.  Perhaps not the most
68 * efficient, but this has gotten complex enough that we need
69 * something which is understandable and reliable.
70 * \param state  returns the 3 words of compute state
71 */
72static void
73update_sampler(struct i915_context *i915, uint32_t unit,
74               const struct i915_sampler_state *sampler,
75               const struct i915_texture *tex, unsigned state[3])
76{
77   const struct pipe_resource *pt = &tex->b;
78   unsigned minlod, lastlod;
79
80   state[0] = sampler->state[0];
81   state[1] = sampler->state[1];
82   state[2] = sampler->state[2];
83
84   if (pt->format == PIPE_FORMAT_UYVY || pt->format == PIPE_FORMAT_YUYV)
85      state[0] |= SS2_COLORSPACE_CONVERSION;
86
87   if (util_format_is_srgb(pt->format)) {
88      state[0] |= SS2_REVERSE_GAMMA_ENABLE;
89   }
90
91   /* There is no HW support for 1D textures, so we just make them 2D textures
92    * with h=1, but that means we need to make the Y coordinate not contribute
93    * to bringing any border color in.  Clearing it sets it to WRAP.
94    */
95   if (pt->target == PIPE_TEXTURE_1D) {
96      state[1] &= ~SS3_TCY_ADDR_MODE_MASK;
97   }
98
99   /* The GLES2 spec says textures are incomplete (return 0,0,0,1) if:
100    *
101    * "A cube map sampler is called, any of the corresponding texture images are
102    * non-power-of-two images, and either the texture wrap mode is not
103    * CLAMP_TO_EDGE, or the minification filter is neither NEAREST nor LINEAR."
104    *
105    * while the i915 spec says:
106    *
107    * "When using cube map texture coordinates, only TEXCOORDMODE_CLAMP and *
108    *  TEXCOORDMODE_CUBE settings are valid, and each TC component must have the
109    *  same Address Control mode. TEXCOORDMODE_CUBE is not valid unless the
110    *  width and height of the cube map are power-of-2."
111    *
112    * We don't expose support for the seamless cube map extension, so always use
113    * edge clamping.
114    */
115   if (pt->target == PIPE_TEXTURE_CUBE) {
116      state[1] &= ~(SS3_TCX_ADDR_MODE_MASK | SS3_TCY_ADDR_MODE_MASK |
117                    SS3_TCZ_ADDR_MODE_MASK);
118      state[1] |= (TEXCOORDMODE_CLAMP_EDGE << SS3_TCX_ADDR_MODE_SHIFT);
119      state[1] |= (TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT);
120      state[1] |= (TEXCOORDMODE_CLAMP_EDGE << SS3_TCZ_ADDR_MODE_SHIFT);
121   }
122
123   /* 3D textures don't seem to respect the border color.
124    * Fallback if there's ever a danger that they might refer to
125    * it.
126    *
127    * Effectively this means fallback on 3D clamp or
128    * clamp_to_border.
129    *
130    * XXX: Check if this is true on i945.
131    * XXX: Check if this bug got fixed in release silicon.
132    */
133#if 0
134   {
135      const unsigned ws = sampler->templ->wrap_s;
136      const unsigned wt = sampler->templ->wrap_t;
137      const unsigned wr = sampler->templ->wrap_r;
138      if (pt->target == PIPE_TEXTURE_3D &&
139          (sampler->templ->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
140           sampler->templ->mag_img_filter != PIPE_TEX_FILTER_NEAREST) &&
141          (ws == PIPE_TEX_WRAP_CLAMP ||
142           wt == PIPE_TEX_WRAP_CLAMP ||
143           wr == PIPE_TEX_WRAP_CLAMP ||
144           ws == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
145           wt == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
146           wr == PIPE_TEX_WRAP_CLAMP_TO_BORDER)) {
147         if (i915->conformance_mode > 0) {
148            assert(0);
149            /*             sampler->fallback = true; */
150            /* TODO */
151         }
152      }
153   }
154#endif
155
156   /* See note at the top of file */
157   minlod = sampler->minlod;
158   lastlod = pt->last_level << 4;
159
160   if (lastlod < minlod) {
161      minlod = lastlod;
162   }
163
164   state[1] |= (sampler->minlod << SS3_MIN_LOD_SHIFT);
165   state[1] |= (unit << SS3_TEXTUREMAP_INDEX_SHIFT);
166}
167
168/***********************************************************************
169 * Sampler views
170 */
171
172static uint32_t
173translate_texture_format(enum pipe_format pipeFormat,
174                         const struct pipe_sampler_view *view)
175{
176   if ((view->swizzle_r != PIPE_SWIZZLE_X ||
177        view->swizzle_g != PIPE_SWIZZLE_Y ||
178        view->swizzle_b != PIPE_SWIZZLE_Z ||
179        view->swizzle_a != PIPE_SWIZZLE_W) &&
180       pipeFormat != PIPE_FORMAT_Z24_UNORM_S8_UINT &&
181       pipeFormat != PIPE_FORMAT_Z24X8_UNORM)
182      debug_printf("i915: unsupported texture swizzle for format %d\n",
183                   pipeFormat);
184
185   switch (pipeFormat) {
186   case PIPE_FORMAT_L8_UNORM:
187      return MAPSURF_8BIT | MT_8BIT_L8;
188   case PIPE_FORMAT_I8_UNORM:
189      return MAPSURF_8BIT | MT_8BIT_I8;
190   case PIPE_FORMAT_A8_UNORM:
191      return MAPSURF_8BIT | MT_8BIT_A8;
192   case PIPE_FORMAT_L8A8_UNORM:
193      return MAPSURF_16BIT | MT_16BIT_AY88;
194   case PIPE_FORMAT_B5G6R5_UNORM:
195      return MAPSURF_16BIT | MT_16BIT_RGB565;
196   case PIPE_FORMAT_B5G5R5A1_UNORM:
197      return MAPSURF_16BIT | MT_16BIT_ARGB1555;
198   case PIPE_FORMAT_B4G4R4A4_UNORM:
199      return MAPSURF_16BIT | MT_16BIT_ARGB4444;
200   case PIPE_FORMAT_B10G10R10A2_UNORM:
201      return MAPSURF_32BIT | MT_32BIT_ARGB2101010;
202   case PIPE_FORMAT_B8G8R8A8_UNORM:
203   case PIPE_FORMAT_B8G8R8A8_SRGB:
204      return MAPSURF_32BIT | MT_32BIT_ARGB8888;
205   case PIPE_FORMAT_B8G8R8X8_UNORM:
206      return MAPSURF_32BIT | MT_32BIT_XRGB8888;
207   case PIPE_FORMAT_R8G8B8A8_UNORM:
208      return MAPSURF_32BIT | MT_32BIT_ABGR8888;
209   case PIPE_FORMAT_R8G8B8X8_UNORM:
210      return MAPSURF_32BIT | MT_32BIT_XBGR8888;
211   case PIPE_FORMAT_YUYV:
212      return (MAPSURF_422 | MT_422_YCRCB_NORMAL);
213   case PIPE_FORMAT_UYVY:
214      return (MAPSURF_422 | MT_422_YCRCB_SWAPY);
215   case PIPE_FORMAT_FXT1_RGB:
216   case PIPE_FORMAT_FXT1_RGBA:
217      return (MAPSURF_COMPRESSED | MT_COMPRESS_FXT1);
218   case PIPE_FORMAT_Z16_UNORM:
219      return (MAPSURF_16BIT | MT_16BIT_L16);
220   case PIPE_FORMAT_DXT1_RGB:
221   case PIPE_FORMAT_DXT1_SRGB:
222      return (MAPSURF_COMPRESSED | MT_COMPRESS_DXT1_RGB);
223   case PIPE_FORMAT_DXT1_RGBA:
224   case PIPE_FORMAT_DXT1_SRGBA:
225      return (MAPSURF_COMPRESSED | MT_COMPRESS_DXT1);
226   case PIPE_FORMAT_DXT3_RGBA:
227   case PIPE_FORMAT_DXT3_SRGBA:
228      return (MAPSURF_COMPRESSED | MT_COMPRESS_DXT2_3);
229   case PIPE_FORMAT_DXT5_RGBA:
230   case PIPE_FORMAT_DXT5_SRGBA:
231      return (MAPSURF_COMPRESSED | MT_COMPRESS_DXT4_5);
232   case PIPE_FORMAT_Z24_UNORM_S8_UINT:
233   case PIPE_FORMAT_Z24X8_UNORM: {
234      if (view->swizzle_r == PIPE_SWIZZLE_X &&
235          view->swizzle_g == PIPE_SWIZZLE_X &&
236          view->swizzle_b == PIPE_SWIZZLE_X &&
237          view->swizzle_a == PIPE_SWIZZLE_1)
238         return (MAPSURF_32BIT | MT_32BIT_xL824);
239      if (view->swizzle_r == PIPE_SWIZZLE_X &&
240          view->swizzle_g == PIPE_SWIZZLE_X &&
241          view->swizzle_b == PIPE_SWIZZLE_X &&
242          view->swizzle_a == PIPE_SWIZZLE_X)
243         return (MAPSURF_32BIT | MT_32BIT_xI824);
244      if (view->swizzle_r == PIPE_SWIZZLE_0 &&
245          view->swizzle_g == PIPE_SWIZZLE_0 &&
246          view->swizzle_b == PIPE_SWIZZLE_0 &&
247          view->swizzle_a == PIPE_SWIZZLE_X)
248         return (MAPSURF_32BIT | MT_32BIT_xA824);
249      debug_printf("i915: unsupported depth swizzle %d %d %d %d\n",
250                   view->swizzle_r, view->swizzle_g, view->swizzle_b,
251                   view->swizzle_a);
252      return (MAPSURF_32BIT | MT_32BIT_xL824);
253   }
254   default:
255      debug_printf("i915: translate_texture_format() bad image format %x\n",
256                   pipeFormat);
257      assert(0);
258      return 0;
259   }
260}
261
262static inline uint32_t
263ms3_tiling_bits(enum i915_winsys_buffer_tile tiling)
264{
265   uint32_t tiling_bits = 0;
266
267   switch (tiling) {
268   case I915_TILE_Y:
269      tiling_bits |= MS3_TILE_WALK_Y;
270      FALLTHROUGH;
271   case I915_TILE_X:
272      tiling_bits |= MS3_TILED_SURFACE;
273      FALLTHROUGH;
274   case I915_TILE_NONE:
275      break;
276   }
277
278   return tiling_bits;
279}
280
281static void
282update_map(struct i915_context *i915, uint32_t unit,
283           const struct i915_texture *tex,
284           const struct i915_sampler_state *sampler,
285           const struct pipe_sampler_view *view, uint32_t state[3])
286{
287   const struct pipe_resource *pt = &tex->b;
288   uint32_t width = pt->width0, height = pt->height0, depth = pt->depth0;
289   int first_level = view->u.tex.first_level;
290   const uint32_t num_levels = pt->last_level - first_level;
291   unsigned max_lod = num_levels * 4;
292   bool is_npot = (!util_is_power_of_two_or_zero(pt->width0) ||
293                   !util_is_power_of_two_or_zero(pt->height0));
294   uint32_t format, pitch;
295
296   /*
297    * This is a bit messy. i915 doesn't support NPOT with mipmaps, but we can
298    * still texture from a single level. This is useful to make u_blitter work.
299    */
300   if (is_npot) {
301      width = u_minify(width, first_level);
302      height = u_minify(height, first_level);
303      max_lod = 1;
304   }
305
306   assert(tex);
307   assert(width);
308   assert(height);
309   assert(depth);
310
311   format = translate_texture_format(pt->format, view);
312   pitch = tex->stride;
313
314   assert(format);
315   assert(pitch);
316
317   /* MS3 state */
318   state[0] =
319      (((height - 1) << MS3_HEIGHT_SHIFT) | ((width - 1) << MS3_WIDTH_SHIFT) |
320       format | ms3_tiling_bits(tex->tiling));
321
322   /*
323    * XXX When min_filter != mag_filter and there's just one mipmap level,
324    * set max_lod = 1 to make sure i915 chooses between min/mag filtering.
325    */
326
327   /* See note at the top of file */
328   if (max_lod > (sampler->maxlod >> 2))
329      max_lod = sampler->maxlod >> 2;
330
331   /* MS4 state */
332   state[1] = ((((pitch / 4) - 1) << MS4_PITCH_SHIFT) | MS4_CUBE_FACE_ENA_MASK |
333               ((max_lod) << MS4_MAX_LOD_SHIFT) |
334               ((depth - 1) << MS4_VOLUME_DEPTH_SHIFT));
335
336   if (is_npot)
337      state[2] = i915_texture_offset(tex, first_level, 0);
338   else
339      state[2] = 0;
340}
341
342static void
343update_samplers(struct i915_context *i915)
344{
345   uint32_t unit;
346
347   i915->current.sampler_enable_nr = 0;
348   i915->current.sampler_enable_flags = 0x0;
349
350   for (unit = 0;
351        unit < i915->num_fragment_sampler_views && unit < i915->num_samplers;
352        unit++) {
353      /* determine unit enable/disable by looking for a bound texture */
354      /* could also examine the fragment program? */
355      if (i915->fragment_sampler_views[unit]) {
356         struct i915_texture *texture =
357            i915_texture(i915->fragment_sampler_views[unit]->texture);
358
359         update_sampler(i915, unit,
360                        i915->fragment_sampler[unit],   /* sampler state */
361                        texture,                        /* texture */
362                        i915->current.sampler[unit]);   /* the result */
363         update_map(i915, unit, texture,                /* texture */
364                    i915->fragment_sampler[unit],       /* sampler state */
365                    i915->fragment_sampler_views[unit], /* sampler view */
366                    i915->current.texbuffer[unit]);     /* the result */
367
368         i915->current.sampler_enable_nr++;
369         i915->current.sampler_enable_flags |= (1 << unit);
370      }
371   }
372
373   i915->hardware_dirty |= I915_HW_SAMPLER | I915_HW_MAP;
374}
375
376struct i915_tracked_state i915_hw_samplers = {
377   "samplers", update_samplers, I915_NEW_SAMPLER | I915_NEW_SAMPLER_VIEW};
378