1/* 2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Rob Clark <robclark@freedesktop.org> 25 */ 26 27#include "pipe/p_state.h" 28#include "util/bitset.h" 29#include "util/format/u_format.h" 30#include "util/u_inlines.h" 31#include "util/u_memory.h" 32#include "util/u_string.h" 33 34#include "freedreno_program.h" 35 36#include "fd5_emit.h" 37#include "fd5_format.h" 38#include "fd5_program.h" 39#include "fd5_texture.h" 40 41#include "ir3_cache.h" 42 43void 44fd5_emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so) 45{ 46 const struct ir3_info *si = &so->info; 47 enum a4xx_state_block sb = fd4_stage2shadersb(so->type); 48 enum a4xx_state_src src; 49 uint32_t i, sz, *bin; 50 51 if (FD_DBG(DIRECT)) { 52 sz = si->sizedwords; 53 src = SS4_DIRECT; 54 bin = fd_bo_map(so->bo); 55 } else { 56 sz = 0; 57 src = SS4_INDIRECT; 58 bin = NULL; 59 } 60 61 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + sz); 62 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) | 63 CP_LOAD_STATE4_0_STATE_SRC(src) | 64 CP_LOAD_STATE4_0_STATE_BLOCK(sb) | 65 CP_LOAD_STATE4_0_NUM_UNIT(so->instrlen)); 66 if (bin) { 67 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) | 68 CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER)); 69 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0)); 70 } else { 71 OUT_RELOC(ring, so->bo, 0, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER), 0); 72 } 73 74 /* for how clever coverity is, it is sometimes rather dull, and 75 * doesn't realize that the only case where bin==NULL, sz==0: 76 */ 77 assume(bin || (sz == 0)); 78 79 for (i = 0; i < sz; i++) { 80 OUT_RING(ring, bin[i]); 81 } 82} 83 84/* TODO maybe some of this we could pre-compute once rather than having 85 * so much draw-time logic? 86 */ 87static void 88emit_stream_out(struct fd_ringbuffer *ring, const struct ir3_shader_variant *v, 89 struct ir3_shader_linkage *l) 90{ 91 const struct ir3_stream_output_info *strmout = &v->stream_output; 92 unsigned ncomp[PIPE_MAX_SO_BUFFERS] = {0}; 93 unsigned prog[align(l->max_loc, 2) / 2]; 94 95 memset(prog, 0, sizeof(prog)); 96 97 for (unsigned i = 0; i < strmout->num_outputs; i++) { 98 const struct ir3_stream_output *out = &strmout->output[i]; 99 unsigned k = out->register_index; 100 unsigned idx; 101 102 ncomp[out->output_buffer] += out->num_components; 103 104 /* linkage map sorted by order frag shader wants things, so 105 * a bit less ideal here.. 106 */ 107 for (idx = 0; idx < l->cnt; idx++) 108 if (l->var[idx].slot == v->outputs[k].slot) 109 break; 110 111 assert(idx < l->cnt); 112 113 for (unsigned j = 0; j < out->num_components; j++) { 114 unsigned c = j + out->start_component; 115 unsigned loc = l->var[idx].loc + c; 116 unsigned off = j + out->dst_offset; /* in dwords */ 117 118 if (loc & 1) { 119 prog[loc / 2] |= A5XX_VPC_SO_PROG_B_EN | 120 A5XX_VPC_SO_PROG_B_BUF(out->output_buffer) | 121 A5XX_VPC_SO_PROG_B_OFF(off * 4); 122 } else { 123 prog[loc / 2] |= A5XX_VPC_SO_PROG_A_EN | 124 A5XX_VPC_SO_PROG_A_BUF(out->output_buffer) | 125 A5XX_VPC_SO_PROG_A_OFF(off * 4); 126 } 127 } 128 } 129 130 OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, 12 + (2 * ARRAY_SIZE(prog))); 131 OUT_RING(ring, REG_A5XX_VPC_SO_BUF_CNTL); 132 OUT_RING(ring, A5XX_VPC_SO_BUF_CNTL_ENABLE | 133 COND(ncomp[0] > 0, A5XX_VPC_SO_BUF_CNTL_BUF0) | 134 COND(ncomp[1] > 0, A5XX_VPC_SO_BUF_CNTL_BUF1) | 135 COND(ncomp[2] > 0, A5XX_VPC_SO_BUF_CNTL_BUF2) | 136 COND(ncomp[3] > 0, A5XX_VPC_SO_BUF_CNTL_BUF3)); 137 OUT_RING(ring, REG_A5XX_VPC_SO_NCOMP(0)); 138 OUT_RING(ring, ncomp[0]); 139 OUT_RING(ring, REG_A5XX_VPC_SO_NCOMP(1)); 140 OUT_RING(ring, ncomp[1]); 141 OUT_RING(ring, REG_A5XX_VPC_SO_NCOMP(2)); 142 OUT_RING(ring, ncomp[2]); 143 OUT_RING(ring, REG_A5XX_VPC_SO_NCOMP(3)); 144 OUT_RING(ring, ncomp[3]); 145 OUT_RING(ring, REG_A5XX_VPC_SO_CNTL); 146 OUT_RING(ring, A5XX_VPC_SO_CNTL_ENABLE); 147 for (unsigned i = 0; i < ARRAY_SIZE(prog); i++) { 148 OUT_RING(ring, REG_A5XX_VPC_SO_PROG); 149 OUT_RING(ring, prog[i]); 150 } 151} 152 153struct stage { 154 const struct ir3_shader_variant *v; 155 const struct ir3_info *i; 156 /* const sizes are in units of 4 * vec4 */ 157 uint8_t constoff; 158 uint8_t constlen; 159 /* instr sizes are in units of 16 instructions */ 160 uint8_t instroff; 161 uint8_t instrlen; 162}; 163 164enum { VS = 0, FS = 1, HS = 2, DS = 3, GS = 4, MAX_STAGES }; 165 166static void 167setup_stages(struct fd5_emit *emit, struct stage *s) 168{ 169 unsigned i; 170 171 s[VS].v = fd5_emit_get_vp(emit); 172 s[FS].v = fd5_emit_get_fp(emit); 173 174 s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */ 175 176 for (i = 0; i < MAX_STAGES; i++) { 177 if (s[i].v) { 178 s[i].i = &s[i].v->info; 179 /* constlen is in units of 4 * vec4: */ 180 assert(s[i].v->constlen % 4 == 0); 181 s[i].constlen = s[i].v->constlen / 4; 182 /* instrlen is already in units of 16 instr.. although 183 * probably we should ditch that and not make the compiler 184 * care about instruction group size of a3xx vs a5xx 185 */ 186 s[i].instrlen = s[i].v->instrlen; 187 } else { 188 s[i].i = NULL; 189 s[i].constlen = 0; 190 s[i].instrlen = 0; 191 } 192 } 193 194 /* NOTE: at least for gles2, blob partitions VS at bottom of const 195 * space and FS taking entire remaining space. We probably don't 196 * need to do that the same way, but for now mimic what the blob 197 * does to make it easier to diff against register values from blob 198 * 199 * NOTE: if VS.instrlen + FS.instrlen > 64, then one or both shaders 200 * is run from external memory. 201 */ 202 if ((s[VS].instrlen + s[FS].instrlen) > 64) { 203 /* prioritize FS for internal memory: */ 204 if (s[FS].instrlen < 64) { 205 /* if FS can fit, kick VS out to external memory: */ 206 s[VS].instrlen = 0; 207 } else if (s[VS].instrlen < 64) { 208 /* otherwise if VS can fit, kick out FS: */ 209 s[FS].instrlen = 0; 210 } else { 211 /* neither can fit, run both from external memory: */ 212 s[VS].instrlen = 0; 213 s[FS].instrlen = 0; 214 } 215 } 216 217 unsigned constoff = 0; 218 for (i = 0; i < MAX_STAGES; i++) { 219 s[i].constoff = constoff; 220 constoff += s[i].constlen; 221 } 222 223 s[VS].instroff = 0; 224 s[FS].instroff = 64 - s[FS].instrlen; 225 s[HS].instroff = s[DS].instroff = s[GS].instroff = s[FS].instroff; 226} 227 228static inline uint32_t 229next_regid(uint32_t reg, uint32_t increment) 230{ 231 if (VALIDREG(reg)) 232 return reg + increment; 233 else 234 return regid(63, 0); 235} 236void 237fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring, 238 struct fd5_emit *emit) 239{ 240 struct stage s[MAX_STAGES]; 241 uint32_t pos_regid, psize_regid, color_regid[8]; 242 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid, 243 samp_mask_regid; 244 uint32_t ij_regid[IJ_COUNT], vertex_regid, instance_regid, clip0_regid, 245 clip1_regid; 246 enum a3xx_threadsize fssz; 247 uint8_t psize_loc = ~0; 248 int i, j; 249 250 setup_stages(emit, s); 251 252 bool do_streamout = (s[VS].v->stream_output.num_outputs > 0); 253 uint8_t clip_mask = s[VS].v->clip_mask, 254 cull_mask = s[VS].v->cull_mask; 255 uint8_t clip_cull_mask = clip_mask | cull_mask; 256 257 clip_mask &= ctx->rasterizer->clip_plane_enable; 258 259 fssz = (s[FS].i->double_threadsize) ? FOUR_QUADS : TWO_QUADS; 260 261 pos_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_POS); 262 psize_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_PSIZ); 263 clip0_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_CLIP_DIST0); 264 clip1_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_CLIP_DIST1); 265 vertex_regid = 266 ir3_find_sysval_regid(s[VS].v, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE); 267 instance_regid = ir3_find_sysval_regid(s[VS].v, SYSTEM_VALUE_INSTANCE_ID); 268 269 if (s[FS].v->color0_mrt) { 270 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] = 271 color_regid[4] = color_regid[5] = color_regid[6] = color_regid[7] = 272 ir3_find_output_regid(s[FS].v, FRAG_RESULT_COLOR); 273 } else { 274 color_regid[0] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA0); 275 color_regid[1] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA1); 276 color_regid[2] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA2); 277 color_regid[3] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA3); 278 color_regid[4] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA4); 279 color_regid[5] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA5); 280 color_regid[6] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA6); 281 color_regid[7] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA7); 282 } 283 284 samp_id_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_SAMPLE_ID); 285 samp_mask_regid = 286 ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_SAMPLE_MASK_IN); 287 face_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_FRONT_FACE); 288 coord_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_FRAG_COORD); 289 zwcoord_regid = next_regid(coord_regid, 2); 290 for (unsigned i = 0; i < ARRAY_SIZE(ij_regid); i++) 291 ij_regid[i] = ir3_find_sysval_regid( 292 s[FS].v, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL + i); 293 294 /* we could probably divide this up into things that need to be 295 * emitted if frag-prog is dirty vs if vert-prog is dirty.. 296 */ 297 298 OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CONFIG, 5); 299 OUT_RING(ring, A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET(s[VS].constoff) | 300 A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET(s[VS].instroff) | 301 COND(s[VS].v, A5XX_HLSQ_VS_CONFIG_ENABLED)); 302 OUT_RING(ring, A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET(s[FS].constoff) | 303 A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET(s[FS].instroff) | 304 COND(s[FS].v, A5XX_HLSQ_FS_CONFIG_ENABLED)); 305 OUT_RING(ring, A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET(s[HS].constoff) | 306 A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET(s[HS].instroff) | 307 COND(s[HS].v, A5XX_HLSQ_HS_CONFIG_ENABLED)); 308 OUT_RING(ring, A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET(s[DS].constoff) | 309 A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET(s[DS].instroff) | 310 COND(s[DS].v, A5XX_HLSQ_DS_CONFIG_ENABLED)); 311 OUT_RING(ring, A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET(s[GS].constoff) | 312 A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET(s[GS].instroff) | 313 COND(s[GS].v, A5XX_HLSQ_GS_CONFIG_ENABLED)); 314 315 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONFIG, 1); 316 OUT_RING(ring, 0x00000000); 317 318 OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CNTL, 5); 319 OUT_RING(ring, A5XX_HLSQ_VS_CNTL_INSTRLEN(s[VS].instrlen) | 320 COND(s[VS].v && s[VS].v->has_ssbo, 321 A5XX_HLSQ_VS_CNTL_SSBO_ENABLE)); 322 OUT_RING(ring, A5XX_HLSQ_FS_CNTL_INSTRLEN(s[FS].instrlen) | 323 COND(s[FS].v && s[FS].v->has_ssbo, 324 A5XX_HLSQ_FS_CNTL_SSBO_ENABLE)); 325 OUT_RING(ring, A5XX_HLSQ_HS_CNTL_INSTRLEN(s[HS].instrlen) | 326 COND(s[HS].v && s[HS].v->has_ssbo, 327 A5XX_HLSQ_HS_CNTL_SSBO_ENABLE)); 328 OUT_RING(ring, A5XX_HLSQ_DS_CNTL_INSTRLEN(s[DS].instrlen) | 329 COND(s[DS].v && s[DS].v->has_ssbo, 330 A5XX_HLSQ_DS_CNTL_SSBO_ENABLE)); 331 OUT_RING(ring, A5XX_HLSQ_GS_CNTL_INSTRLEN(s[GS].instrlen) | 332 COND(s[GS].v && s[GS].v->has_ssbo, 333 A5XX_HLSQ_GS_CNTL_SSBO_ENABLE)); 334 335 OUT_PKT4(ring, REG_A5XX_SP_VS_CONFIG, 5); 336 OUT_RING(ring, A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET(s[VS].constoff) | 337 A5XX_SP_VS_CONFIG_SHADEROBJOFFSET(s[VS].instroff) | 338 COND(s[VS].v, A5XX_SP_VS_CONFIG_ENABLED)); 339 OUT_RING(ring, A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET(s[FS].constoff) | 340 A5XX_SP_FS_CONFIG_SHADEROBJOFFSET(s[FS].instroff) | 341 COND(s[FS].v, A5XX_SP_FS_CONFIG_ENABLED)); 342 OUT_RING(ring, A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET(s[HS].constoff) | 343 A5XX_SP_HS_CONFIG_SHADEROBJOFFSET(s[HS].instroff) | 344 COND(s[HS].v, A5XX_SP_HS_CONFIG_ENABLED)); 345 OUT_RING(ring, A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET(s[DS].constoff) | 346 A5XX_SP_DS_CONFIG_SHADEROBJOFFSET(s[DS].instroff) | 347 COND(s[DS].v, A5XX_SP_DS_CONFIG_ENABLED)); 348 OUT_RING(ring, A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET(s[GS].constoff) | 349 A5XX_SP_GS_CONFIG_SHADEROBJOFFSET(s[GS].instroff) | 350 COND(s[GS].v, A5XX_SP_GS_CONFIG_ENABLED)); 351 352 OUT_PKT4(ring, REG_A5XX_SP_CS_CONFIG, 1); 353 OUT_RING(ring, 0x00000000); 354 355 OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CONSTLEN, 2); 356 OUT_RING(ring, s[VS].constlen); /* HLSQ_VS_CONSTLEN */ 357 OUT_RING(ring, s[VS].instrlen); /* HLSQ_VS_INSTRLEN */ 358 359 OUT_PKT4(ring, REG_A5XX_HLSQ_FS_CONSTLEN, 2); 360 OUT_RING(ring, s[FS].constlen); /* HLSQ_FS_CONSTLEN */ 361 OUT_RING(ring, s[FS].instrlen); /* HLSQ_FS_INSTRLEN */ 362 363 OUT_PKT4(ring, REG_A5XX_HLSQ_HS_CONSTLEN, 2); 364 OUT_RING(ring, s[HS].constlen); /* HLSQ_HS_CONSTLEN */ 365 OUT_RING(ring, s[HS].instrlen); /* HLSQ_HS_INSTRLEN */ 366 367 OUT_PKT4(ring, REG_A5XX_HLSQ_DS_CONSTLEN, 2); 368 OUT_RING(ring, s[DS].constlen); /* HLSQ_DS_CONSTLEN */ 369 OUT_RING(ring, s[DS].instrlen); /* HLSQ_DS_INSTRLEN */ 370 371 OUT_PKT4(ring, REG_A5XX_HLSQ_GS_CONSTLEN, 2); 372 OUT_RING(ring, s[GS].constlen); /* HLSQ_GS_CONSTLEN */ 373 OUT_RING(ring, s[GS].instrlen); /* HLSQ_GS_INSTRLEN */ 374 375 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONSTLEN, 2); 376 OUT_RING(ring, 0x00000000); /* HLSQ_CS_CONSTLEN */ 377 OUT_RING(ring, 0x00000000); /* HLSQ_CS_INSTRLEN */ 378 379 OUT_PKT4(ring, REG_A5XX_SP_VS_CTRL_REG0, 1); 380 OUT_RING( 381 ring, 382 A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(s[VS].i->max_half_reg + 1) | 383 A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s[VS].i->max_reg + 1) | 384 COND(s[VS].instrlen != 0, A5XX_SP_VS_CTRL_REG0_BUFFER) | 385 /* XXX: 0x2 is only unset in 386 * dEQP-GLES3.functional.ubo.single_nested_struct_array.single_buffer.packed_instance_array_vertex 387 * on a collection of blob traces. That shader is 1091 instrs, 0 388 * half, 3 full, 108 constlen. Other >1091 instr non-VS shaders don't 389 * unset it, so that's not the trick. 390 */ 391 0x2 | 392 A5XX_SP_VS_CTRL_REG0_BRANCHSTACK(ir3_shader_branchstack_hw(s[VS].v)) | 393 COND(s[VS].v->need_pixlod, A5XX_SP_VS_CTRL_REG0_PIXLODENABLE)); 394 395 /* If we have streamout, link against the real FS in the binning program, 396 * rather than the dummy FS used for binning pass state, to ensure the 397 * OUTLOC's match. Depending on whether we end up doing sysmem or gmem, the 398 * actual streamout could happen with either the binning pass or draw pass 399 * program, but the same streamout stateobj is used in either case: 400 */ 401 const struct ir3_shader_variant *link_fs = s[FS].v; 402 if (do_streamout && emit->binning_pass) 403 link_fs = emit->prog->fs; 404 struct ir3_shader_linkage l = {0}; 405 ir3_link_shaders(&l, s[VS].v, link_fs, true); 406 407 uint8_t clip0_loc = l.clip0_loc; 408 uint8_t clip1_loc = l.clip1_loc; 409 410 OUT_PKT4(ring, REG_A5XX_VPC_VAR_DISABLE(0), 4); 411 OUT_RING(ring, ~l.varmask[0]); /* VPC_VAR[0].DISABLE */ 412 OUT_RING(ring, ~l.varmask[1]); /* VPC_VAR[1].DISABLE */ 413 OUT_RING(ring, ~l.varmask[2]); /* VPC_VAR[2].DISABLE */ 414 OUT_RING(ring, ~l.varmask[3]); /* VPC_VAR[3].DISABLE */ 415 416 /* Add stream out outputs after computing the VPC_VAR_DISABLE bitmask. */ 417 ir3_link_stream_out(&l, s[VS].v); 418 419 /* a5xx appends pos/psize to end of the linkage map: */ 420 if (VALIDREG(pos_regid)) 421 ir3_link_add(&l, VARYING_SLOT_POS, pos_regid, 0xf, l.max_loc); 422 423 if (VALIDREG(psize_regid)) { 424 psize_loc = l.max_loc; 425 ir3_link_add(&l, VARYING_SLOT_PSIZ, psize_regid, 0x1, l.max_loc); 426 } 427 428 /* Handle the case where clip/cull distances aren't read by the FS. Make 429 * sure to avoid adding an output with an empty writemask if the user 430 * disables all the clip distances in the API so that the slot is unused. 431 */ 432 if (clip0_loc == 0xff && VALIDREG(clip0_regid) && 433 (clip_cull_mask & 0xf) != 0) { 434 clip0_loc = l.max_loc; 435 ir3_link_add(&l, VARYING_SLOT_CLIP_DIST0, clip0_regid, 436 clip_cull_mask & 0xf, l.max_loc); 437 } 438 439 if (clip1_loc == 0xff && VALIDREG(clip1_regid) && 440 (clip_cull_mask >> 4) != 0) { 441 clip1_loc = l.max_loc; 442 ir3_link_add(&l, VARYING_SLOT_CLIP_DIST1, clip1_regid, 443 clip_cull_mask >> 4, l.max_loc); 444 } 445 446 /* If we have stream-out, we use the full shader for binning 447 * pass, rather than the optimized binning pass one, so that we 448 * have all the varying outputs available for xfb. So streamout 449 * state should always be derived from the non-binning pass 450 * program: 451 */ 452 if (do_streamout && !emit->binning_pass) 453 emit_stream_out(ring, s[VS].v, &l); 454 455 for (i = 0, j = 0; (i < 16) && (j < l.cnt); i++) { 456 uint32_t reg = 0; 457 458 OUT_PKT4(ring, REG_A5XX_SP_VS_OUT_REG(i), 1); 459 460 reg |= A5XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid); 461 reg |= A5XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask); 462 j++; 463 464 reg |= A5XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid); 465 reg |= A5XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask); 466 j++; 467 468 OUT_RING(ring, reg); 469 } 470 471 for (i = 0, j = 0; (i < 8) && (j < l.cnt); i++) { 472 uint32_t reg = 0; 473 474 OUT_PKT4(ring, REG_A5XX_SP_VS_VPC_DST_REG(i), 1); 475 476 reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc); 477 reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc); 478 reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc); 479 reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc); 480 481 OUT_RING(ring, reg); 482 } 483 484 OUT_PKT4(ring, REG_A5XX_SP_VS_OBJ_START_LO, 2); 485 OUT_RELOC(ring, s[VS].v->bo, 0, 0, 0); /* SP_VS_OBJ_START_LO/HI */ 486 487 if (s[VS].instrlen) 488 fd5_emit_shader(ring, s[VS].v); 489 490 // TODO depending on other bits in this reg (if any) set somewhere else? 491 OUT_PKT4(ring, REG_A5XX_PC_PRIM_VTX_CNTL, 1); 492 OUT_RING(ring, COND(s[VS].v->writes_psize, A5XX_PC_PRIM_VTX_CNTL_PSIZE)); 493 494 OUT_PKT4(ring, REG_A5XX_SP_PRIMITIVE_CNTL, 1); 495 OUT_RING(ring, A5XX_SP_PRIMITIVE_CNTL_VSOUT(l.cnt)); 496 497 OUT_PKT4(ring, REG_A5XX_VPC_CNTL_0, 1); 498 OUT_RING(ring, A5XX_VPC_CNTL_0_STRIDE_IN_VPC(l.max_loc) | 499 COND(s[FS].v->total_in > 0, A5XX_VPC_CNTL_0_VARYING) | 500 0x10000); // XXX 501 502 fd5_context(ctx)->max_loc = l.max_loc; 503 504 if (emit->binning_pass) { 505 OUT_PKT4(ring, REG_A5XX_SP_FS_OBJ_START_LO, 2); 506 OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_LO */ 507 OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_HI */ 508 } else { 509 OUT_PKT4(ring, REG_A5XX_SP_FS_OBJ_START_LO, 2); 510 OUT_RELOC(ring, s[FS].v->bo, 0, 0, 0); /* SP_FS_OBJ_START_LO/HI */ 511 } 512 513 OUT_PKT4(ring, REG_A5XX_HLSQ_CONTROL_0_REG, 5); 514 OUT_RING(ring, A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(fssz) | 515 A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE(TWO_QUADS) | 516 0x00000880); /* XXX HLSQ_CONTROL_0 */ 517 OUT_RING(ring, A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(63)); 518 OUT_RING(ring, A5XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) | 519 A5XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) | 520 A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(samp_mask_regid) | 521 A5XX_HLSQ_CONTROL_2_REG_CENTERRHW(ij_regid[IJ_PERSP_CENTER_RHW])); 522 OUT_RING( 523 ring, 524 A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(ij_regid[IJ_PERSP_PIXEL]) | 525 A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(ij_regid[IJ_LINEAR_PIXEL]) | 526 A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID( 527 ij_regid[IJ_PERSP_CENTROID]) | 528 A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID( 529 ij_regid[IJ_LINEAR_CENTROID])); 530 OUT_RING( 531 ring, 532 A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) | 533 A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) | 534 A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(ij_regid[IJ_PERSP_SAMPLE]) | 535 A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(ij_regid[IJ_LINEAR_SAMPLE])); 536 537 OUT_PKT4(ring, REG_A5XX_SP_FS_CTRL_REG0, 1); 538 OUT_RING( 539 ring, 540 COND(s[FS].v->total_in > 0, A5XX_SP_FS_CTRL_REG0_VARYING) | 541 0x40002 | /* XXX set pretty much everywhere */ 542 COND(s[FS].instrlen != 0, A5XX_SP_FS_CTRL_REG0_BUFFER) | 543 A5XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) | 544 A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(s[FS].i->max_half_reg + 1) | 545 A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s[FS].i->max_reg + 1) | 546 A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(ir3_shader_branchstack_hw(s[FS].v)) | 547 COND(s[FS].v->need_pixlod, A5XX_SP_FS_CTRL_REG0_PIXLODENABLE)); 548 549 OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1); 550 OUT_RING(ring, 0x020fffff); /* XXX */ 551 552 OUT_PKT4(ring, REG_A5XX_VPC_GS_SIV_CNTL, 1); 553 OUT_RING(ring, 0x0000ffff); /* XXX */ 554 555 OUT_PKT4(ring, REG_A5XX_SP_SP_CNTL, 1); 556 OUT_RING(ring, 0x00000010); /* XXX */ 557 558 OUT_PKT4(ring, REG_A5XX_GRAS_CNTL, 1); 559 OUT_RING(ring, 560 CONDREG(ij_regid[IJ_PERSP_PIXEL], A5XX_GRAS_CNTL_IJ_PERSP_PIXEL) | 561 CONDREG(ij_regid[IJ_PERSP_CENTROID], 562 A5XX_GRAS_CNTL_IJ_PERSP_CENTROID) | 563 CONDREG(ij_regid[IJ_PERSP_SAMPLE], 564 A5XX_GRAS_CNTL_IJ_PERSP_SAMPLE) | 565 CONDREG(ij_regid[IJ_LINEAR_PIXEL], A5XX_GRAS_CNTL_IJ_LINEAR_PIXEL) | 566 CONDREG(ij_regid[IJ_LINEAR_CENTROID], 567 A5XX_GRAS_CNTL_IJ_LINEAR_CENTROID) | 568 CONDREG(ij_regid[IJ_LINEAR_SAMPLE], 569 A5XX_GRAS_CNTL_IJ_LINEAR_SAMPLE) | 570 COND(s[FS].v->fragcoord_compmask != 0, 571 A5XX_GRAS_CNTL_COORD_MASK(s[FS].v->fragcoord_compmask) | 572 A5XX_GRAS_CNTL_IJ_LINEAR_PIXEL) | 573 COND(s[FS].v->frag_face, A5XX_GRAS_CNTL_IJ_LINEAR_PIXEL) | 574 CONDREG(ij_regid[IJ_LINEAR_PIXEL], A5XX_GRAS_CNTL_IJ_LINEAR_PIXEL)); 575 576 OUT_PKT4(ring, REG_A5XX_RB_RENDER_CONTROL0, 2); 577 OUT_RING( 578 ring, 579 CONDREG(ij_regid[IJ_PERSP_PIXEL], 580 A5XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL) | 581 CONDREG(ij_regid[IJ_PERSP_CENTROID], 582 A5XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID) | 583 CONDREG(ij_regid[IJ_PERSP_SAMPLE], 584 A5XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE) | 585 CONDREG(ij_regid[IJ_LINEAR_PIXEL], 586 A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL) | 587 CONDREG(ij_regid[IJ_LINEAR_CENTROID], 588 A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_CENTROID) | 589 CONDREG(ij_regid[IJ_LINEAR_SAMPLE], 590 A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE) | 591 COND(s[FS].v->fragcoord_compmask != 0, 592 A5XX_RB_RENDER_CONTROL0_COORD_MASK(s[FS].v->fragcoord_compmask) | 593 A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL) | 594 COND(s[FS].v->frag_face, A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL) | 595 CONDREG(ij_regid[IJ_LINEAR_PIXEL], A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL)); 596 OUT_RING(ring, 597 CONDREG(samp_mask_regid, A5XX_RB_RENDER_CONTROL1_SAMPLEMASK) | 598 COND(s[FS].v->frag_face, A5XX_RB_RENDER_CONTROL1_FACENESS) | 599 CONDREG(samp_id_regid, A5XX_RB_RENDER_CONTROL1_SAMPLEID)); 600 601 OUT_PKT4(ring, REG_A5XX_SP_FS_OUTPUT_REG(0), 8); 602 for (i = 0; i < 8; i++) { 603 OUT_RING(ring, A5XX_SP_FS_OUTPUT_REG_REGID(color_regid[i]) | 604 COND(color_regid[i] & HALF_REG_ID, 605 A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION)); 606 } 607 608 OUT_PKT4(ring, REG_A5XX_VPC_PACK, 1); 609 OUT_RING(ring, A5XX_VPC_PACK_NUMNONPOSVAR(s[FS].v->total_in) | 610 A5XX_VPC_PACK_PSIZELOC(psize_loc)); 611 612 if (!emit->binning_pass) { 613 uint32_t vinterp[8], vpsrepl[8]; 614 615 memset(vinterp, 0, sizeof(vinterp)); 616 memset(vpsrepl, 0, sizeof(vpsrepl)); 617 618 /* looks like we need to do int varyings in the frag 619 * shader on a5xx (no flatshad reg? or a420.0 bug?): 620 * 621 * (sy)(ss)nop 622 * (sy)ldlv.u32 r0.x,l[r0.x], 1 623 * ldlv.u32 r0.y,l[r0.x+1], 1 624 * (ss)bary.f (ei)r63.x, 0, r0.x 625 * (ss)(rpt1)cov.s32f16 hr0.x, (r)r0.x 626 * (rpt5)nop 627 * sam (f16)(xyzw)hr0.x, hr0.x, s#0, t#0 628 * 629 * Possibly on later a5xx variants we'll be able to use 630 * something like the code below instead of workaround 631 * in the shader: 632 */ 633 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */ 634 for (j = -1; 635 (j = ir3_next_varying(s[FS].v, j)) < (int)s[FS].v->inputs_count;) { 636 /* NOTE: varyings are packed, so if compmask is 0xb 637 * then first, third, and fourth component occupy 638 * three consecutive varying slots: 639 */ 640 unsigned compmask = s[FS].v->inputs[j].compmask; 641 642 uint32_t inloc = s[FS].v->inputs[j].inloc; 643 644 if (s[FS].v->inputs[j].flat || 645 (s[FS].v->inputs[j].rasterflat && emit->rasterflat)) { 646 uint32_t loc = inloc; 647 648 for (i = 0; i < 4; i++) { 649 if (compmask & (1 << i)) { 650 vinterp[loc / 16] |= 1 << ((loc % 16) * 2); 651 // flatshade[loc / 32] |= 1 << (loc % 32); 652 loc++; 653 } 654 } 655 } 656 657 bool coord_mode = emit->sprite_coord_mode; 658 if (ir3_point_sprite(s[FS].v, j, emit->sprite_coord_enable, 659 &coord_mode)) { 660 /* mask is two 2-bit fields, where: 661 * '01' -> S 662 * '10' -> T 663 * '11' -> 1 - T (flip mode) 664 */ 665 unsigned mask = coord_mode ? 0b1101 : 0b1001; 666 uint32_t loc = inloc; 667 if (compmask & 0x1) { 668 vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2); 669 loc++; 670 } 671 if (compmask & 0x2) { 672 vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2); 673 loc++; 674 } 675 if (compmask & 0x4) { 676 /* .z <- 0.0f */ 677 vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2); 678 loc++; 679 } 680 if (compmask & 0x8) { 681 /* .w <- 1.0f */ 682 vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2); 683 loc++; 684 } 685 } 686 } 687 688 OUT_PKT4(ring, REG_A5XX_VPC_VARYING_INTERP_MODE(0), 8); 689 for (i = 0; i < 8; i++) 690 OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */ 691 692 OUT_PKT4(ring, REG_A5XX_VPC_VARYING_PS_REPL_MODE(0), 8); 693 for (i = 0; i < 8; i++) 694 OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */ 695 } 696 697 OUT_PKT4(ring, REG_A5XX_GRAS_VS_CL_CNTL, 1); 698 OUT_RING(ring, A5XX_GRAS_VS_CL_CNTL_CLIP_MASK(clip_mask) | 699 A5XX_GRAS_VS_CL_CNTL_CULL_MASK(cull_mask)); 700 701 OUT_PKT4(ring, REG_A5XX_VPC_CLIP_CNTL, 1); 702 OUT_RING(ring, A5XX_VPC_CLIP_CNTL_CLIP_MASK(clip_cull_mask) | 703 A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC(clip0_loc) | 704 A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC(clip1_loc)); 705 706 OUT_PKT4(ring, REG_A5XX_PC_CLIP_CNTL, 1); 707 OUT_RING(ring, A5XX_PC_CLIP_CNTL_CLIP_MASK(clip_mask)); 708 709 if (!emit->binning_pass) 710 if (s[FS].instrlen) 711 fd5_emit_shader(ring, s[FS].v); 712 713 OUT_PKT4(ring, REG_A5XX_VFD_CONTROL_1, 5); 714 OUT_RING(ring, A5XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) | 715 A5XX_VFD_CONTROL_1_REGID4INST(instance_regid) | 0xfc0000); 716 OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_2 */ 717 OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_3 */ 718 OUT_RING(ring, 0x000000fc); /* VFD_CONTROL_4 */ 719 OUT_RING(ring, 0x00000000); /* VFD_CONTROL_5 */ 720} 721 722static struct ir3_program_state * 723fd5_program_create(void *data, struct ir3_shader_variant *bs, 724 struct ir3_shader_variant *vs, struct ir3_shader_variant *hs, 725 struct ir3_shader_variant *ds, struct ir3_shader_variant *gs, 726 struct ir3_shader_variant *fs, 727 const struct ir3_cache_key *key) in_dt 728{ 729 struct fd_context *ctx = fd_context(data); 730 struct fd5_program_state *state = CALLOC_STRUCT(fd5_program_state); 731 732 tc_assert_driver_thread(ctx->tc); 733 734 state->bs = bs; 735 state->vs = vs; 736 state->fs = fs; 737 738 return &state->base; 739} 740 741static void 742fd5_program_destroy(void *data, struct ir3_program_state *state) 743{ 744 struct fd5_program_state *so = fd5_program_state(state); 745 free(so); 746} 747 748static const struct ir3_cache_funcs cache_funcs = { 749 .create_state = fd5_program_create, 750 .destroy_state = fd5_program_destroy, 751}; 752 753void 754fd5_prog_init(struct pipe_context *pctx) 755{ 756 struct fd_context *ctx = fd_context(pctx); 757 758 ctx->shader_cache = ir3_cache_create(&cache_funcs, ctx); 759 ir3_prog_init(pctx); 760 fd_prog_init(pctx); 761} 762