1/* 2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Rob Clark <robclark@freedesktop.org> 25 */ 26 27#include "pipe/p_state.h" 28#include "util/format/u_format.h" 29#include "util/u_helpers.h" 30#include "util/u_memory.h" 31#include "util/u_string.h" 32#include "util/u_viewport.h" 33 34#include "freedreno_query_hw.h" 35#include "freedreno_resource.h" 36 37#include "fd5_blend.h" 38#include "fd5_blitter.h" 39#include "fd5_context.h" 40#include "fd5_emit.h" 41#include "fd5_format.h" 42#include "fd5_image.h" 43#include "fd5_program.h" 44#include "fd5_rasterizer.h" 45#include "fd5_screen.h" 46#include "fd5_texture.h" 47#include "fd5_zsa.h" 48 49#define emit_const_user fd5_emit_const_user 50#define emit_const_bo fd5_emit_const_bo 51#include "ir3_const.h" 52 53/* regid: base const register 54 * prsc or dwords: buffer containing constant values 55 * sizedwords: size of const value buffer 56 */ 57static void 58fd5_emit_const_user(struct fd_ringbuffer *ring, 59 const struct ir3_shader_variant *v, uint32_t regid, 60 uint32_t sizedwords, const uint32_t *dwords) 61{ 62 emit_const_asserts(ring, v, regid, sizedwords); 63 64 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + sizedwords); 65 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid / 4) | 66 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) | 67 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(v->type)) | 68 CP_LOAD_STATE4_0_NUM_UNIT(sizedwords / 4)); 69 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) | 70 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS)); 71 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0)); 72 for (int i = 0; i < sizedwords; i++) 73 OUT_RING(ring, ((uint32_t *)dwords)[i]); 74} 75 76static void 77fd5_emit_const_bo(struct fd_ringbuffer *ring, 78 const struct ir3_shader_variant *v, uint32_t regid, 79 uint32_t offset, uint32_t sizedwords, struct fd_bo *bo) 80{ 81 uint32_t dst_off = regid / 4; 82 assert(dst_off % 4 == 0); 83 uint32_t num_unit = sizedwords / 4; 84 assert(num_unit % 4 == 0); 85 86 emit_const_asserts(ring, v, regid, sizedwords); 87 88 OUT_PKT7(ring, CP_LOAD_STATE4, 3); 89 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(dst_off) | 90 CP_LOAD_STATE4_0_STATE_SRC(SS4_INDIRECT) | 91 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(v->type)) | 92 CP_LOAD_STATE4_0_NUM_UNIT(num_unit)); 93 OUT_RELOC(ring, bo, offset, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS), 0); 94} 95 96static void 97fd5_emit_const_ptrs(struct fd_ringbuffer *ring, gl_shader_stage type, 98 uint32_t regid, uint32_t num, struct fd_bo **bos, 99 uint32_t *offsets) 100{ 101 uint32_t anum = align(num, 2); 102 uint32_t i; 103 104 assert((regid % 4) == 0); 105 106 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (2 * anum)); 107 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid / 4) | 108 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) | 109 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type)) | 110 CP_LOAD_STATE4_0_NUM_UNIT(anum / 2)); 111 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) | 112 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS)); 113 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0)); 114 115 for (i = 0; i < num; i++) { 116 if (bos[i]) { 117 OUT_RELOC(ring, bos[i], offsets[i], 0, 0); 118 } else { 119 OUT_RING(ring, 0xbad00000 | (i << 16)); 120 OUT_RING(ring, 0xbad00000 | (i << 16)); 121 } 122 } 123 124 for (; i < anum; i++) { 125 OUT_RING(ring, 0xffffffff); 126 OUT_RING(ring, 0xffffffff); 127 } 128} 129 130static bool 131is_stateobj(struct fd_ringbuffer *ring) 132{ 133 return false; 134} 135 136static void 137emit_const_ptrs(struct fd_ringbuffer *ring, const struct ir3_shader_variant *v, 138 uint32_t dst_offset, uint32_t num, struct fd_bo **bos, 139 uint32_t *offsets) 140{ 141 /* TODO inline this */ 142 assert(dst_offset + num <= v->constlen * 4); 143 fd5_emit_const_ptrs(ring, v->type, dst_offset, num, bos, offsets); 144} 145 146void 147fd5_emit_cs_consts(const struct ir3_shader_variant *v, 148 struct fd_ringbuffer *ring, struct fd_context *ctx, 149 const struct pipe_grid_info *info) 150{ 151 ir3_emit_cs_consts(v, ring, ctx, info); 152} 153 154/* Border color layout is diff from a4xx/a5xx.. if it turns out to be 155 * the same as a6xx then move this somewhere common ;-) 156 * 157 * Entry layout looks like (total size, 0x60 bytes): 158 */ 159 160struct PACKED bcolor_entry { 161 uint32_t fp32[4]; 162 uint16_t ui16[4]; 163 int16_t si16[4]; 164 165 uint16_t fp16[4]; 166 uint16_t rgb565; 167 uint16_t rgb5a1; 168 uint16_t rgba4; 169 uint8_t __pad0[2]; 170 uint8_t ui8[4]; 171 int8_t si8[4]; 172 uint32_t rgb10a2; 173 uint32_t z24; /* also s8? */ 174 175 uint16_t 176 srgb[4]; /* appears to duplicate fp16[], but clamped, used for srgb */ 177 uint8_t __pad1[24]; 178}; 179 180#define FD5_BORDER_COLOR_SIZE 0x60 181#define FD5_BORDER_COLOR_UPLOAD_SIZE \ 182 (2 * PIPE_MAX_SAMPLERS * FD5_BORDER_COLOR_SIZE) 183 184static void 185setup_border_colors(struct fd_texture_stateobj *tex, 186 struct bcolor_entry *entries) 187{ 188 unsigned i, j; 189 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD5_BORDER_COLOR_SIZE); 190 191 for (i = 0; i < tex->num_samplers; i++) { 192 struct bcolor_entry *e = &entries[i]; 193 struct pipe_sampler_state *sampler = tex->samplers[i]; 194 union pipe_color_union *bc; 195 196 if (!sampler) 197 continue; 198 199 bc = &sampler->border_color; 200 201 /* 202 * XXX HACK ALERT XXX 203 * 204 * The border colors need to be swizzled in a particular 205 * format-dependent order. Even though samplers don't know about 206 * formats, we can assume that with a GL state tracker, there's a 207 * 1:1 correspondence between sampler and texture. Take advantage 208 * of that knowledge. 209 */ 210 if ((i >= tex->num_textures) || !tex->textures[i]) 211 continue; 212 213 enum pipe_format format = tex->textures[i]->format; 214 const struct util_format_description *desc = 215 util_format_description(format); 216 217 e->rgb565 = 0; 218 e->rgb5a1 = 0; 219 e->rgba4 = 0; 220 e->rgb10a2 = 0; 221 e->z24 = 0; 222 223 for (j = 0; j < 4; j++) { 224 int c = desc->swizzle[j]; 225 int cd = c; 226 227 /* 228 * HACK: for PIPE_FORMAT_X24S8_UINT we end up w/ the 229 * stencil border color value in bc->ui[0] but according 230 * to desc->swizzle and desc->channel, the .x component 231 * is NONE and the stencil value is in the y component. 232 * Meanwhile the hardware wants this in the .x componetn. 233 */ 234 if ((format == PIPE_FORMAT_X24S8_UINT) || 235 (format == PIPE_FORMAT_X32_S8X24_UINT)) { 236 if (j == 0) { 237 c = 1; 238 cd = 0; 239 } else { 240 continue; 241 } 242 } 243 244 if (c >= 4) 245 continue; 246 247 if (desc->channel[c].pure_integer) { 248 uint16_t clamped; 249 switch (desc->channel[c].size) { 250 case 2: 251 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED); 252 clamped = CLAMP(bc->ui[j], 0, 0x3); 253 break; 254 case 8: 255 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED) 256 clamped = CLAMP(bc->i[j], -128, 127); 257 else 258 clamped = CLAMP(bc->ui[j], 0, 255); 259 break; 260 case 10: 261 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED); 262 clamped = CLAMP(bc->ui[j], 0, 0x3ff); 263 break; 264 case 16: 265 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED) 266 clamped = CLAMP(bc->i[j], -32768, 32767); 267 else 268 clamped = CLAMP(bc->ui[j], 0, 65535); 269 break; 270 default: 271 assert(!"Unexpected bit size"); 272 case 32: 273 clamped = 0; 274 break; 275 } 276 e->fp32[cd] = bc->ui[j]; 277 e->fp16[cd] = clamped; 278 } else { 279 float f = bc->f[j]; 280 float f_u = CLAMP(f, 0, 1); 281 float f_s = CLAMP(f, -1, 1); 282 283 e->fp32[c] = fui(f); 284 e->fp16[c] = _mesa_float_to_half(f); 285 e->srgb[c] = _mesa_float_to_half(f_u); 286 e->ui16[c] = f_u * 0xffff; 287 e->si16[c] = f_s * 0x7fff; 288 e->ui8[c] = f_u * 0xff; 289 e->si8[c] = f_s * 0x7f; 290 if (c == 1) 291 e->rgb565 |= (int)(f_u * 0x3f) << 5; 292 else if (c < 3) 293 e->rgb565 |= (int)(f_u * 0x1f) << (c ? 11 : 0); 294 if (c == 3) 295 e->rgb5a1 |= (f_u > 0.5f) ? 0x8000 : 0; 296 else 297 e->rgb5a1 |= (int)(f_u * 0x1f) << (c * 5); 298 if (c == 3) 299 e->rgb10a2 |= (int)(f_u * 0x3) << 30; 300 else 301 e->rgb10a2 |= (int)(f_u * 0x3ff) << (c * 10); 302 e->rgba4 |= (int)(f_u * 0xf) << (c * 4); 303 if (c == 0) 304 e->z24 = f_u * 0xffffff; 305 } 306 } 307 308#ifdef DEBUG 309 memset(&e->__pad0, 0, sizeof(e->__pad0)); 310 memset(&e->__pad1, 0, sizeof(e->__pad1)); 311#endif 312 } 313} 314 315static void 316emit_border_color(struct fd_context *ctx, struct fd_ringbuffer *ring) assert_dt 317{ 318 struct fd5_context *fd5_ctx = fd5_context(ctx); 319 struct bcolor_entry *entries; 320 unsigned off; 321 void *ptr; 322 323 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD5_BORDER_COLOR_SIZE); 324 325 u_upload_alloc(fd5_ctx->border_color_uploader, 0, 326 FD5_BORDER_COLOR_UPLOAD_SIZE, FD5_BORDER_COLOR_UPLOAD_SIZE, 327 &off, &fd5_ctx->border_color_buf, &ptr); 328 329 entries = ptr; 330 331 setup_border_colors(&ctx->tex[PIPE_SHADER_VERTEX], &entries[0]); 332 setup_border_colors(&ctx->tex[PIPE_SHADER_FRAGMENT], 333 &entries[ctx->tex[PIPE_SHADER_VERTEX].num_samplers]); 334 335 OUT_PKT4(ring, REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO, 2); 336 OUT_RELOC(ring, fd_resource(fd5_ctx->border_color_buf)->bo, off, 0, 0); 337 338 u_upload_unmap(fd5_ctx->border_color_uploader); 339} 340 341static bool 342emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring, 343 enum a4xx_state_block sb, 344 struct fd_texture_stateobj *tex) assert_dt 345{ 346 bool needs_border = false; 347 unsigned bcolor_offset = 348 (sb == SB4_FS_TEX) ? ctx->tex[PIPE_SHADER_VERTEX].num_samplers : 0; 349 unsigned i; 350 351 if (tex->num_samplers > 0) { 352 /* output sampler state: */ 353 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (4 * tex->num_samplers)); 354 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) | 355 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) | 356 CP_LOAD_STATE4_0_STATE_BLOCK(sb) | 357 CP_LOAD_STATE4_0_NUM_UNIT(tex->num_samplers)); 358 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER) | 359 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0)); 360 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0)); 361 for (i = 0; i < tex->num_samplers; i++) { 362 static const struct fd5_sampler_stateobj dummy_sampler = {}; 363 const struct fd5_sampler_stateobj *sampler = 364 tex->samplers[i] ? fd5_sampler_stateobj(tex->samplers[i]) 365 : &dummy_sampler; 366 OUT_RING(ring, sampler->texsamp0); 367 OUT_RING(ring, sampler->texsamp1); 368 OUT_RING(ring, sampler->texsamp2 | 369 A5XX_TEX_SAMP_2_BCOLOR_OFFSET(bcolor_offset + i)); 370 OUT_RING(ring, sampler->texsamp3); 371 372 needs_border |= sampler->needs_border; 373 } 374 } 375 376 if (tex->num_textures > 0) { 377 unsigned num_textures = tex->num_textures; 378 379 /* emit texture state: */ 380 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (12 * num_textures)); 381 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) | 382 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) | 383 CP_LOAD_STATE4_0_STATE_BLOCK(sb) | 384 CP_LOAD_STATE4_0_NUM_UNIT(num_textures)); 385 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS) | 386 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0)); 387 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0)); 388 for (i = 0; i < tex->num_textures; i++) { 389 static const struct fd5_pipe_sampler_view dummy_view = {}; 390 const struct fd5_pipe_sampler_view *view = 391 tex->textures[i] ? fd5_pipe_sampler_view(tex->textures[i]) 392 : &dummy_view; 393 enum a5xx_tile_mode tile_mode = TILE5_LINEAR; 394 395 if (view->base.texture) 396 tile_mode = fd_resource(view->base.texture)->layout.tile_mode; 397 398 OUT_RING(ring, 399 view->texconst0 | A5XX_TEX_CONST_0_TILE_MODE(tile_mode)); 400 OUT_RING(ring, view->texconst1); 401 OUT_RING(ring, view->texconst2); 402 OUT_RING(ring, view->texconst3); 403 if (view->base.texture) { 404 struct fd_resource *rsc = fd_resource(view->base.texture); 405 if (view->base.format == PIPE_FORMAT_X32_S8X24_UINT) 406 rsc = rsc->stencil; 407 OUT_RELOC(ring, rsc->bo, view->offset, 408 (uint64_t)view->texconst5 << 32, 0); 409 } else { 410 OUT_RING(ring, 0x00000000); 411 OUT_RING(ring, view->texconst5); 412 } 413 OUT_RING(ring, view->texconst6); 414 OUT_RING(ring, view->texconst7); 415 OUT_RING(ring, view->texconst8); 416 OUT_RING(ring, view->texconst9); 417 OUT_RING(ring, view->texconst10); 418 OUT_RING(ring, view->texconst11); 419 } 420 } 421 422 return needs_border; 423} 424 425static void 426emit_ssbos(struct fd_context *ctx, struct fd_ringbuffer *ring, 427 enum a4xx_state_block sb, struct fd_shaderbuf_stateobj *so, 428 const struct ir3_shader_variant *v) 429{ 430 unsigned count = util_last_bit(so->enabled_mask); 431 432 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + 2 * count); 433 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) | 434 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) | 435 CP_LOAD_STATE4_0_STATE_BLOCK(sb) | 436 CP_LOAD_STATE4_0_NUM_UNIT(count)); 437 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS) | 438 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0)); 439 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0)); 440 441 for (unsigned i = 0; i < count; i++) { 442 struct pipe_shader_buffer *buf = &so->sb[i]; 443 unsigned sz = buf->buffer_size; 444 445 /* Unlike a6xx, SSBO size is in bytes. */ 446 OUT_RING(ring, A5XX_SSBO_1_0_WIDTH(sz & MASK(16))); 447 OUT_RING(ring, A5XX_SSBO_1_1_HEIGHT(sz >> 16)); 448 } 449 450 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + 2 * count); 451 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) | 452 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) | 453 CP_LOAD_STATE4_0_STATE_BLOCK(sb) | 454 CP_LOAD_STATE4_0_NUM_UNIT(count)); 455 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_UBO) | 456 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0)); 457 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0)); 458 for (unsigned i = 0; i < count; i++) { 459 struct pipe_shader_buffer *buf = &so->sb[i]; 460 461 if (buf->buffer) { 462 struct fd_resource *rsc = fd_resource(buf->buffer); 463 OUT_RELOC(ring, rsc->bo, buf->buffer_offset, 0, 0); 464 } else { 465 OUT_RING(ring, 0x00000000); 466 OUT_RING(ring, 0x00000000); 467 } 468 } 469} 470 471void 472fd5_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd5_emit *emit) 473{ 474 int32_t i, j; 475 const struct fd_vertex_state *vtx = emit->vtx; 476 const struct ir3_shader_variant *vp = fd5_emit_get_vp(emit); 477 478 for (i = 0, j = 0; i <= vp->inputs_count; i++) { 479 if (vp->inputs[i].sysval) 480 continue; 481 if (vp->inputs[i].compmask) { 482 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i]; 483 const struct pipe_vertex_buffer *vb = 484 &vtx->vertexbuf.vb[elem->vertex_buffer_index]; 485 struct fd_resource *rsc = fd_resource(vb->buffer.resource); 486 enum pipe_format pfmt = elem->src_format; 487 enum a5xx_vtx_fmt fmt = fd5_pipe2vtx(pfmt); 488 bool isint = util_format_is_pure_integer(pfmt); 489 uint32_t off = vb->buffer_offset + elem->src_offset; 490 uint32_t size = vb->buffer.resource->width0 - off; 491 assert(fmt != VFMT5_NONE); 492 493 OUT_PKT4(ring, REG_A5XX_VFD_FETCH(j), 4); 494 OUT_RELOC(ring, rsc->bo, off, 0, 0); 495 OUT_RING(ring, size); /* VFD_FETCH[j].SIZE */ 496 OUT_RING(ring, vb->stride); /* VFD_FETCH[j].STRIDE */ 497 498 OUT_PKT4(ring, REG_A5XX_VFD_DECODE(j), 2); 499 OUT_RING( 500 ring, 501 A5XX_VFD_DECODE_INSTR_IDX(j) | A5XX_VFD_DECODE_INSTR_FORMAT(fmt) | 502 COND(elem->instance_divisor, A5XX_VFD_DECODE_INSTR_INSTANCED) | 503 A5XX_VFD_DECODE_INSTR_SWAP(fd5_pipe2swap(pfmt)) | 504 A5XX_VFD_DECODE_INSTR_UNK30 | 505 COND(!isint, A5XX_VFD_DECODE_INSTR_FLOAT)); 506 OUT_RING( 507 ring, 508 MAX2(1, elem->instance_divisor)); /* VFD_DECODE[j].STEP_RATE */ 509 510 OUT_PKT4(ring, REG_A5XX_VFD_DEST_CNTL(j), 1); 511 OUT_RING(ring, 512 A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vp->inputs[i].compmask) | 513 A5XX_VFD_DEST_CNTL_INSTR_REGID(vp->inputs[i].regid)); 514 515 j++; 516 } 517 } 518 519 OUT_PKT4(ring, REG_A5XX_VFD_CONTROL_0, 1); 520 OUT_RING(ring, A5XX_VFD_CONTROL_0_VTXCNT(j)); 521} 522 523void 524fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring, 525 struct fd5_emit *emit) 526{ 527 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer; 528 const struct ir3_shader_variant *vp = fd5_emit_get_vp(emit); 529 const struct ir3_shader_variant *fp = fd5_emit_get_fp(emit); 530 const enum fd_dirty_3d_state dirty = emit->dirty; 531 bool needs_border = false; 532 533 emit_marker5(ring, 5); 534 535 if ((dirty & FD_DIRTY_FRAMEBUFFER) && !emit->binning_pass) { 536 unsigned char mrt_comp[A5XX_MAX_RENDER_TARGETS] = {0}; 537 538 for (unsigned i = 0; i < A5XX_MAX_RENDER_TARGETS; i++) { 539 mrt_comp[i] = ((i < pfb->nr_cbufs) && pfb->cbufs[i]) ? 0xf : 0; 540 } 541 542 OUT_PKT4(ring, REG_A5XX_RB_RENDER_COMPONENTS, 1); 543 OUT_RING(ring, A5XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) | 544 A5XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) | 545 A5XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) | 546 A5XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) | 547 A5XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) | 548 A5XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) | 549 A5XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) | 550 A5XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7])); 551 } 552 553 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_FRAMEBUFFER)) { 554 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa); 555 uint32_t rb_alpha_control = zsa->rb_alpha_control; 556 557 if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0]))) 558 rb_alpha_control &= ~A5XX_RB_ALPHA_CONTROL_ALPHA_TEST; 559 560 OUT_PKT4(ring, REG_A5XX_RB_ALPHA_CONTROL, 1); 561 OUT_RING(ring, rb_alpha_control); 562 563 OUT_PKT4(ring, REG_A5XX_RB_STENCIL_CONTROL, 1); 564 OUT_RING(ring, zsa->rb_stencil_control); 565 } 566 567 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_BLEND | FD_DIRTY_PROG)) { 568 struct fd5_blend_stateobj *blend = fd5_blend_stateobj(ctx->blend); 569 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa); 570 571 if (pfb->zsbuf) { 572 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture); 573 uint32_t gras_lrz_cntl = zsa->gras_lrz_cntl; 574 575 if (emit->no_lrz_write || !rsc->lrz || !rsc->lrz_valid) 576 gras_lrz_cntl = 0; 577 else if (emit->binning_pass && blend->lrz_write && zsa->lrz_write) 578 gras_lrz_cntl |= A5XX_GRAS_LRZ_CNTL_LRZ_WRITE; 579 580 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1); 581 OUT_RING(ring, gras_lrz_cntl); 582 } 583 } 584 585 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) { 586 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa); 587 struct pipe_stencil_ref *sr = &ctx->stencil_ref; 588 589 OUT_PKT4(ring, REG_A5XX_RB_STENCILREFMASK, 2); 590 OUT_RING(ring, zsa->rb_stencilrefmask | 591 A5XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0])); 592 OUT_RING(ring, zsa->rb_stencilrefmask_bf | 593 A5XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1])); 594 } 595 596 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) { 597 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa); 598 bool fragz = fp->no_earlyz || fp->has_kill || zsa->base.alpha_enabled || 599 fp->writes_pos; 600 601 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_CNTL, 1); 602 OUT_RING(ring, zsa->rb_depth_cntl); 603 604 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_PLANE_CNTL, 1); 605 OUT_RING(ring, COND(fragz, A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z) | 606 COND(fragz && fp->fragcoord_compmask != 0, 607 A5XX_RB_DEPTH_PLANE_CNTL_UNK1)); 608 609 OUT_PKT4(ring, REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL, 1); 610 OUT_RING(ring, COND(fragz, A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z) | 611 COND(fragz && fp->fragcoord_compmask != 0, 612 A5XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1)); 613 } 614 615 /* NOTE: scissor enabled bit is part of rasterizer state: */ 616 if (dirty & (FD_DIRTY_SCISSOR | FD_DIRTY_RASTERIZER)) { 617 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx); 618 619 OUT_PKT4(ring, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2); 620 OUT_RING(ring, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->minx) | 621 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->miny)); 622 OUT_RING(ring, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->maxx - 1) | 623 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->maxy - 1)); 624 625 OUT_PKT4(ring, REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2); 626 OUT_RING(ring, A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->minx) | 627 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->miny)); 628 OUT_RING(ring, 629 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->maxx - 1) | 630 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->maxy - 1)); 631 632 ctx->batch->max_scissor.minx = 633 MIN2(ctx->batch->max_scissor.minx, scissor->minx); 634 ctx->batch->max_scissor.miny = 635 MIN2(ctx->batch->max_scissor.miny, scissor->miny); 636 ctx->batch->max_scissor.maxx = 637 MAX2(ctx->batch->max_scissor.maxx, scissor->maxx); 638 ctx->batch->max_scissor.maxy = 639 MAX2(ctx->batch->max_scissor.maxy, scissor->maxy); 640 } 641 642 if (dirty & FD_DIRTY_VIEWPORT) { 643 fd_wfi(ctx->batch, ring); 644 OUT_PKT4(ring, REG_A5XX_GRAS_CL_VPORT_XOFFSET_0, 6); 645 OUT_RING(ring, A5XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0])); 646 OUT_RING(ring, A5XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0])); 647 OUT_RING(ring, A5XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1])); 648 OUT_RING(ring, A5XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1])); 649 OUT_RING(ring, A5XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2])); 650 OUT_RING(ring, A5XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2])); 651 } 652 653 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_RASTERIZER_CLIP_PLANE_ENABLE)) 654 fd5_program_emit(ctx, ring, emit); 655 656 if (dirty & FD_DIRTY_RASTERIZER) { 657 struct fd5_rasterizer_stateobj *rasterizer = 658 fd5_rasterizer_stateobj(ctx->rasterizer); 659 660 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CNTL, 1); 661 OUT_RING(ring, rasterizer->gras_su_cntl | 662 A5XX_GRAS_SU_CNTL_LINE_MODE(pfb->samples > 1 ? 663 RECTANGULAR : BRESENHAM)); 664 665 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POINT_MINMAX, 2); 666 OUT_RING(ring, rasterizer->gras_su_point_minmax); 667 OUT_RING(ring, rasterizer->gras_su_point_size); 668 669 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE, 3); 670 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale); 671 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset); 672 OUT_RING(ring, rasterizer->gras_su_poly_offset_clamp); 673 674 OUT_PKT4(ring, REG_A5XX_PC_RASTER_CNTL, 1); 675 OUT_RING(ring, rasterizer->pc_raster_cntl); 676 677 OUT_PKT4(ring, REG_A5XX_GRAS_CL_CNTL, 1); 678 OUT_RING(ring, rasterizer->gras_cl_clip_cntl); 679 } 680 681 /* note: must come after program emit.. because there is some overlap 682 * in registers, ex. PC_PRIMITIVE_CNTL and we rely on some cached 683 * values from fd5_program_emit() to avoid having to re-emit the prog 684 * every time rast state changes. 685 * 686 * Since the primitive restart state is not part of a tracked object, we 687 * re-emit this register every time. 688 */ 689 if (emit->info && ctx->rasterizer) { 690 struct fd5_rasterizer_stateobj *rasterizer = 691 fd5_rasterizer_stateobj(ctx->rasterizer); 692 unsigned max_loc = fd5_context(ctx)->max_loc; 693 694 OUT_PKT4(ring, REG_A5XX_PC_PRIMITIVE_CNTL, 1); 695 OUT_RING(ring, 696 rasterizer->pc_primitive_cntl | 697 A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(max_loc) | 698 COND(emit->info->primitive_restart && emit->info->index_size, 699 A5XX_PC_PRIMITIVE_CNTL_PRIMITIVE_RESTART)); 700 } 701 702 if (dirty & (FD_DIRTY_FRAMEBUFFER | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) { 703 uint32_t posz_regid = ir3_find_output_regid(fp, FRAG_RESULT_DEPTH); 704 unsigned nr = pfb->nr_cbufs; 705 706 if (emit->binning_pass) 707 nr = 0; 708 else if (ctx->rasterizer->rasterizer_discard) 709 nr = 0; 710 711 OUT_PKT4(ring, REG_A5XX_RB_FS_OUTPUT_CNTL, 1); 712 OUT_RING(ring, 713 A5XX_RB_FS_OUTPUT_CNTL_MRT(nr) | 714 COND(fp->writes_pos, A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z)); 715 716 OUT_PKT4(ring, REG_A5XX_SP_FS_OUTPUT_CNTL, 1); 717 OUT_RING(ring, A5XX_SP_FS_OUTPUT_CNTL_MRT(nr) | 718 A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(posz_regid) | 719 A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(regid(63, 0))); 720 } 721 722 ir3_emit_vs_consts(vp, ring, ctx, emit->info, emit->indirect, emit->draw); 723 if (!emit->binning_pass) 724 ir3_emit_fs_consts(fp, ring, ctx); 725 726 const struct ir3_stream_output_info *info = &vp->stream_output; 727 if (info->num_outputs) { 728 struct fd_streamout_stateobj *so = &ctx->streamout; 729 730 for (unsigned i = 0; i < so->num_targets; i++) { 731 struct fd_stream_output_target *target = 732 fd_stream_output_target(so->targets[i]); 733 734 if (!target) 735 continue; 736 737 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(i), 3); 738 /* VPC_SO[i].BUFFER_BASE_LO: */ 739 OUT_RELOC(ring, fd_resource(target->base.buffer)->bo, 0, 0, 0); 740 OUT_RING(ring, target->base.buffer_size + target->base.buffer_offset); 741 742 struct fd_bo *offset_bo = fd_resource(target->offset_buf)->bo; 743 744 if (so->reset & (1 << i)) { 745 assert(so->offsets[i] == 0); 746 747 OUT_PKT7(ring, CP_MEM_WRITE, 3); 748 OUT_RELOC(ring, offset_bo, 0, 0, 0); 749 OUT_RING(ring, target->base.buffer_offset); 750 751 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(i), 1); 752 OUT_RING(ring, target->base.buffer_offset); 753 } else { 754 OUT_PKT7(ring, CP_MEM_TO_REG, 3); 755 OUT_RING(ring, 756 CP_MEM_TO_REG_0_REG(REG_A5XX_VPC_SO_BUFFER_OFFSET(i)) | 757 CP_MEM_TO_REG_0_SHIFT_BY_2 | CP_MEM_TO_REG_0_UNK31 | 758 CP_MEM_TO_REG_0_CNT(0)); 759 OUT_RELOC(ring, offset_bo, 0, 0, 0); 760 } 761 762 // After a draw HW would write the new offset to offset_bo 763 OUT_PKT4(ring, REG_A5XX_VPC_SO_FLUSH_BASE_LO(i), 2); 764 OUT_RELOC(ring, offset_bo, 0, 0, 0); 765 766 so->reset &= ~(1 << i); 767 768 emit->streamout_mask |= (1 << i); 769 } 770 } 771 772 if (!emit->streamout_mask && info->num_outputs) { 773 OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, 4); 774 OUT_RING(ring, REG_A5XX_VPC_SO_CNTL); 775 OUT_RING(ring, 0); 776 OUT_RING(ring, REG_A5XX_VPC_SO_BUF_CNTL); 777 OUT_RING(ring, 0); 778 } else if (emit->streamout_mask && !(dirty & FD_DIRTY_PROG)) { 779 /* reemit the program (if we haven't already) to re-enable streamout. We 780 * really should switch to setting up program state at compile time so we 781 * can separate the SO state from the rest, and not recompute all the 782 * time. 783 */ 784 fd5_program_emit(ctx, ring, emit); 785 } 786 787 if (dirty & FD_DIRTY_BLEND) { 788 struct fd5_blend_stateobj *blend = fd5_blend_stateobj(ctx->blend); 789 uint32_t i; 790 791 for (i = 0; i < A5XX_MAX_RENDER_TARGETS; i++) { 792 enum pipe_format format = pipe_surface_format(pfb->cbufs[i]); 793 bool is_int = util_format_is_pure_integer(format); 794 bool has_alpha = util_format_has_alpha(format); 795 uint32_t control = blend->rb_mrt[i].control; 796 797 if (is_int) { 798 control &= A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; 799 control |= A5XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY); 800 } 801 802 if (!has_alpha) { 803 control &= ~A5XX_RB_MRT_CONTROL_BLEND2; 804 } 805 806 OUT_PKT4(ring, REG_A5XX_RB_MRT_CONTROL(i), 1); 807 OUT_RING(ring, control); 808 809 OUT_PKT4(ring, REG_A5XX_RB_MRT_BLEND_CONTROL(i), 1); 810 OUT_RING(ring, blend->rb_mrt[i].blend_control); 811 } 812 813 OUT_PKT4(ring, REG_A5XX_SP_BLEND_CNTL, 1); 814 OUT_RING(ring, blend->sp_blend_cntl); 815 } 816 817 if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_SAMPLE_MASK)) { 818 struct fd5_blend_stateobj *blend = fd5_blend_stateobj(ctx->blend); 819 820 OUT_PKT4(ring, REG_A5XX_RB_BLEND_CNTL, 1); 821 OUT_RING(ring, blend->rb_blend_cntl | 822 A5XX_RB_BLEND_CNTL_SAMPLE_MASK(ctx->sample_mask)); 823 } 824 825 if (dirty & FD_DIRTY_BLEND_COLOR) { 826 struct pipe_blend_color *bcolor = &ctx->blend_color; 827 828 OUT_PKT4(ring, REG_A5XX_RB_BLEND_RED, 8); 829 OUT_RING(ring, A5XX_RB_BLEND_RED_FLOAT(bcolor->color[0]) | 830 A5XX_RB_BLEND_RED_UINT(CLAMP(bcolor->color[0], 0.f, 1.f) * 0xff) | 831 A5XX_RB_BLEND_RED_SINT(CLAMP(bcolor->color[0], -1.f, 1.f) * 0x7f)); 832 OUT_RING(ring, A5XX_RB_BLEND_RED_F32(bcolor->color[0])); 833 OUT_RING(ring, A5XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]) | 834 A5XX_RB_BLEND_GREEN_UINT(CLAMP(bcolor->color[1], 0.f, 1.f) * 0xff) | 835 A5XX_RB_BLEND_GREEN_SINT(CLAMP(bcolor->color[1], -1.f, 1.f) * 0x7f)); 836 OUT_RING(ring, A5XX_RB_BLEND_RED_F32(bcolor->color[1])); 837 OUT_RING(ring, A5XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]) | 838 A5XX_RB_BLEND_BLUE_UINT(CLAMP(bcolor->color[2], 0.f, 1.f) * 0xff) | 839 A5XX_RB_BLEND_BLUE_SINT(CLAMP(bcolor->color[2], -1.f, 1.f) * 0x7f)); 840 OUT_RING(ring, A5XX_RB_BLEND_BLUE_F32(bcolor->color[2])); 841 OUT_RING(ring, A5XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]) | 842 A5XX_RB_BLEND_ALPHA_UINT(CLAMP(bcolor->color[3], 0.f, 1.f) * 0xff) | 843 A5XX_RB_BLEND_ALPHA_SINT(CLAMP(bcolor->color[3], -1.f, 1.f) * 0x7f)); 844 OUT_RING(ring, A5XX_RB_BLEND_ALPHA_F32(bcolor->color[3])); 845 } 846 847 if (ctx->dirty_shader[PIPE_SHADER_VERTEX] & FD_DIRTY_SHADER_TEX) { 848 needs_border |= 849 emit_textures(ctx, ring, SB4_VS_TEX, &ctx->tex[PIPE_SHADER_VERTEX]); 850 OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 1); 851 OUT_RING(ring, ctx->tex[PIPE_SHADER_VERTEX].num_textures); 852 } 853 854 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_TEX) { 855 needs_border |= 856 emit_textures(ctx, ring, SB4_FS_TEX, &ctx->tex[PIPE_SHADER_FRAGMENT]); 857 } 858 859 OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 1); 860 OUT_RING(ring, ctx->shaderimg[PIPE_SHADER_FRAGMENT].enabled_mask 861 ? ~0 862 : ctx->tex[PIPE_SHADER_FRAGMENT].num_textures); 863 864 OUT_PKT4(ring, REG_A5XX_TPL1_CS_TEX_COUNT, 1); 865 OUT_RING(ring, 0); 866 867 if (needs_border) 868 emit_border_color(ctx, ring); 869 870 if (!emit->binning_pass) { 871 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_SSBO) 872 emit_ssbos(ctx, ring, SB4_SSBO, &ctx->shaderbuf[PIPE_SHADER_FRAGMENT], 873 fp); 874 875 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_IMAGE) 876 fd5_emit_images(ctx, ring, PIPE_SHADER_FRAGMENT, fp); 877 } 878} 879 880void 881fd5_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring, 882 struct ir3_shader_variant *cp) 883{ 884 enum fd_dirty_shader_state dirty = ctx->dirty_shader[PIPE_SHADER_COMPUTE]; 885 886 if (dirty & FD_DIRTY_SHADER_TEX) { 887 bool needs_border = false; 888 needs_border |= 889 emit_textures(ctx, ring, SB4_CS_TEX, &ctx->tex[PIPE_SHADER_COMPUTE]); 890 891 if (needs_border) 892 emit_border_color(ctx, ring); 893 894 OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 1); 895 OUT_RING(ring, 0); 896 897 OUT_PKT4(ring, REG_A5XX_TPL1_HS_TEX_COUNT, 1); 898 OUT_RING(ring, 0); 899 900 OUT_PKT4(ring, REG_A5XX_TPL1_DS_TEX_COUNT, 1); 901 OUT_RING(ring, 0); 902 903 OUT_PKT4(ring, REG_A5XX_TPL1_GS_TEX_COUNT, 1); 904 OUT_RING(ring, 0); 905 906 OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 1); 907 OUT_RING(ring, 0); 908 } 909 910 OUT_PKT4(ring, REG_A5XX_TPL1_CS_TEX_COUNT, 1); 911 OUT_RING(ring, ctx->shaderimg[PIPE_SHADER_COMPUTE].enabled_mask 912 ? ~0 913 : ctx->tex[PIPE_SHADER_COMPUTE].num_textures); 914 915 if (dirty & FD_DIRTY_SHADER_SSBO) 916 emit_ssbos(ctx, ring, SB4_CS_SSBO, &ctx->shaderbuf[PIPE_SHADER_COMPUTE], 917 cp); 918 919 if (dirty & FD_DIRTY_SHADER_IMAGE) 920 fd5_emit_images(ctx, ring, PIPE_SHADER_COMPUTE, cp); 921} 922 923/* emit setup at begin of new cmdstream buffer (don't rely on previous 924 * state, there could have been a context switch between ioctls): 925 */ 926void 927fd5_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring) 928{ 929 struct fd_context *ctx = batch->ctx; 930 931 fd5_set_render_mode(ctx, ring, BYPASS); 932 fd5_cache_flush(batch, ring); 933 934 OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1); 935 OUT_RING(ring, 0xfffff); 936 937 /* 938 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords) 939 0000000500024048: 70d08003 00000000 001c5000 00000005 940 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords) 941 0000000500024058: 70d08003 00000010 001c7000 00000005 942 943 t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords) 944 0000000500024068: 70268000 945 */ 946 947 OUT_PKT4(ring, REG_A5XX_PC_RESTART_INDEX, 1); 948 OUT_RING(ring, 0xffffffff); 949 950 OUT_PKT4(ring, REG_A5XX_PC_RASTER_CNTL, 1); 951 OUT_RING(ring, 0x00000012); 952 953 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POINT_MINMAX, 2); 954 OUT_RING(ring, A5XX_GRAS_SU_POINT_MINMAX_MIN(1.0f) | 955 A5XX_GRAS_SU_POINT_MINMAX_MAX(4092.0f)); 956 OUT_RING(ring, A5XX_GRAS_SU_POINT_SIZE(0.5f)); 957 958 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 1); 959 OUT_RING(ring, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */ 960 961 OUT_PKT4(ring, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL, 1); 962 OUT_RING(ring, 0x00000000); /* GRAS_SC_SCREEN_SCISSOR_CNTL */ 963 964 OUT_PKT4(ring, REG_A5XX_SP_VS_CONFIG_MAX_CONST, 1); 965 OUT_RING(ring, 0); /* SP_VS_CONFIG_MAX_CONST */ 966 967 OUT_PKT4(ring, REG_A5XX_SP_FS_CONFIG_MAX_CONST, 1); 968 OUT_RING(ring, 0); /* SP_FS_CONFIG_MAX_CONST */ 969 970 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E292, 2); 971 OUT_RING(ring, 0x00000000); /* UNKNOWN_E292 */ 972 OUT_RING(ring, 0x00000000); /* UNKNOWN_E293 */ 973 974 OUT_PKT4(ring, REG_A5XX_RB_MODE_CNTL, 1); 975 OUT_RING(ring, 0x00000044); /* RB_MODE_CNTL */ 976 977 OUT_PKT4(ring, REG_A5XX_RB_DBG_ECO_CNTL, 1); 978 OUT_RING(ring, 0x00100000); /* RB_DBG_ECO_CNTL */ 979 980 OUT_PKT4(ring, REG_A5XX_VFD_MODE_CNTL, 1); 981 OUT_RING(ring, 0x00000000); /* VFD_MODE_CNTL */ 982 983 OUT_PKT4(ring, REG_A5XX_PC_MODE_CNTL, 1); 984 OUT_RING(ring, 0x0000001f); /* PC_MODE_CNTL */ 985 986 OUT_PKT4(ring, REG_A5XX_SP_MODE_CNTL, 1); 987 OUT_RING(ring, 0x0000001e); /* SP_MODE_CNTL */ 988 989 if (ctx->screen->gpu_id == 540) { 990 OUT_PKT4(ring, REG_A5XX_SP_DBG_ECO_CNTL, 1); 991 OUT_RING(ring, 0x800); /* SP_DBG_ECO_CNTL */ 992 993 OUT_PKT4(ring, REG_A5XX_HLSQ_DBG_ECO_CNTL, 1); 994 OUT_RING(ring, 0x0); 995 996 OUT_PKT4(ring, REG_A5XX_VPC_DBG_ECO_CNTL, 1); 997 OUT_RING(ring, 0x800400); 998 } else { 999 OUT_PKT4(ring, REG_A5XX_SP_DBG_ECO_CNTL, 1); 1000 OUT_RING(ring, 0x40000800); /* SP_DBG_ECO_CNTL */ 1001 } 1002 1003 OUT_PKT4(ring, REG_A5XX_TPL1_MODE_CNTL, 1); 1004 OUT_RING(ring, 0x00000544); /* TPL1_MODE_CNTL */ 1005 1006 OUT_PKT4(ring, REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0, 2); 1007 OUT_RING(ring, 0x00000080); /* HLSQ_TIMEOUT_THRESHOLD_0 */ 1008 OUT_RING(ring, 0x00000000); /* HLSQ_TIMEOUT_THRESHOLD_1 */ 1009 1010 OUT_PKT4(ring, REG_A5XX_VPC_DBG_ECO_CNTL, 1); 1011 OUT_RING(ring, 0x00000400); /* VPC_DBG_ECO_CNTL */ 1012 1013 OUT_PKT4(ring, REG_A5XX_HLSQ_MODE_CNTL, 1); 1014 OUT_RING(ring, 0x00000001); /* HLSQ_MODE_CNTL */ 1015 1016 OUT_PKT4(ring, REG_A5XX_VPC_MODE_CNTL, 1); 1017 OUT_RING(ring, 0x00000000); /* VPC_MODE_CNTL */ 1018 1019 /* we don't use this yet.. probably best to disable.. */ 1020 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3); 1021 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) | 1022 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS | 1023 CP_SET_DRAW_STATE__0_GROUP_ID(0)); 1024 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0)); 1025 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0)); 1026 1027 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 1); 1028 OUT_RING(ring, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */ 1029 1030 OUT_PKT4(ring, REG_A5XX_GRAS_SC_BIN_CNTL, 1); 1031 OUT_RING(ring, 0x00000000); /* GRAS_SC_BIN_CNTL */ 1032 1033 OUT_PKT4(ring, REG_A5XX_GRAS_SC_BIN_CNTL, 1); 1034 OUT_RING(ring, 0x00000000); /* GRAS_SC_BIN_CNTL */ 1035 1036 OUT_PKT4(ring, REG_A5XX_VPC_FS_PRIMITIVEID_CNTL, 1); 1037 OUT_RING(ring, 0x000000ff); /* VPC_FS_PRIMITIVEID_CNTL */ 1038 1039 OUT_PKT4(ring, REG_A5XX_VPC_SO_OVERRIDE, 1); 1040 OUT_RING(ring, A5XX_VPC_SO_OVERRIDE_SO_DISABLE); 1041 1042 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(0), 3); 1043 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */ 1044 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */ 1045 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */ 1046 1047 OUT_PKT4(ring, REG_A5XX_VPC_SO_FLUSH_BASE_LO(0), 2); 1048 OUT_RING(ring, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */ 1049 OUT_RING(ring, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */ 1050 1051 OUT_PKT4(ring, REG_A5XX_PC_GS_PARAM, 1); 1052 OUT_RING(ring, 0x00000000); /* PC_GS_PARAM */ 1053 1054 OUT_PKT4(ring, REG_A5XX_PC_HS_PARAM, 1); 1055 OUT_RING(ring, 0x00000000); /* PC_HS_PARAM */ 1056 1057 OUT_PKT4(ring, REG_A5XX_TPL1_TP_FS_ROTATION_CNTL, 1); 1058 OUT_RING(ring, 0x00000000); /* TPL1_TP_FS_ROTATION_CNTL */ 1059 1060 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E004, 1); 1061 OUT_RING(ring, 0x00000000); /* UNKNOWN_E004 */ 1062 1063 OUT_PKT4(ring, REG_A5XX_GRAS_SU_LAYERED, 1); 1064 OUT_RING(ring, 0x00000000); /* GRAS_SU_LAYERED */ 1065 1066 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUF_CNTL, 1); 1067 OUT_RING(ring, 0x00000000); /* VPC_SO_BUF_CNTL */ 1068 1069 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(0), 1); 1070 OUT_RING(ring, 0x00000000); /* UNKNOWN_E2AB */ 1071 1072 OUT_PKT4(ring, REG_A5XX_PC_GS_LAYERED, 1); 1073 OUT_RING(ring, 0x00000000); /* PC_GS_LAYERED */ 1074 1075 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5AB, 1); 1076 OUT_RING(ring, 0x00000000); /* UNKNOWN_E5AB */ 1077 1078 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5C2, 1); 1079 OUT_RING(ring, 0x00000000); /* UNKNOWN_E5C2 */ 1080 1081 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(1), 3); 1082 OUT_RING(ring, 0x00000000); 1083 OUT_RING(ring, 0x00000000); 1084 OUT_RING(ring, 0x00000000); 1085 1086 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(1), 6); 1087 OUT_RING(ring, 0x00000000); 1088 OUT_RING(ring, 0x00000000); 1089 OUT_RING(ring, 0x00000000); 1090 OUT_RING(ring, 0x00000000); 1091 OUT_RING(ring, 0x00000000); 1092 OUT_RING(ring, 0x00000000); 1093 1094 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(2), 6); 1095 OUT_RING(ring, 0x00000000); 1096 OUT_RING(ring, 0x00000000); 1097 OUT_RING(ring, 0x00000000); 1098 OUT_RING(ring, 0x00000000); 1099 OUT_RING(ring, 0x00000000); 1100 OUT_RING(ring, 0x00000000); 1101 1102 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(3), 3); 1103 OUT_RING(ring, 0x00000000); 1104 OUT_RING(ring, 0x00000000); 1105 OUT_RING(ring, 0x00000000); 1106 1107 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5DB, 1); 1108 OUT_RING(ring, 0x00000000); 1109 1110 OUT_PKT4(ring, REG_A5XX_SP_HS_CTRL_REG0, 1); 1111 OUT_RING(ring, 0x00000000); 1112 1113 OUT_PKT4(ring, REG_A5XX_SP_GS_CTRL_REG0, 1); 1114 OUT_RING(ring, 0x00000000); 1115 1116 OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 4); 1117 OUT_RING(ring, 0x00000000); 1118 OUT_RING(ring, 0x00000000); 1119 OUT_RING(ring, 0x00000000); 1120 OUT_RING(ring, 0x00000000); 1121 1122 OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 2); 1123 OUT_RING(ring, 0x00000000); 1124 OUT_RING(ring, 0x00000000); 1125 1126 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7C0, 3); 1127 OUT_RING(ring, 0x00000000); 1128 OUT_RING(ring, 0x00000000); 1129 OUT_RING(ring, 0x00000000); 1130 1131 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7C5, 3); 1132 OUT_RING(ring, 0x00000000); 1133 OUT_RING(ring, 0x00000000); 1134 OUT_RING(ring, 0x00000000); 1135 1136 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7CA, 3); 1137 OUT_RING(ring, 0x00000000); 1138 OUT_RING(ring, 0x00000000); 1139 OUT_RING(ring, 0x00000000); 1140 1141 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7CF, 3); 1142 OUT_RING(ring, 0x00000000); 1143 OUT_RING(ring, 0x00000000); 1144 OUT_RING(ring, 0x00000000); 1145 1146 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7D4, 3); 1147 OUT_RING(ring, 0x00000000); 1148 OUT_RING(ring, 0x00000000); 1149 OUT_RING(ring, 0x00000000); 1150 1151 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7D9, 3); 1152 OUT_RING(ring, 0x00000000); 1153 OUT_RING(ring, 0x00000000); 1154 OUT_RING(ring, 0x00000000); 1155 1156 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1); 1157 OUT_RING(ring, 0x00000000); 1158} 1159 1160static void 1161fd5_mem_to_mem(struct fd_ringbuffer *ring, struct pipe_resource *dst, 1162 unsigned dst_off, struct pipe_resource *src, unsigned src_off, 1163 unsigned sizedwords) 1164{ 1165 struct fd_bo *src_bo = fd_resource(src)->bo; 1166 struct fd_bo *dst_bo = fd_resource(dst)->bo; 1167 unsigned i; 1168 1169 for (i = 0; i < sizedwords; i++) { 1170 OUT_PKT7(ring, CP_MEM_TO_MEM, 5); 1171 OUT_RING(ring, 0x00000000); 1172 OUT_RELOC(ring, dst_bo, dst_off, 0, 0); 1173 OUT_RELOC(ring, src_bo, src_off, 0, 0); 1174 1175 dst_off += 4; 1176 src_off += 4; 1177 } 1178} 1179 1180void 1181fd5_emit_init_screen(struct pipe_screen *pscreen) 1182{ 1183 struct fd_screen *screen = fd_screen(pscreen); 1184 screen->emit_ib = fd5_emit_ib; 1185 screen->mem_to_mem = fd5_mem_to_mem; 1186} 1187 1188void 1189fd5_emit_init(struct pipe_context *pctx) 1190{ 1191} 1192